Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99821902	1			T2	1637		T3	60766		T13	16066
all_pins[1]	99821902	1			T2	1637		T3	60766		T13	16066
all_pins[2]	99821902	1			T2	1637		T3	60766		T13	16066

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298678432	1			T2	4666		T3	177782		T13	48037
values[0x1]	787274	1			T2	245		T3	4516		T13	161
transitions[0x0=>0x1]	785614	1			T2	245		T3	4488		T13	161
transitions[0x1=>0x0]	785639	1			T2	245		T3	4489		T13	161

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99317258	1			T2	1392		T3	60489		T13	15905
all_pins[0]	values[0x1]	504644	1			T2	245		T3	277		T13	161
all_pins[0]	transitions[0x0=>0x1]	504629	1			T2	245		T3	277		T13	161
all_pins[0]	transitions[0x1=>0x0]	56	1			T36	3		T37	3		T38	8
all_pins[1]	values[0x0]	99821831	1			T2	1637		T3	60766		T13	16066
all_pins[1]	values[0x1]	71	1			T36	3		T37	3		T38	8
all_pins[1]	transitions[0x0=>0x1]	60	1			T36	3		T37	3		T38	8
all_pins[1]	transitions[0x1=>0x0]	282548	1			T3	4239		T22	3049		T26	479
all_pins[2]	values[0x0]	99539343	1			T2	1637		T3	56527		T13	16066
all_pins[2]	values[0x1]	282559	1			T3	4239		T22	3049		T26	479
all_pins[2]	transitions[0x0=>0x1]	280925	1			T3	4211		T22	3028		T26	479
all_pins[2]	transitions[0x1=>0x0]	503035	1			T2	245		T3	250		T13	161