Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10256570 |
1 |
|
|
T2 |
6224 |
|
T3 |
23222 |
|
T13 |
17191 |
auto[1] |
25047550 |
1 |
|
|
T2 |
11576 |
|
T3 |
36096 |
|
T13 |
25504 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
35186943 |
1 |
|
|
T2 |
17692 |
|
T3 |
59209 |
|
T13 |
42618 |
triple_byte_access |
38885 |
1 |
|
|
T2 |
34 |
|
T3 |
33 |
|
T13 |
24 |
halfword_access |
39291 |
1 |
|
|
T2 |
39 |
|
T3 |
32 |
|
T13 |
26 |
byte_access |
39001 |
1 |
|
|
T2 |
35 |
|
T3 |
44 |
|
T13 |
27 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10139393 |
1 |
|
|
T2 |
6116 |
|
T3 |
23113 |
|
T13 |
17114 |
auto[0] |
triple_byte_access |
38885 |
1 |
|
|
T2 |
34 |
|
T3 |
33 |
|
T13 |
24 |
auto[0] |
halfword_access |
39291 |
1 |
|
|
T2 |
39 |
|
T3 |
32 |
|
T13 |
26 |
auto[0] |
byte_access |
39001 |
1 |
|
|
T2 |
35 |
|
T3 |
44 |
|
T13 |
27 |
auto[1] |
word_access |
25047550 |
1 |
|
|
T2 |
11576 |
|
T3 |
36096 |
|
T13 |
25504 |