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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.02 95.91 92.34 100.00 66.12 94.19 99.00 96.58


Total test records in report: 1235
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T1056 /workspace/coverage/default/3.kmac_key_error.1590209710 Jun 30 05:51:49 PM PDT 24 Jun 30 05:51:58 PM PDT 24 1788963420 ps
T1057 /workspace/coverage/default/42.kmac_entropy_refresh.3996491903 Jun 30 05:59:17 PM PDT 24 Jun 30 06:01:01 PM PDT 24 9344508224 ps
T1058 /workspace/coverage/default/49.kmac_test_vectors_shake_256.3503253379 Jun 30 06:02:12 PM PDT 24 Jun 30 06:59:16 PM PDT 24 44514262005 ps
T1059 /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.385790771 Jun 30 05:52:01 PM PDT 24 Jun 30 05:52:07 PM PDT 24 251889133 ps
T1060 /workspace/coverage/default/17.kmac_test_vectors_shake_128.3601648224 Jun 30 05:53:45 PM PDT 24 Jun 30 07:10:46 PM PDT 24 1545093758621 ps
T1061 /workspace/coverage/default/18.kmac_edn_timeout_error.3799373379 Jun 30 05:54:04 PM PDT 24 Jun 30 05:54:39 PM PDT 24 2846230004 ps
T1062 /workspace/coverage/default/22.kmac_alert_test.2661699992 Jun 30 05:54:36 PM PDT 24 Jun 30 05:54:37 PM PDT 24 50297014 ps
T1063 /workspace/coverage/default/0.kmac_long_msg_and_output.4247821490 Jun 30 05:51:25 PM PDT 24 Jun 30 06:16:32 PM PDT 24 53799348431 ps
T1064 /workspace/coverage/default/14.kmac_key_error.3439502164 Jun 30 05:53:19 PM PDT 24 Jun 30 05:53:22 PM PDT 24 662398926 ps
T1065 /workspace/coverage/default/22.kmac_test_vectors_shake_256.4274140678 Jun 30 05:54:35 PM PDT 24 Jun 30 06:57:18 PM PDT 24 151202544221 ps
T1066 /workspace/coverage/default/0.kmac_test_vectors_kmac.3750885635 Jun 30 05:51:26 PM PDT 24 Jun 30 05:51:30 PM PDT 24 67581211 ps
T1067 /workspace/coverage/default/35.kmac_entropy_refresh.2642021556 Jun 30 05:57:08 PM PDT 24 Jun 30 06:00:04 PM PDT 24 4314551149 ps
T1068 /workspace/coverage/default/8.kmac_burst_write.3390688029 Jun 30 05:52:25 PM PDT 24 Jun 30 05:55:56 PM PDT 24 3661988922 ps
T1069 /workspace/coverage/default/16.kmac_test_vectors_shake_128.4274530243 Jun 30 05:53:38 PM PDT 24 Jun 30 07:00:20 PM PDT 24 53179802521 ps
T1070 /workspace/coverage/default/9.kmac_test_vectors_sha3_256.364650094 Jun 30 05:52:36 PM PDT 24 Jun 30 06:24:49 PM PDT 24 375788866659 ps
T1071 /workspace/coverage/default/41.kmac_test_vectors_shake_128.2109712613 Jun 30 05:58:46 PM PDT 24 Jun 30 07:19:51 PM PDT 24 232533843745 ps
T1072 /workspace/coverage/default/41.kmac_test_vectors_sha3_224.3274847235 Jun 30 05:58:40 PM PDT 24 Jun 30 06:24:29 PM PDT 24 19925473821 ps
T1073 /workspace/coverage/default/13.kmac_stress_all.4234936549 Jun 30 05:53:14 PM PDT 24 Jun 30 06:00:08 PM PDT 24 87168361188 ps
T1074 /workspace/coverage/default/30.kmac_entropy_refresh.948727394 Jun 30 05:55:55 PM PDT 24 Jun 30 05:59:18 PM PDT 24 42564016166 ps
T1075 /workspace/coverage/default/24.kmac_burst_write.3169794474 Jun 30 05:54:53 PM PDT 24 Jun 30 05:56:02 PM PDT 24 3292415221 ps
T1076 /workspace/coverage/default/41.kmac_test_vectors_sha3_512.2770933632 Jun 30 05:58:45 PM PDT 24 Jun 30 06:13:36 PM PDT 24 63826264930 ps
T1077 /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3051343371 Jun 30 05:52:16 PM PDT 24 Jun 30 06:09:58 PM PDT 24 111329332514 ps
T1078 /workspace/coverage/default/48.kmac_error.690233701 Jun 30 06:01:56 PM PDT 24 Jun 30 06:04:22 PM PDT 24 6975162678 ps
T182 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1613415091 Jun 30 05:03:36 PM PDT 24 Jun 30 05:03:37 PM PDT 24 30229827 ps
T119 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.466556321 Jun 30 05:03:03 PM PDT 24 Jun 30 05:03:05 PM PDT 24 280721978 ps
T1079 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2847595597 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:02 PM PDT 24 96966257 ps
T145 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1553303719 Jun 30 05:03:56 PM PDT 24 Jun 30 05:03:57 PM PDT 24 197962882 ps
T183 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3345506543 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:12 PM PDT 24 387691313 ps
T112 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3920282443 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:15 PM PDT 24 850336674 ps
T1080 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2796575846 Jun 30 05:03:11 PM PDT 24 Jun 30 05:03:12 PM PDT 24 52285087 ps
T115 /workspace/coverage/cover_reg_top/6.kmac_intr_test.816449843 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:45 PM PDT 24 22633643 ps
T120 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2849023691 Jun 30 05:03:09 PM PDT 24 Jun 30 05:03:12 PM PDT 24 81336732 ps
T116 /workspace/coverage/cover_reg_top/42.kmac_intr_test.578743582 Jun 30 05:04:25 PM PDT 24 Jun 30 05:04:27 PM PDT 24 15957242 ps
T117 /workspace/coverage/cover_reg_top/13.kmac_intr_test.1643836114 Jun 30 05:03:57 PM PDT 24 Jun 30 05:03:58 PM PDT 24 14904809 ps
T184 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2307086731 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:20 PM PDT 24 1531393695 ps
T121 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.111565347 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:04 PM PDT 24 92045661 ps
T122 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.202736880 Jun 30 05:03:45 PM PDT 24 Jun 30 05:03:49 PM PDT 24 129984987 ps
T168 /workspace/coverage/cover_reg_top/24.kmac_intr_test.4284038743 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:21 PM PDT 24 33257032 ps
T96 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1239322725 Jun 30 05:03:57 PM PDT 24 Jun 30 05:03:58 PM PDT 24 291280388 ps
T113 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2428186191 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:03 PM PDT 24 548953559 ps
T1081 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2511038052 Jun 30 05:03:45 PM PDT 24 Jun 30 05:03:48 PM PDT 24 87263649 ps
T146 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3784926258 Jun 30 05:04:12 PM PDT 24 Jun 30 05:04:15 PM PDT 24 484103154 ps
T132 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2104018601 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:46 PM PDT 24 94620879 ps
T1082 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.563409209 Jun 30 05:03:42 PM PDT 24 Jun 30 05:03:45 PM PDT 24 25243964 ps
T152 /workspace/coverage/cover_reg_top/40.kmac_intr_test.4170640964 Jun 30 05:04:25 PM PDT 24 Jun 30 05:04:26 PM PDT 24 14497011 ps
T1083 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.733335298 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:03 PM PDT 24 18799650 ps
T97 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.233322333 Jun 30 05:03:37 PM PDT 24 Jun 30 05:03:39 PM PDT 24 35333114 ps
T154 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.636927401 Jun 30 05:03:35 PM PDT 24 Jun 30 05:03:39 PM PDT 24 151932644 ps
T114 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3037125957 Jun 30 05:03:45 PM PDT 24 Jun 30 05:03:50 PM PDT 24 173582025 ps
T1084 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.50949917 Jun 30 05:03:42 PM PDT 24 Jun 30 05:03:43 PM PDT 24 14973396 ps
T1085 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4013476321 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:12 PM PDT 24 56289743 ps
T99 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3707128456 Jun 30 05:03:21 PM PDT 24 Jun 30 05:03:22 PM PDT 24 40306132 ps
T1086 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1752167571 Jun 30 05:03:42 PM PDT 24 Jun 30 05:03:45 PM PDT 24 36259986 ps
T1087 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.260338720 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:53 PM PDT 24 49524535 ps
T108 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.774194125 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:11 PM PDT 24 26432875 ps
T147 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2458863020 Jun 30 05:03:57 PM PDT 24 Jun 30 05:04:00 PM PDT 24 127167875 ps
T1088 /workspace/coverage/cover_reg_top/34.kmac_intr_test.2787467027 Jun 30 05:04:20 PM PDT 24 Jun 30 05:04:21 PM PDT 24 14950490 ps
T1089 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.739360612 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:02 PM PDT 24 313080138 ps
T1090 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3535040257 Jun 30 05:03:55 PM PDT 24 Jun 30 05:03:58 PM PDT 24 204297209 ps
T1091 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3518256528 Jun 30 05:03:12 PM PDT 24 Jun 30 05:03:14 PM PDT 24 101940572 ps
T109 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3981132157 Jun 30 05:02:54 PM PDT 24 Jun 30 05:02:55 PM PDT 24 399770188 ps
T1092 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.740817628 Jun 30 05:03:52 PM PDT 24 Jun 30 05:03:53 PM PDT 24 60705366 ps
T169 /workspace/coverage/cover_reg_top/17.kmac_intr_test.220772704 Jun 30 05:04:07 PM PDT 24 Jun 30 05:04:08 PM PDT 24 22618418 ps
T98 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3961229520 Jun 30 05:03:52 PM PDT 24 Jun 30 05:03:55 PM PDT 24 112626548 ps
T1093 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3191240296 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:12 PM PDT 24 22147980 ps
T148 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2379999929 Jun 30 05:03:09 PM PDT 24 Jun 30 05:03:12 PM PDT 24 115857818 ps
T149 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.982878625 Jun 30 05:03:44 PM PDT 24 Jun 30 05:03:45 PM PDT 24 73138671 ps
T104 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1818527997 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:45 PM PDT 24 751017559 ps
T1094 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.35509981 Jun 30 05:03:52 PM PDT 24 Jun 30 05:03:55 PM PDT 24 52713198 ps
T103 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2170269147 Jun 30 05:03:44 PM PDT 24 Jun 30 05:03:46 PM PDT 24 252548811 ps
T176 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3546325089 Jun 30 05:03:57 PM PDT 24 Jun 30 05:04:03 PM PDT 24 196049483 ps
T105 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.517788968 Jun 30 05:03:35 PM PDT 24 Jun 30 05:03:36 PM PDT 24 84262091 ps
T150 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2785427426 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:00 PM PDT 24 58753267 ps
T170 /workspace/coverage/cover_reg_top/36.kmac_intr_test.3499993116 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:20 PM PDT 24 16595632 ps
T1095 /workspace/coverage/cover_reg_top/33.kmac_intr_test.3673707387 Jun 30 05:04:20 PM PDT 24 Jun 30 05:04:22 PM PDT 24 26783443 ps
T153 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1823087451 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:04 PM PDT 24 68343326 ps
T100 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1384654502 Jun 30 05:03:35 PM PDT 24 Jun 30 05:03:37 PM PDT 24 45587328 ps
T1096 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1425646105 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:19 PM PDT 24 1199911425 ps
T1097 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3739207074 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:20 PM PDT 24 78243188 ps
T172 /workspace/coverage/cover_reg_top/43.kmac_intr_test.656596289 Jun 30 05:04:30 PM PDT 24 Jun 30 05:04:31 PM PDT 24 40348059 ps
T1098 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3593693996 Jun 30 05:03:16 PM PDT 24 Jun 30 05:03:24 PM PDT 24 132611135 ps
T1099 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1258107679 Jun 30 05:04:13 PM PDT 24 Jun 30 05:04:15 PM PDT 24 20127066 ps
T102 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1580742067 Jun 30 05:03:17 PM PDT 24 Jun 30 05:03:20 PM PDT 24 240565021 ps
T171 /workspace/coverage/cover_reg_top/35.kmac_intr_test.989896251 Jun 30 05:04:20 PM PDT 24 Jun 30 05:04:21 PM PDT 24 47166184 ps
T136 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3835241031 Jun 30 05:03:27 PM PDT 24 Jun 30 05:03:29 PM PDT 24 112605772 ps
T1100 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1813388510 Jun 30 05:03:49 PM PDT 24 Jun 30 05:03:53 PM PDT 24 50902774 ps
T1101 /workspace/coverage/cover_reg_top/18.kmac_intr_test.2358693142 Jun 30 05:04:12 PM PDT 24 Jun 30 05:04:13 PM PDT 24 48499511 ps
T1102 /workspace/coverage/cover_reg_top/20.kmac_intr_test.299284303 Jun 30 05:04:22 PM PDT 24 Jun 30 05:04:23 PM PDT 24 23857996 ps
T1103 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3416294506 Jun 30 05:03:26 PM PDT 24 Jun 30 05:03:27 PM PDT 24 48188565 ps
T1104 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.803295817 Jun 30 05:04:01 PM PDT 24 Jun 30 05:04:04 PM PDT 24 960100579 ps
T1105 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.2563600133 Jun 30 05:04:16 PM PDT 24 Jun 30 05:04:17 PM PDT 24 28150093 ps
T1106 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.249251801 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:53 PM PDT 24 133882549 ps
T151 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3095180830 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:45 PM PDT 24 62176345 ps
T178 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1473965518 Jun 30 05:03:27 PM PDT 24 Jun 30 05:03:31 PM PDT 24 166313101 ps
T1107 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2937918807 Jun 30 05:04:11 PM PDT 24 Jun 30 05:04:13 PM PDT 24 19363588 ps
T1108 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.61198169 Jun 30 05:03:17 PM PDT 24 Jun 30 05:03:19 PM PDT 24 22393857 ps
T1109 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.614630204 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:53 PM PDT 24 77447597 ps
T106 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2356232089 Jun 30 05:03:36 PM PDT 24 Jun 30 05:03:39 PM PDT 24 138652060 ps
T1110 /workspace/coverage/cover_reg_top/10.kmac_intr_test.949792376 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:52 PM PDT 24 31659000 ps
T1111 /workspace/coverage/cover_reg_top/27.kmac_intr_test.2992005618 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:21 PM PDT 24 16281483 ps
T175 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.847478482 Jun 30 05:03:18 PM PDT 24 Jun 30 05:03:22 PM PDT 24 1645958056 ps
T101 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3473916488 Jun 30 05:04:12 PM PDT 24 Jun 30 05:04:15 PM PDT 24 65730912 ps
T1112 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2469656892 Jun 30 05:03:11 PM PDT 24 Jun 30 05:03:14 PM PDT 24 134657185 ps
T1113 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.4030694849 Jun 30 05:03:45 PM PDT 24 Jun 30 05:03:47 PM PDT 24 26583748 ps
T1114 /workspace/coverage/cover_reg_top/39.kmac_intr_test.54811590 Jun 30 05:04:26 PM PDT 24 Jun 30 05:04:28 PM PDT 24 15423567 ps
T1115 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1484244500 Jun 30 05:03:21 PM PDT 24 Jun 30 05:03:22 PM PDT 24 22118182 ps
T1116 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3132087680 Jun 30 05:04:07 PM PDT 24 Jun 30 05:04:10 PM PDT 24 414237410 ps
T1117 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2712689855 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:45 PM PDT 24 40280042 ps
T1118 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4100799866 Jun 30 05:04:01 PM PDT 24 Jun 30 05:04:04 PM PDT 24 46668244 ps
T1119 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2884666909 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:20 PM PDT 24 2018857412 ps
T1120 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2757509221 Jun 30 05:03:27 PM PDT 24 Jun 30 05:03:28 PM PDT 24 58440773 ps
T1121 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2805270380 Jun 30 05:04:30 PM PDT 24 Jun 30 05:04:31 PM PDT 24 14185793 ps
T1122 /workspace/coverage/cover_reg_top/29.kmac_intr_test.1665753671 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:21 PM PDT 24 18509943 ps
T1123 /workspace/coverage/cover_reg_top/8.kmac_intr_test.1009054926 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:45 PM PDT 24 15885158 ps
T1124 /workspace/coverage/cover_reg_top/46.kmac_intr_test.4038261110 Jun 30 05:04:28 PM PDT 24 Jun 30 05:04:29 PM PDT 24 15823177 ps
T1125 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.171654812 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:01 PM PDT 24 69587440 ps
T1126 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1203810544 Jun 30 05:03:58 PM PDT 24 Jun 30 05:03:59 PM PDT 24 28974368 ps
T1127 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2835657360 Jun 30 05:03:27 PM PDT 24 Jun 30 05:03:29 PM PDT 24 219082433 ps
T1128 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1355838058 Jun 30 05:04:15 PM PDT 24 Jun 30 05:04:17 PM PDT 24 100760196 ps
T1129 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2244946628 Jun 30 05:04:02 PM PDT 24 Jun 30 05:04:05 PM PDT 24 389686498 ps
T107 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1065020518 Jun 30 05:03:57 PM PDT 24 Jun 30 05:03:59 PM PDT 24 96520371 ps
T1130 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2790058108 Jun 30 05:04:27 PM PDT 24 Jun 30 05:04:29 PM PDT 24 18046218 ps
T1131 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2100967489 Jun 30 05:03:53 PM PDT 24 Jun 30 05:03:54 PM PDT 24 102650319 ps
T1132 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2639693224 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:53 PM PDT 24 281939010 ps
T1133 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.983871565 Jun 30 05:03:27 PM PDT 24 Jun 30 05:03:29 PM PDT 24 164176775 ps
T1134 /workspace/coverage/cover_reg_top/9.kmac_intr_test.1412838423 Jun 30 05:03:52 PM PDT 24 Jun 30 05:03:53 PM PDT 24 41597103 ps
T1135 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1144209892 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:12 PM PDT 24 54921954 ps
T1136 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3757994432 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:00 PM PDT 24 71143013 ps
T1137 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.798265902 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:00 PM PDT 24 95682873 ps
T1138 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1032216043 Jun 30 05:04:13 PM PDT 24 Jun 30 05:04:15 PM PDT 24 175815572 ps
T1139 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2227710913 Jun 30 05:03:34 PM PDT 24 Jun 30 05:03:37 PM PDT 24 100695931 ps
T1140 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4124390602 Jun 30 05:03:17 PM PDT 24 Jun 30 05:03:21 PM PDT 24 117549301 ps
T1141 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3262854565 Jun 30 05:03:03 PM PDT 24 Jun 30 05:03:06 PM PDT 24 420178979 ps
T1142 /workspace/coverage/cover_reg_top/49.kmac_intr_test.1237326525 Jun 30 05:04:26 PM PDT 24 Jun 30 05:04:28 PM PDT 24 12439361 ps
T1143 /workspace/coverage/cover_reg_top/28.kmac_intr_test.219269133 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:20 PM PDT 24 21668045 ps
T1144 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.450884281 Jun 30 05:03:55 PM PDT 24 Jun 30 05:03:57 PM PDT 24 32511859 ps
T1145 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2526920332 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:21 PM PDT 24 11814857 ps
T177 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1287319322 Jun 30 05:04:14 PM PDT 24 Jun 30 05:04:18 PM PDT 24 355766313 ps
T1146 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3699790811 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:04 PM PDT 24 56813318 ps
T1147 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3996163600 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:12 PM PDT 24 40560138 ps
T1148 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3014153945 Jun 30 05:03:01 PM PDT 24 Jun 30 05:03:03 PM PDT 24 41876271 ps
T1149 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.223528632 Jun 30 05:02:54 PM PDT 24 Jun 30 05:02:57 PM PDT 24 96781398 ps
T1150 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1137900707 Jun 30 05:04:20 PM PDT 24 Jun 30 05:04:22 PM PDT 24 24525049 ps
T1151 /workspace/coverage/cover_reg_top/41.kmac_intr_test.3764319371 Jun 30 05:04:27 PM PDT 24 Jun 30 05:04:29 PM PDT 24 21684158 ps
T1152 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3743175327 Jun 30 05:03:35 PM PDT 24 Jun 30 05:03:38 PM PDT 24 44386505 ps
T1153 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1170133514 Jun 30 05:04:11 PM PDT 24 Jun 30 05:04:13 PM PDT 24 91102099 ps
T1154 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.778821333 Jun 30 05:04:02 PM PDT 24 Jun 30 05:04:03 PM PDT 24 61027856 ps
T1155 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3041496150 Jun 30 05:03:50 PM PDT 24 Jun 30 05:03:53 PM PDT 24 124827242 ps
T179 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2788125764 Jun 30 05:04:07 PM PDT 24 Jun 30 05:04:10 PM PDT 24 141209308 ps
T1156 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3188070675 Jun 30 05:03:18 PM PDT 24 Jun 30 05:03:20 PM PDT 24 18292569 ps
T1157 /workspace/coverage/cover_reg_top/26.kmac_intr_test.3033903645 Jun 30 05:04:18 PM PDT 24 Jun 30 05:04:19 PM PDT 24 21584506 ps
T1158 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1790841443 Jun 30 05:04:07 PM PDT 24 Jun 30 05:04:10 PM PDT 24 223434644 ps
T1159 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.29207636 Jun 30 05:04:07 PM PDT 24 Jun 30 05:04:11 PM PDT 24 88385674 ps
T180 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2623776879 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:06 PM PDT 24 84289551 ps
T1160 /workspace/coverage/cover_reg_top/12.kmac_intr_test.2723233045 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:52 PM PDT 24 42729095 ps
T1161 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1978290593 Jun 30 05:03:28 PM PDT 24 Jun 30 05:03:29 PM PDT 24 14198518 ps
T1162 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.904476380 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:21 PM PDT 24 970634363 ps
T1163 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3199457440 Jun 30 05:03:57 PM PDT 24 Jun 30 05:03:59 PM PDT 24 33394447 ps
T1164 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.835880881 Jun 30 05:03:19 PM PDT 24 Jun 30 05:03:22 PM PDT 24 76002827 ps
T1165 /workspace/coverage/cover_reg_top/11.kmac_intr_test.3277860476 Jun 30 05:03:53 PM PDT 24 Jun 30 05:03:54 PM PDT 24 44689878 ps
T1166 /workspace/coverage/cover_reg_top/1.kmac_intr_test.472125833 Jun 30 05:03:03 PM PDT 24 Jun 30 05:03:04 PM PDT 24 23685841 ps
T1167 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2651554920 Jun 30 05:02:53 PM PDT 24 Jun 30 05:02:55 PM PDT 24 24753762 ps
T1168 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2610387250 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:54 PM PDT 24 50070033 ps
T1169 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3929838651 Jun 30 05:03:52 PM PDT 24 Jun 30 05:03:55 PM PDT 24 51508069 ps
T1170 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3363706837 Jun 30 05:03:50 PM PDT 24 Jun 30 05:03:51 PM PDT 24 111124682 ps
T1171 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1171588915 Jun 30 05:04:13 PM PDT 24 Jun 30 05:04:17 PM PDT 24 446174772 ps
T1172 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.832293187 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:03 PM PDT 24 69715924 ps
T1173 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2224140660 Jun 30 05:03:42 PM PDT 24 Jun 30 05:03:44 PM PDT 24 64100699 ps
T1174 /workspace/coverage/cover_reg_top/16.kmac_intr_test.2530422028 Jun 30 05:04:06 PM PDT 24 Jun 30 05:04:08 PM PDT 24 32181724 ps
T1175 /workspace/coverage/cover_reg_top/22.kmac_intr_test.651410852 Jun 30 05:04:20 PM PDT 24 Jun 30 05:04:22 PM PDT 24 36080303 ps
T1176 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1299922928 Jun 30 05:03:20 PM PDT 24 Jun 30 05:03:39 PM PDT 24 998471901 ps
T1177 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2024505769 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:46 PM PDT 24 35751253 ps
T1178 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.460519765 Jun 30 05:04:06 PM PDT 24 Jun 30 05:04:08 PM PDT 24 49296033 ps
T1179 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2146168804 Jun 30 05:04:15 PM PDT 24 Jun 30 05:04:19 PM PDT 24 601600441 ps
T1180 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.207069654 Jun 30 05:03:11 PM PDT 24 Jun 30 05:03:13 PM PDT 24 67897126 ps
T1181 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3012366899 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:52 PM PDT 24 146013059 ps
T1182 /workspace/coverage/cover_reg_top/38.kmac_intr_test.49313992 Jun 30 05:04:25 PM PDT 24 Jun 30 05:04:26 PM PDT 24 99057909 ps
T1183 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1843204041 Jun 30 05:04:12 PM PDT 24 Jun 30 05:04:14 PM PDT 24 214355844 ps
T1184 /workspace/coverage/cover_reg_top/19.kmac_intr_test.3721097798 Jun 30 05:04:20 PM PDT 24 Jun 30 05:04:21 PM PDT 24 16715515 ps
T137 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4129158668 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:05 PM PDT 24 19725608 ps
T1185 /workspace/coverage/cover_reg_top/32.kmac_intr_test.2606598001 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:20 PM PDT 24 14803839 ps
T1186 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1993368005 Jun 30 05:03:29 PM PDT 24 Jun 30 05:03:31 PM PDT 24 32881204 ps
T1187 /workspace/coverage/cover_reg_top/7.kmac_intr_test.3780911457 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:45 PM PDT 24 16803067 ps
T174 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3454913885 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:54 PM PDT 24 106347475 ps
T1188 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1520800693 Jun 30 05:04:06 PM PDT 24 Jun 30 05:04:09 PM PDT 24 249070121 ps
T1189 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2712594646 Jun 30 05:03:26 PM PDT 24 Jun 30 05:03:31 PM PDT 24 4479703851 ps
T1190 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2390940051 Jun 30 05:03:10 PM PDT 24 Jun 30 05:03:16 PM PDT 24 378452849 ps
T1191 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2545996597 Jun 30 05:03:01 PM PDT 24 Jun 30 05:03:02 PM PDT 24 57743424 ps
T1192 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.919433643 Jun 30 05:04:20 PM PDT 24 Jun 30 05:04:22 PM PDT 24 48206170 ps
T1193 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3427373531 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:00 PM PDT 24 88204080 ps
T1194 /workspace/coverage/cover_reg_top/44.kmac_intr_test.153437365 Jun 30 05:04:26 PM PDT 24 Jun 30 05:04:27 PM PDT 24 12216148 ps
T1195 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2466906056 Jun 30 05:04:06 PM PDT 24 Jun 30 05:04:09 PM PDT 24 841446855 ps
T1196 /workspace/coverage/cover_reg_top/47.kmac_intr_test.3064166001 Jun 30 05:04:26 PM PDT 24 Jun 30 05:04:28 PM PDT 24 16643001 ps
T1197 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.824093054 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:52 PM PDT 24 31721695 ps
T1198 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.129171361 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:46 PM PDT 24 383627581 ps
T1199 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1336111489 Jun 30 05:04:05 PM PDT 24 Jun 30 05:04:06 PM PDT 24 64484956 ps
T1200 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1168792750 Jun 30 05:04:06 PM PDT 24 Jun 30 05:04:07 PM PDT 24 14304505 ps
T138 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1873932701 Jun 30 05:03:17 PM PDT 24 Jun 30 05:03:18 PM PDT 24 104702176 ps
T1201 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.568902029 Jun 30 05:04:16 PM PDT 24 Jun 30 05:04:18 PM PDT 24 130524720 ps
T1202 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3641806128 Jun 30 05:03:51 PM PDT 24 Jun 30 05:03:55 PM PDT 24 207390951 ps
T1203 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2391482925 Jun 30 05:04:21 PM PDT 24 Jun 30 05:04:24 PM PDT 24 131450783 ps
T1204 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1169330121 Jun 30 05:03:52 PM PDT 24 Jun 30 05:03:55 PM PDT 24 333119287 ps
T1205 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3503673317 Jun 30 05:03:44 PM PDT 24 Jun 30 05:03:48 PM PDT 24 191040765 ps
T1206 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.378447557 Jun 30 05:04:07 PM PDT 24 Jun 30 05:04:10 PM PDT 24 126827853 ps
T1207 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2020696138 Jun 30 05:03:11 PM PDT 24 Jun 30 05:03:13 PM PDT 24 174943694 ps
T1208 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1570219143 Jun 30 05:03:27 PM PDT 24 Jun 30 05:03:42 PM PDT 24 1125010339 ps
T1209 /workspace/coverage/cover_reg_top/21.kmac_intr_test.1623112038 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:20 PM PDT 24 19315823 ps
T139 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3552773411 Jun 30 05:03:03 PM PDT 24 Jun 30 05:03:05 PM PDT 24 32169477 ps
T1210 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1427301376 Jun 30 05:04:06 PM PDT 24 Jun 30 05:04:08 PM PDT 24 54338926 ps
T181 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3372880640 Jun 30 05:03:03 PM PDT 24 Jun 30 05:03:08 PM PDT 24 762865515 ps
T1211 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.344429028 Jun 30 05:03:19 PM PDT 24 Jun 30 05:03:20 PM PDT 24 27655632 ps
T1212 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3304794568 Jun 30 05:03:34 PM PDT 24 Jun 30 05:03:37 PM PDT 24 115219545 ps
T1213 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2464658209 Jun 30 05:03:35 PM PDT 24 Jun 30 05:03:37 PM PDT 24 110882032 ps
T1214 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2286412632 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:45 PM PDT 24 23049073 ps
T1215 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1673524398 Jun 30 05:03:19 PM PDT 24 Jun 30 05:03:22 PM PDT 24 52696607 ps
T1216 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3638455201 Jun 30 05:03:45 PM PDT 24 Jun 30 05:03:50 PM PDT 24 248410146 ps
T1217 /workspace/coverage/cover_reg_top/14.kmac_intr_test.3211619463 Jun 30 05:03:56 PM PDT 24 Jun 30 05:03:57 PM PDT 24 16404957 ps
T1218 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.532278730 Jun 30 05:04:12 PM PDT 24 Jun 30 05:04:14 PM PDT 24 192564739 ps
T1219 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.916253156 Jun 30 05:03:43 PM PDT 24 Jun 30 05:03:47 PM PDT 24 224146912 ps
T1220 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.489295920 Jun 30 05:03:35 PM PDT 24 Jun 30 05:03:38 PM PDT 24 60090984 ps
T1221 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2883475922 Jun 30 05:03:11 PM PDT 24 Jun 30 05:03:13 PM PDT 24 50873901 ps
T1222 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3677317220 Jun 30 05:04:06 PM PDT 24 Jun 30 05:04:08 PM PDT 24 24274115 ps
T1223 /workspace/coverage/cover_reg_top/5.kmac_intr_test.3448924446 Jun 30 05:03:37 PM PDT 24 Jun 30 05:03:38 PM PDT 24 94169627 ps
T1224 /workspace/coverage/cover_reg_top/30.kmac_intr_test.4093503909 Jun 30 05:04:17 PM PDT 24 Jun 30 05:04:18 PM PDT 24 39440853 ps
T1225 /workspace/coverage/cover_reg_top/37.kmac_intr_test.1864991590 Jun 30 05:04:26 PM PDT 24 Jun 30 05:04:27 PM PDT 24 42799595 ps
T1226 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2224994906 Jun 30 05:03:35 PM PDT 24 Jun 30 05:03:39 PM PDT 24 487783057 ps
T1227 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.336476213 Jun 30 05:04:05 PM PDT 24 Jun 30 05:04:08 PM PDT 24 115369527 ps
T1228 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3516861388 Jun 30 05:03:58 PM PDT 24 Jun 30 05:04:02 PM PDT 24 331388291 ps
T1229 /workspace/coverage/cover_reg_top/0.kmac_intr_test.1696133236 Jun 30 05:03:02 PM PDT 24 Jun 30 05:03:04 PM PDT 24 13787188 ps
T1230 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1525873766 Jun 30 05:04:04 PM PDT 24 Jun 30 05:04:07 PM PDT 24 142580976 ps
T1231 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1452642741 Jun 30 05:03:55 PM PDT 24 Jun 30 05:03:57 PM PDT 24 199238028 ps
T1232 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.969796167 Jun 30 05:03:42 PM PDT 24 Jun 30 05:03:45 PM PDT 24 66183827 ps
T1233 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1734366050 Jun 30 05:03:27 PM PDT 24 Jun 30 05:03:28 PM PDT 24 31003552 ps
T1234 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1207751356 Jun 30 05:04:00 PM PDT 24 Jun 30 05:04:02 PM PDT 24 289994661 ps
T1235 /workspace/coverage/cover_reg_top/25.kmac_intr_test.4109406819 Jun 30 05:04:19 PM PDT 24 Jun 30 05:04:21 PM PDT 24 40070908 ps

Test location /workspace/coverage/default/48.kmac_stress_all.3196524807
Short name T3
Test name
Test status
Simulation time 147195860680 ps
CPU time 690.27 seconds
Started Jun 30 06:01:54 PM PDT 24
Finished Jun 30 06:13:25 PM PDT 24
Peak memory 331100 kb
Host smart-bf2af8af-8fc3-473c-a3b8-d4d18bcf54a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3196524807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3196524807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3920282443
Short name T112
Test name
Test status
Simulation time 850336674 ps
CPU time 4.6 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:15 PM PDT 24
Peak memory 207312 kb
Host smart-fa35a6c0-1e69-4972-bddd-71881661a0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920282443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.39202
82443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.2271069823
Short name T10
Test name
Test status
Simulation time 9880324146 ps
CPU time 66.35 seconds
Started Jun 30 05:51:50 PM PDT 24
Finished Jun 30 05:52:57 PM PDT 24
Peak memory 271636 kb
Host smart-071179ff-de38-4954-9a66-f711589064c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271069823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.2271069823 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/7.kmac_burst_write.104802043
Short name T35
Test name
Test status
Simulation time 64212028800 ps
CPU time 351.55 seconds
Started Jun 30 05:52:17 PM PDT 24
Finished Jun 30 05:58:09 PM PDT 24
Peak memory 229248 kb
Host smart-850154eb-1ee7-41a8-a2e5-eb20ebd2ba9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104802043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.104802043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.3636662113
Short name T30
Test name
Test status
Simulation time 142146109050 ps
CPU time 2554.28 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 06:34:10 PM PDT 24
Peak memory 413192 kb
Host smart-9cc4de95-2060-4cff-9caf-34a44f3c2aeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636662113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.3636662113 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.kmac_key_error.1479037057
Short name T16
Test name
Test status
Simulation time 1060354428 ps
CPU time 5.89 seconds
Started Jun 30 05:59:31 PM PDT 24
Finished Jun 30 05:59:37 PM PDT 24
Peak memory 207924 kb
Host smart-d1d0a68d-fcd1-4356-a8cf-66d9390ac30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479037057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1479037057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.1686919667
Short name T6
Test name
Test status
Simulation time 448545841 ps
CPU time 22.31 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:54:42 PM PDT 24
Peak memory 232508 kb
Host smart-80261623-d8d2-4f1c-8adc-25e73466d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686919667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1686919667 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1384654502
Short name T100
Test name
Test status
Simulation time 45587328 ps
CPU time 1.27 seconds
Started Jun 30 05:03:35 PM PDT 24
Finished Jun 30 05:03:37 PM PDT 24
Peak memory 215940 kb
Host smart-060511d1-8d4c-4897-8b3a-90bf0b703751
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384654502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1384654502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.kmac_error.3310286842
Short name T26
Test name
Test status
Simulation time 3662992353 ps
CPU time 127.04 seconds
Started Jun 30 05:54:58 PM PDT 24
Finished Jun 30 05:57:05 PM PDT 24
Peak memory 248956 kb
Host smart-037541d0-afee-4ad0-9c64-fec5047206b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310286842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3310286842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.816449843
Short name T115
Test name
Test status
Simulation time 22633643 ps
CPU time 0.77 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 207016 kb
Host smart-2436b4da-b23e-4b86-8324-67f88b1d7917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816449843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.816449843 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.3155336123
Short name T5
Test name
Test status
Simulation time 29329565 ps
CPU time 1.2 seconds
Started Jun 30 05:52:54 PM PDT 24
Finished Jun 30 05:52:56 PM PDT 24
Peak memory 216124 kb
Host smart-5d86b42f-2085-4b69-b4fd-4ae49daff692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155336123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3155336123 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2353719977
Short name T50
Test name
Test status
Simulation time 112177210 ps
CPU time 1.3 seconds
Started Jun 30 05:51:41 PM PDT 24
Finished Jun 30 05:51:43 PM PDT 24
Peak memory 216096 kb
Host smart-48d91f4e-85ff-41c0-9b0a-fd7d671e3107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353719977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2353719977 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.3283486122
Short name T48
Test name
Test status
Simulation time 486957590 ps
CPU time 14.6 seconds
Started Jun 30 06:01:01 PM PDT 24
Finished Jun 30 06:01:16 PM PDT 24
Peak memory 232528 kb
Host smart-3fbd419d-c0da-48e7-a5b9-4bb1fc2a68fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283486122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3283486122 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3473916488
Short name T101
Test name
Test status
Simulation time 65730912 ps
CPU time 2.4 seconds
Started Jun 30 05:04:12 PM PDT 24
Finished Jun 30 05:04:15 PM PDT 24
Peak memory 215872 kb
Host smart-87ae4a18-1e56-4ef4-84ac-9a7de8a6110e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473916488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3473916488 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.3189282975
Short name T186
Test name
Test status
Simulation time 52922712044 ps
CPU time 4229.98 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 07:05:35 PM PDT 24
Peak memory 649972 kb
Host smart-cdae606c-81a4-454a-a11f-f2a7fbc77709
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3189282975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.3189282975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_alert_test.3419394485
Short name T239
Test name
Test status
Simulation time 94818137 ps
CPU time 0.89 seconds
Started Jun 30 05:52:55 PM PDT 24
Finished Jun 30 05:52:56 PM PDT 24
Peak memory 205640 kb
Host smart-d69f9e1c-9bc8-4bef-81e8-0713468a8305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419394485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3419394485 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3552773411
Short name T139
Test name
Test status
Simulation time 32169477 ps
CPU time 1.23 seconds
Started Jun 30 05:03:03 PM PDT 24
Finished Jun 30 05:03:05 PM PDT 24
Peak memory 215460 kb
Host smart-d5f6c38f-41fb-44fd-99f8-1a8f73c2f8ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552773411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3552773411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3086045186
Short name T483
Test name
Test status
Simulation time 187744594 ps
CPU time 1.35 seconds
Started Jun 30 05:53:26 PM PDT 24
Finished Jun 30 05:53:28 PM PDT 24
Peak memory 216088 kb
Host smart-99ff25ef-7e87-4394-86b6-182d4c5904e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086045186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3086045186 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.982878625
Short name T149
Test name
Test status
Simulation time 73138671 ps
CPU time 1.22 seconds
Started Jun 30 05:03:44 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 215876 kb
Host smart-6904f3f2-2060-4076-93d7-aa9f4f399978
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982878625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.982878625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3546325089
Short name T176
Test name
Test status
Simulation time 196049483 ps
CPU time 4.63 seconds
Started Jun 30 05:03:57 PM PDT 24
Finished Jun 30 05:04:03 PM PDT 24
Peak memory 215400 kb
Host smart-994ad2da-dc9c-4361-8089-61f9d71ca395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546325089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3546
325089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.460519765
Short name T1178
Test name
Test status
Simulation time 49296033 ps
CPU time 1.15 seconds
Started Jun 30 05:04:06 PM PDT 24
Finished Jun 30 05:04:08 PM PDT 24
Peak memory 215664 kb
Host smart-ad8283a6-e2ac-4ade-97fe-668796bb61f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460519765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_
errors.460519765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3638520167
Short name T40
Test name
Test status
Simulation time 2650456957 ps
CPU time 32.51 seconds
Started Jun 30 05:51:41 PM PDT 24
Finished Jun 30 05:52:14 PM PDT 24
Peak memory 217444 kb
Host smart-85b6a94b-1f52-4859-baa6-91b0d7d47168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638520167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3638520167 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.450951802
Short name T65
Test name
Test status
Simulation time 611517112959 ps
CPU time 4016.96 seconds
Started Jun 30 05:53:03 PM PDT 24
Finished Jun 30 07:00:01 PM PDT 24
Peak memory 570104 kb
Host smart-0988366b-eae3-462f-ab6b-03467070f8c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=450951802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.450951802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_error.3255189639
Short name T70
Test name
Test status
Simulation time 17546075091 ps
CPU time 73.22 seconds
Started Jun 30 05:53:09 PM PDT 24
Finished Jun 30 05:54:22 PM PDT 24
Peak memory 234700 kb
Host smart-41a7475c-4dc8-4edf-b122-8157929bebb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255189639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3255189639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.808649858
Short name T84
Test name
Test status
Simulation time 77302294 ps
CPU time 0.88 seconds
Started Jun 30 05:54:37 PM PDT 24
Finished Jun 30 05:54:39 PM PDT 24
Peak memory 206588 kb
Host smart-6611ea10-c03f-4306-9c9c-9ccd44c8c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808649858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.808649858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3200385715
Short name T24
Test name
Test status
Simulation time 61984192826 ps
CPU time 229.19 seconds
Started Jun 30 06:02:11 PM PDT 24
Finished Jun 30 06:06:01 PM PDT 24
Peak memory 240796 kb
Host smart-b221f357-3f26-411c-9862-d5ea410c7be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200385715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3200385715 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3454913885
Short name T174
Test name
Test status
Simulation time 106347475 ps
CPU time 2.7 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:54 PM PDT 24
Peak memory 207404 kb
Host smart-7d07ab6f-bfca-4764-869d-d2f9dcf2365b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454913885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3454
913885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.1643836114
Short name T117
Test name
Test status
Simulation time 14904809 ps
CPU time 0.75 seconds
Started Jun 30 05:03:57 PM PDT 24
Finished Jun 30 05:03:58 PM PDT 24
Peak memory 206992 kb
Host smart-d731e87f-72bb-4195-bfe1-7e8e3b3e4792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643836114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1643836114 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2623776879
Short name T180
Test name
Test status
Simulation time 84289551 ps
CPU time 2.55 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:06 PM PDT 24
Peak memory 215580 kb
Host smart-4422e743-79ea-44a7-b14e-3862db4f7657
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623776879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.26237
76879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.1329037935
Short name T157
Test name
Test status
Simulation time 345933765073 ps
CPU time 4870.33 seconds
Started Jun 30 05:58:02 PM PDT 24
Finished Jun 30 07:19:13 PM PDT 24
Peak memory 655736 kb
Host smart-ff0c0c09-bd74-4255-87f1-38000b1080c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1329037935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1329037935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.1349449017
Short name T155
Test name
Test status
Simulation time 262534380581 ps
CPU time 4954.38 seconds
Started Jun 30 05:59:16 PM PDT 24
Finished Jun 30 07:21:52 PM PDT 24
Peak memory 632000 kb
Host smart-a497cbd3-3c6f-4206-8eeb-8a8f65869699
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1349449017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.1349449017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_burst_write.621700821
Short name T38
Test name
Test status
Simulation time 7592108418 ps
CPU time 633.22 seconds
Started Jun 30 05:53:55 PM PDT 24
Finished Jun 30 06:04:28 PM PDT 24
Peak memory 231900 kb
Host smart-cd07e0cc-475f-4f0b-8223-3de79c8dd6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621700821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.621700821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_error.3023172198
Short name T409
Test name
Test status
Simulation time 54993879096 ps
CPU time 376.95 seconds
Started Jun 30 05:52:49 PM PDT 24
Finished Jun 30 05:59:07 PM PDT 24
Peak memory 257112 kb
Host smart-7d372cd7-1ccf-4b71-9789-9b20ea91f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023172198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3023172198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3345506543
Short name T183
Test name
Test status
Simulation time 387691313 ps
CPU time 9.17 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 207328 kb
Host smart-1bf566a8-04cc-4b79-865d-14f1cccc0b1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345506543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3345506
543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.904476380
Short name T1162
Test name
Test status
Simulation time 970634363 ps
CPU time 18.38 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:21 PM PDT 24
Peak memory 207400 kb
Host smart-7fbe8049-e50b-4412-b6e1-3ce8134023d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904476380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.90447638
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.832293187
Short name T1172
Test name
Test status
Simulation time 69715924 ps
CPU time 1.06 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:03 PM PDT 24
Peak memory 207204 kb
Host smart-8cd49e57-c94e-43f0-95d1-244e6104f7a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832293187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.83229318
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3262854565
Short name T1141
Test name
Test status
Simulation time 420178979 ps
CPU time 2.24 seconds
Started Jun 30 05:03:03 PM PDT 24
Finished Jun 30 05:03:06 PM PDT 24
Peak memory 223668 kb
Host smart-15475ed6-4c46-48f2-855a-878c629781d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262854565 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3262854565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3014153945
Short name T1148
Test name
Test status
Simulation time 41876271 ps
CPU time 0.9 seconds
Started Jun 30 05:03:01 PM PDT 24
Finished Jun 30 05:03:03 PM PDT 24
Peak memory 207068 kb
Host smart-7638f201-5b15-4e9a-9dfc-d09e386ef552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014153945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3014153945 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.1696133236
Short name T1229
Test name
Test status
Simulation time 13787188 ps
CPU time 0.76 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:04 PM PDT 24
Peak memory 207024 kb
Host smart-55f81880-5b25-4f45-98e9-5615b39b969d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696133236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1696133236 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2651554920
Short name T1167
Test name
Test status
Simulation time 24753762 ps
CPU time 0.75 seconds
Started Jun 30 05:02:53 PM PDT 24
Finished Jun 30 05:02:55 PM PDT 24
Peak memory 207084 kb
Host smart-6289562e-b181-4b44-b1f0-b2387e767757
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651554920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2651554920
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1823087451
Short name T153
Test name
Test status
Simulation time 68343326 ps
CPU time 1.74 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:04 PM PDT 24
Peak memory 215536 kb
Host smart-eb4619b9-b486-46f5-a104-0010c4b9c6eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823087451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.1823087451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3981132157
Short name T109
Test name
Test status
Simulation time 399770188 ps
CPU time 0.94 seconds
Started Jun 30 05:02:54 PM PDT 24
Finished Jun 30 05:02:55 PM PDT 24
Peak memory 207260 kb
Host smart-ea823060-372b-4316-8ae1-4affbd79b71e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981132157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.3981132157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.223528632
Short name T1149
Test name
Test status
Simulation time 96781398 ps
CPU time 2.65 seconds
Started Jun 30 05:02:54 PM PDT 24
Finished Jun 30 05:02:57 PM PDT 24
Peak memory 215888 kb
Host smart-cb2f6856-a255-4fdd-82d2-b5747a7d8a64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223528632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_
shadow_reg_errors_with_csr_rw.223528632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.466556321
Short name T119
Test name
Test status
Simulation time 280721978 ps
CPU time 2.07 seconds
Started Jun 30 05:03:03 PM PDT 24
Finished Jun 30 05:03:05 PM PDT 24
Peak memory 215560 kb
Host smart-00385af6-a637-4537-b9df-c3b91c9995bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466556321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.466556321 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2390940051
Short name T1190
Test name
Test status
Simulation time 378452849 ps
CPU time 5.04 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:16 PM PDT 24
Peak memory 207188 kb
Host smart-60b090db-4f9d-4f71-8d78-5cca37337db0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390940051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2390940
051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2884666909
Short name T1119
Test name
Test status
Simulation time 2018857412 ps
CPU time 9.12 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:20 PM PDT 24
Peak memory 207196 kb
Host smart-98e51685-2494-4002-9f75-39d852613f9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884666909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2884666
909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2020696138
Short name T1207
Test name
Test status
Simulation time 174943694 ps
CPU time 1.15 seconds
Started Jun 30 05:03:11 PM PDT 24
Finished Jun 30 05:03:13 PM PDT 24
Peak memory 207404 kb
Host smart-fe51258b-ec92-4b45-88d1-5c0e2da7ab1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020696138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2020696
138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.207069654
Short name T1180
Test name
Test status
Simulation time 67897126 ps
CPU time 1.47 seconds
Started Jun 30 05:03:11 PM PDT 24
Finished Jun 30 05:03:13 PM PDT 24
Peak memory 223476 kb
Host smart-26c49b86-5fdd-4d83-b3bb-e11f5448fff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207069654 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.207069654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4013476321
Short name T1085
Test name
Test status
Simulation time 56289743 ps
CPU time 0.96 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 215280 kb
Host smart-5e684497-b43f-4bf5-805c-ff6b99ae18e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013476321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4013476321 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.472125833
Short name T1166
Test name
Test status
Simulation time 23685841 ps
CPU time 0.79 seconds
Started Jun 30 05:03:03 PM PDT 24
Finished Jun 30 05:03:04 PM PDT 24
Peak memory 206920 kb
Host smart-97c81941-07ec-4134-8a41-88a1f1d562e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472125833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.472125833 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4129158668
Short name T137
Test name
Test status
Simulation time 19725608 ps
CPU time 1.38 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:05 PM PDT 24
Peak memory 215468 kb
Host smart-c689264a-6da9-4415-a401-7c506cc1f99c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129158668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.4129158668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.733335298
Short name T1083
Test name
Test status
Simulation time 18799650 ps
CPU time 0.72 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:03 PM PDT 24
Peak memory 207080 kb
Host smart-e615e211-d42d-4c12-a3ad-2e27c45633ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733335298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.733335298 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2379999929
Short name T148
Test name
Test status
Simulation time 115857818 ps
CPU time 2.52 seconds
Started Jun 30 05:03:09 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 215536 kb
Host smart-b23b3b14-dbb1-427f-a6e3-afdf914f5e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379999929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2379999929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2545996597
Short name T1191
Test name
Test status
Simulation time 57743424 ps
CPU time 1.08 seconds
Started Jun 30 05:03:01 PM PDT 24
Finished Jun 30 05:03:02 PM PDT 24
Peak memory 215824 kb
Host smart-851b878b-a5cb-4da1-b4a0-79c99b18cb94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545996597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.2545996597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3699790811
Short name T1146
Test name
Test status
Simulation time 56813318 ps
CPU time 2.48 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:04 PM PDT 24
Peak memory 223324 kb
Host smart-28d17a04-20d6-4c8c-ab39-60a113a5aa80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699790811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3699790811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.111565347
Short name T121
Test name
Test status
Simulation time 92045661 ps
CPU time 1.54 seconds
Started Jun 30 05:03:02 PM PDT 24
Finished Jun 30 05:03:04 PM PDT 24
Peak memory 215516 kb
Host smart-ebb5bd38-ea61-43d5-8e13-656f56803f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111565347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.111565347 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3372880640
Short name T181
Test name
Test status
Simulation time 762865515 ps
CPU time 4.98 seconds
Started Jun 30 05:03:03 PM PDT 24
Finished Jun 30 05:03:08 PM PDT 24
Peak memory 207244 kb
Host smart-6c3881da-9511-49b1-8144-c9bcd56ddf53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372880640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.33728
80640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3041496150
Short name T1155
Test name
Test status
Simulation time 124827242 ps
CPU time 2.47 seconds
Started Jun 30 05:03:50 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 216768 kb
Host smart-75544b6a-a526-47f5-b27b-1ec15a4a8ea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041496150 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3041496150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.740817628
Short name T1092
Test name
Test status
Simulation time 60705366 ps
CPU time 0.91 seconds
Started Jun 30 05:03:52 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 207044 kb
Host smart-732475c2-1076-4b37-acc6-cb1632224b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740817628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.740817628 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.949792376
Short name T1110
Test name
Test status
Simulation time 31659000 ps
CPU time 0.75 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:52 PM PDT 24
Peak memory 206984 kb
Host smart-2ab695cb-a473-4ff5-b034-9daf3651c2af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949792376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.949792376 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2610387250
Short name T1168
Test name
Test status
Simulation time 50070033 ps
CPU time 2.06 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:54 PM PDT 24
Peak memory 215868 kb
Host smart-9f2b154e-27b1-4140-aa9e-7011c8e84ded
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610387250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.2610387250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3012366899
Short name T1181
Test name
Test status
Simulation time 146013059 ps
CPU time 1.14 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:52 PM PDT 24
Peak memory 215872 kb
Host smart-79a29268-e4a9-4016-9c06-d73cd3b768e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012366899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3012366899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3929838651
Short name T1169
Test name
Test status
Simulation time 51508069 ps
CPU time 2.48 seconds
Started Jun 30 05:03:52 PM PDT 24
Finished Jun 30 05:03:55 PM PDT 24
Peak memory 215916 kb
Host smart-82f76b0b-b4e1-4a5e-8260-4aa1a5e41cc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929838651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.3929838651 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1813388510
Short name T1100
Test name
Test status
Simulation time 50902774 ps
CPU time 3.08 seconds
Started Jun 30 05:03:49 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 215480 kb
Host smart-25866905-510d-421e-9481-911331145c89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813388510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1813388510 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3641806128
Short name T1202
Test name
Test status
Simulation time 207390951 ps
CPU time 3.05 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:55 PM PDT 24
Peak memory 207348 kb
Host smart-d007d773-677e-4ab4-8c24-68fc66f733c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641806128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3641
806128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.249251801
Short name T1106
Test name
Test status
Simulation time 133882549 ps
CPU time 1.51 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 215540 kb
Host smart-c65d2f2b-fc21-42d0-866f-575b718b472d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249251801 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.249251801 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.824093054
Short name T1197
Test name
Test status
Simulation time 31721695 ps
CPU time 0.89 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:52 PM PDT 24
Peak memory 207144 kb
Host smart-450f9014-27d0-4161-a63e-b42f84a5200a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824093054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.824093054 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.3277860476
Short name T1165
Test name
Test status
Simulation time 44689878 ps
CPU time 0.78 seconds
Started Jun 30 05:03:53 PM PDT 24
Finished Jun 30 05:03:54 PM PDT 24
Peak memory 207000 kb
Host smart-ed3625f7-99df-4052-9aa2-0717361552c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277860476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3277860476 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1452642741
Short name T1231
Test name
Test status
Simulation time 199238028 ps
CPU time 1.6 seconds
Started Jun 30 05:03:55 PM PDT 24
Finished Jun 30 05:03:57 PM PDT 24
Peak memory 216104 kb
Host smart-addce9e6-c4db-430f-b8c2-899b5ba18ec1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452642741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1452642741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3363706837
Short name T1170
Test name
Test status
Simulation time 111124682 ps
CPU time 1.15 seconds
Started Jun 30 05:03:50 PM PDT 24
Finished Jun 30 05:03:51 PM PDT 24
Peak memory 215836 kb
Host smart-8e33d20c-4648-486d-9560-4515e3d544df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363706837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.3363706837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3961229520
Short name T98
Test name
Test status
Simulation time 112626548 ps
CPU time 2.26 seconds
Started Jun 30 05:03:52 PM PDT 24
Finished Jun 30 05:03:55 PM PDT 24
Peak memory 224008 kb
Host smart-cb44e700-2c4e-4c83-ba6d-b08033e1995a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961229520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.3961229520 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1169330121
Short name T1204
Test name
Test status
Simulation time 333119287 ps
CPU time 2.42 seconds
Started Jun 30 05:03:52 PM PDT 24
Finished Jun 30 05:03:55 PM PDT 24
Peak memory 215500 kb
Host smart-3455a8a2-7f61-48ff-b678-50a5091870eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169330121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1169330121 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.35509981
Short name T1094
Test name
Test status
Simulation time 52713198 ps
CPU time 2.44 seconds
Started Jun 30 05:03:52 PM PDT 24
Finished Jun 30 05:03:55 PM PDT 24
Peak memory 215596 kb
Host smart-e52ba8d6-e41a-4faa-b1e8-f83ea0c74eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35509981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.355099
81 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2244946628
Short name T1129
Test name
Test status
Simulation time 389686498 ps
CPU time 2.48 seconds
Started Jun 30 05:04:02 PM PDT 24
Finished Jun 30 05:04:05 PM PDT 24
Peak memory 223576 kb
Host smart-2b0e5360-633a-43c8-ada5-deb31930a623
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244946628 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2244946628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.260338720
Short name T1087
Test name
Test status
Simulation time 49524535 ps
CPU time 1.09 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 207272 kb
Host smart-617aec8b-0fa4-4305-84bb-139c60cf16cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260338720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.260338720 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2723233045
Short name T1160
Test name
Test status
Simulation time 42729095 ps
CPU time 0.74 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:52 PM PDT 24
Peak memory 206996 kb
Host smart-6818742a-03f3-453f-9225-553f3506f1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723233045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2723233045 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.171654812
Short name T1125
Test name
Test status
Simulation time 69587440 ps
CPU time 2.12 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:01 PM PDT 24
Peak memory 215524 kb
Host smart-4f97bce0-51c4-4bde-aa2c-dd46d5d11d46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171654812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr
_outstanding.171654812 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2100967489
Short name T1131
Test name
Test status
Simulation time 102650319 ps
CPU time 1.03 seconds
Started Jun 30 05:03:53 PM PDT 24
Finished Jun 30 05:03:54 PM PDT 24
Peak memory 215824 kb
Host smart-2e48448b-d098-4feb-8129-039281053b27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100967489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2100967489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.450884281
Short name T1144
Test name
Test status
Simulation time 32511859 ps
CPU time 1.64 seconds
Started Jun 30 05:03:55 PM PDT 24
Finished Jun 30 05:03:57 PM PDT 24
Peak memory 215928 kb
Host smart-f60cd0e0-90a4-46b9-8a50-a7c9cbe2ec12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450884281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac
_shadow_reg_errors_with_csr_rw.450884281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2639693224
Short name T1132
Test name
Test status
Simulation time 281939010 ps
CPU time 1.28 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 215572 kb
Host smart-e2dd611f-3df8-4585-9a64-5881d900ac2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639693224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2639693224 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3757994432
Short name T1136
Test name
Test status
Simulation time 71143013 ps
CPU time 2.25 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:00 PM PDT 24
Peak memory 223748 kb
Host smart-b94f4f52-8210-4561-a1fb-990aa08ef8c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757994432 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3757994432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.778821333
Short name T1154
Test name
Test status
Simulation time 61027856 ps
CPU time 1.12 seconds
Started Jun 30 05:04:02 PM PDT 24
Finished Jun 30 05:04:03 PM PDT 24
Peak memory 207208 kb
Host smart-08418bfe-e131-492c-bc5c-79ca2d901d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778821333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.778821333 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2847595597
Short name T1079
Test name
Test status
Simulation time 96966257 ps
CPU time 2.55 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:02 PM PDT 24
Peak memory 216020 kb
Host smart-56a706b5-d5c0-4289-a574-60dd81a16ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847595597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.2847595597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1239322725
Short name T96
Test name
Test status
Simulation time 291280388 ps
CPU time 1.03 seconds
Started Jun 30 05:03:57 PM PDT 24
Finished Jun 30 05:03:58 PM PDT 24
Peak memory 207260 kb
Host smart-d33c67be-1ca2-48ec-9e14-9016e8c484fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239322725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1239322725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3199457440
Short name T1163
Test name
Test status
Simulation time 33394447 ps
CPU time 2.11 seconds
Started Jun 30 05:03:57 PM PDT 24
Finished Jun 30 05:03:59 PM PDT 24
Peak memory 215580 kb
Host smart-3d095cda-7fc2-4d24-a642-22ccbf203741
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199457440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3199457440 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2428186191
Short name T113
Test name
Test status
Simulation time 548953559 ps
CPU time 4.27 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:03 PM PDT 24
Peak memory 207328 kb
Host smart-5aac41ee-5e5e-4db4-8eb4-408f07baea06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428186191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2428
186191 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3516861388
Short name T1228
Test name
Test status
Simulation time 331388291 ps
CPU time 2.56 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:02 PM PDT 24
Peak memory 216884 kb
Host smart-d6e7bfa9-8209-4480-9c0d-eb2e3734c173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516861388 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3516861388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1207751356
Short name T1234
Test name
Test status
Simulation time 289994661 ps
CPU time 0.99 seconds
Started Jun 30 05:04:00 PM PDT 24
Finished Jun 30 05:04:02 PM PDT 24
Peak memory 207172 kb
Host smart-6fbf7468-f7cb-44b8-931e-40caaa0d2c73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207751356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1207751356 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3211619463
Short name T1217
Test name
Test status
Simulation time 16404957 ps
CPU time 0.82 seconds
Started Jun 30 05:03:56 PM PDT 24
Finished Jun 30 05:03:57 PM PDT 24
Peak memory 207000 kb
Host smart-8c7d97b3-68ee-4cbf-a3c8-65a469a42a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211619463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3211619463 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.798265902
Short name T1137
Test name
Test status
Simulation time 95682873 ps
CPU time 1.59 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:00 PM PDT 24
Peak memory 215760 kb
Host smart-38c8b691-46d7-4268-96da-de4777e4cff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798265902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr
_outstanding.798265902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1065020518
Short name T107
Test name
Test status
Simulation time 96520371 ps
CPU time 1.22 seconds
Started Jun 30 05:03:57 PM PDT 24
Finished Jun 30 05:03:59 PM PDT 24
Peak memory 215780 kb
Host smart-fca86919-1f93-4bfd-9a00-4fffce893fec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065020518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.1065020518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2785427426
Short name T150
Test name
Test status
Simulation time 58753267 ps
CPU time 1.56 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:00 PM PDT 24
Peak memory 215608 kb
Host smart-670756f3-ff6a-4af0-8016-ec11ff8027e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785427426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.2785427426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.803295817
Short name T1104
Test name
Test status
Simulation time 960100579 ps
CPU time 2.25 seconds
Started Jun 30 05:04:01 PM PDT 24
Finished Jun 30 05:04:04 PM PDT 24
Peak memory 215400 kb
Host smart-1abf1228-db27-4fda-b5d3-ec41d76b8608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803295817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.803295817 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2458863020
Short name T147
Test name
Test status
Simulation time 127167875 ps
CPU time 2.93 seconds
Started Jun 30 05:03:57 PM PDT 24
Finished Jun 30 05:04:00 PM PDT 24
Peak memory 215572 kb
Host smart-b076ec7e-1a17-4520-9b05-f39f64db55ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458863020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2458
863020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2466906056
Short name T1195
Test name
Test status
Simulation time 841446855 ps
CPU time 2.46 seconds
Started Jun 30 05:04:06 PM PDT 24
Finished Jun 30 05:04:09 PM PDT 24
Peak memory 223748 kb
Host smart-1842193d-9239-4de1-b195-e382347dba27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466906056 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2466906056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1168792750
Short name T1200
Test name
Test status
Simulation time 14304505 ps
CPU time 0.91 seconds
Started Jun 30 05:04:06 PM PDT 24
Finished Jun 30 05:04:07 PM PDT 24
Peak memory 207152 kb
Host smart-d75d0c99-8819-4d64-b3e5-73461da72832
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168792750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1168792750 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1203810544
Short name T1126
Test name
Test status
Simulation time 28974368 ps
CPU time 0.76 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:03:59 PM PDT 24
Peak memory 207000 kb
Host smart-1d92311a-0c03-47e8-8048-e189728e7558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203810544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1203810544 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1790841443
Short name T1158
Test name
Test status
Simulation time 223434644 ps
CPU time 2.51 seconds
Started Jun 30 05:04:07 PM PDT 24
Finished Jun 30 05:04:10 PM PDT 24
Peak memory 215492 kb
Host smart-7010668b-2416-4370-a492-2ef9e39b7173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790841443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1790841443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3427373531
Short name T1193
Test name
Test status
Simulation time 88204080 ps
CPU time 1.1 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:00 PM PDT 24
Peak memory 215876 kb
Host smart-dfb72d81-6c0f-457c-b583-f7f68b85f78b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427373531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3427373531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4100799866
Short name T1118
Test name
Test status
Simulation time 46668244 ps
CPU time 2.43 seconds
Started Jun 30 05:04:01 PM PDT 24
Finished Jun 30 05:04:04 PM PDT 24
Peak memory 215732 kb
Host smart-c8594c9a-fb99-483c-9281-5d381858bb8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100799866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.4100799866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.739360612
Short name T1089
Test name
Test status
Simulation time 313080138 ps
CPU time 3.19 seconds
Started Jun 30 05:03:58 PM PDT 24
Finished Jun 30 05:04:02 PM PDT 24
Peak memory 215516 kb
Host smart-5c41f79c-8e32-4de1-85c7-a01f772b3234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739360612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.739360612 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1525873766
Short name T1230
Test name
Test status
Simulation time 142580976 ps
CPU time 2.55 seconds
Started Jun 30 05:04:04 PM PDT 24
Finished Jun 30 05:04:07 PM PDT 24
Peak memory 218044 kb
Host smart-a631fe7c-8c68-4616-a5d5-455b4dfe6e8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525873766 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1525873766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3677317220
Short name T1222
Test name
Test status
Simulation time 24274115 ps
CPU time 0.95 seconds
Started Jun 30 05:04:06 PM PDT 24
Finished Jun 30 05:04:08 PM PDT 24
Peak memory 207140 kb
Host smart-671c0358-6bbc-4e41-9441-44af6d3b470b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677317220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3677317220 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2530422028
Short name T1174
Test name
Test status
Simulation time 32181724 ps
CPU time 0.76 seconds
Started Jun 30 05:04:06 PM PDT 24
Finished Jun 30 05:04:08 PM PDT 24
Peak memory 206960 kb
Host smart-828fd24e-5329-4f5b-9fab-b4455cd28095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530422028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2530422028 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.378447557
Short name T1206
Test name
Test status
Simulation time 126827853 ps
CPU time 2.7 seconds
Started Jun 30 05:04:07 PM PDT 24
Finished Jun 30 05:04:10 PM PDT 24
Peak memory 215756 kb
Host smart-e94b7a55-bf8f-4b5d-99ed-030d70c0374f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378447557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.378447557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1520800693
Short name T1188
Test name
Test status
Simulation time 249070121 ps
CPU time 1.92 seconds
Started Jun 30 05:04:06 PM PDT 24
Finished Jun 30 05:04:09 PM PDT 24
Peak memory 216200 kb
Host smart-7703b8e7-0c99-44a6-a51e-8e178254bc70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520800693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.1520800693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3132087680
Short name T1116
Test name
Test status
Simulation time 414237410 ps
CPU time 3.14 seconds
Started Jun 30 05:04:07 PM PDT 24
Finished Jun 30 05:04:10 PM PDT 24
Peak memory 215516 kb
Host smart-7bcc60b5-335c-4180-929c-4cc433f9ccf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132087680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3132087680 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2788125764
Short name T179
Test name
Test status
Simulation time 141209308 ps
CPU time 2.46 seconds
Started Jun 30 05:04:07 PM PDT 24
Finished Jun 30 05:04:10 PM PDT 24
Peak memory 215568 kb
Host smart-cb7692a8-3094-4fcb-938a-30b032784063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788125764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2788
125764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.532278730
Short name T1218
Test name
Test status
Simulation time 192564739 ps
CPU time 1.66 seconds
Started Jun 30 05:04:12 PM PDT 24
Finished Jun 30 05:04:14 PM PDT 24
Peak memory 223740 kb
Host smart-95510d3b-638b-4743-afcb-26900a12b310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532278730 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.532278730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.2563600133
Short name T1105
Test name
Test status
Simulation time 28150093 ps
CPU time 1.13 seconds
Started Jun 30 05:04:16 PM PDT 24
Finished Jun 30 05:04:17 PM PDT 24
Peak memory 207396 kb
Host smart-42e0feae-9138-4793-b2c0-7d89fbfb8700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563600133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2563600133 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.220772704
Short name T169
Test name
Test status
Simulation time 22618418 ps
CPU time 0.77 seconds
Started Jun 30 05:04:07 PM PDT 24
Finished Jun 30 05:04:08 PM PDT 24
Peak memory 206844 kb
Host smart-1257d313-98b7-46c1-86e3-94538cb42696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220772704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.220772704 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3784926258
Short name T146
Test name
Test status
Simulation time 484103154 ps
CPU time 2.56 seconds
Started Jun 30 05:04:12 PM PDT 24
Finished Jun 30 05:04:15 PM PDT 24
Peak memory 215428 kb
Host smart-62fa351e-1b3d-49e0-86c9-973a84db85f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784926258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.3784926258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1336111489
Short name T1199
Test name
Test status
Simulation time 64484956 ps
CPU time 1.07 seconds
Started Jun 30 05:04:05 PM PDT 24
Finished Jun 30 05:04:06 PM PDT 24
Peak memory 215920 kb
Host smart-52bd9fec-ce8b-4d78-b71f-c5915deb25e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336111489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.1336111489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1427301376
Short name T1210
Test name
Test status
Simulation time 54338926 ps
CPU time 1.46 seconds
Started Jun 30 05:04:06 PM PDT 24
Finished Jun 30 05:04:08 PM PDT 24
Peak memory 215600 kb
Host smart-3820045d-c00c-439a-9749-83837e8330e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427301376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1427301376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.29207636
Short name T1159
Test name
Test status
Simulation time 88385674 ps
CPU time 3 seconds
Started Jun 30 05:04:07 PM PDT 24
Finished Jun 30 05:04:11 PM PDT 24
Peak memory 215492 kb
Host smart-8693a911-fb80-43c7-a9a1-a798f18b50d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.29207636 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.336476213
Short name T1227
Test name
Test status
Simulation time 115369527 ps
CPU time 2.5 seconds
Started Jun 30 05:04:05 PM PDT 24
Finished Jun 30 05:04:08 PM PDT 24
Peak memory 215524 kb
Host smart-e0741336-62d1-4112-8ef0-1c0b36ff538e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336476213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.33647
6213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1032216043
Short name T1138
Test name
Test status
Simulation time 175815572 ps
CPU time 1.72 seconds
Started Jun 30 05:04:13 PM PDT 24
Finished Jun 30 05:04:15 PM PDT 24
Peak memory 223660 kb
Host smart-cb530570-12dc-49d8-9cb5-75507ddb3396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032216043 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1032216043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1258107679
Short name T1099
Test name
Test status
Simulation time 20127066 ps
CPU time 1 seconds
Started Jun 30 05:04:13 PM PDT 24
Finished Jun 30 05:04:15 PM PDT 24
Peak memory 207312 kb
Host smart-a004979d-c38b-4fab-845e-6eb844e049a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258107679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1258107679 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2358693142
Short name T1101
Test name
Test status
Simulation time 48499511 ps
CPU time 0.8 seconds
Started Jun 30 05:04:12 PM PDT 24
Finished Jun 30 05:04:13 PM PDT 24
Peak memory 207008 kb
Host smart-92061baa-3995-4275-8516-133245dce48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358693142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2358693142 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1170133514
Short name T1153
Test name
Test status
Simulation time 91102099 ps
CPU time 1.51 seconds
Started Jun 30 05:04:11 PM PDT 24
Finished Jun 30 05:04:13 PM PDT 24
Peak memory 215600 kb
Host smart-5036a36f-cc82-4ff7-99db-3d9dcdc07d2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170133514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.1170133514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1843204041
Short name T1183
Test name
Test status
Simulation time 214355844 ps
CPU time 1.23 seconds
Started Jun 30 05:04:12 PM PDT 24
Finished Jun 30 05:04:14 PM PDT 24
Peak memory 215760 kb
Host smart-693e9fea-70d9-4b34-98ca-a4ce603f53cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843204041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1843204041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.568902029
Short name T1201
Test name
Test status
Simulation time 130524720 ps
CPU time 2.4 seconds
Started Jun 30 05:04:16 PM PDT 24
Finished Jun 30 05:04:18 PM PDT 24
Peak memory 223628 kb
Host smart-6ce4157f-e41b-450c-b5d5-50a08a6f009a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568902029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.568902029 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1287319322
Short name T177
Test name
Test status
Simulation time 355766313 ps
CPU time 4.08 seconds
Started Jun 30 05:04:14 PM PDT 24
Finished Jun 30 05:04:18 PM PDT 24
Peak memory 215516 kb
Host smart-c1f60584-b965-457d-877a-a49f03766a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287319322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1287
319322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2391482925
Short name T1203
Test name
Test status
Simulation time 131450783 ps
CPU time 2.39 seconds
Started Jun 30 05:04:21 PM PDT 24
Finished Jun 30 05:04:24 PM PDT 24
Peak memory 218316 kb
Host smart-aaff813c-14c4-49b9-a284-407e6f74bea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391482925 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2391482925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1137900707
Short name T1150
Test name
Test status
Simulation time 24525049 ps
CPU time 1.06 seconds
Started Jun 30 05:04:20 PM PDT 24
Finished Jun 30 05:04:22 PM PDT 24
Peak memory 207376 kb
Host smart-2f6d38ef-cb7f-4291-baab-e51be72b6c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137900707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1137900707 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.3721097798
Short name T1184
Test name
Test status
Simulation time 16715515 ps
CPU time 0.81 seconds
Started Jun 30 05:04:20 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 206916 kb
Host smart-4a8745d8-1143-4699-841e-e7dfcc8e91cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721097798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3721097798 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.919433643
Short name T1192
Test name
Test status
Simulation time 48206170 ps
CPU time 1.48 seconds
Started Jun 30 05:04:20 PM PDT 24
Finished Jun 30 05:04:22 PM PDT 24
Peak memory 215920 kb
Host smart-f41bb042-36b6-4b33-ab20-437d58cb2c0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919433643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.919433643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2937918807
Short name T1107
Test name
Test status
Simulation time 19363588 ps
CPU time 1.11 seconds
Started Jun 30 05:04:11 PM PDT 24
Finished Jun 30 05:04:13 PM PDT 24
Peak memory 215856 kb
Host smart-4669e124-e388-49ad-9956-1541781bfd2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937918807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.2937918807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1355838058
Short name T1128
Test name
Test status
Simulation time 100760196 ps
CPU time 1.8 seconds
Started Jun 30 05:04:15 PM PDT 24
Finished Jun 30 05:04:17 PM PDT 24
Peak memory 215440 kb
Host smart-28cc3feb-c36e-48b1-8db5-cd380d0e065e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355838058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.1355838058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1171588915
Short name T1171
Test name
Test status
Simulation time 446174772 ps
CPU time 3.3 seconds
Started Jun 30 05:04:13 PM PDT 24
Finished Jun 30 05:04:17 PM PDT 24
Peak memory 215540 kb
Host smart-ce059d0c-7f6f-4a49-b801-661974811558
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171588915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1171588915 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2146168804
Short name T1179
Test name
Test status
Simulation time 601600441 ps
CPU time 4.1 seconds
Started Jun 30 05:04:15 PM PDT 24
Finished Jun 30 05:04:19 PM PDT 24
Peak memory 215028 kb
Host smart-cf4d2561-ffa3-4163-bf1d-5a009cb7b08a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146168804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2146
168804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2307086731
Short name T184
Test name
Test status
Simulation time 1531393695 ps
CPU time 9.33 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:20 PM PDT 24
Peak memory 215548 kb
Host smart-dd900205-88ad-429c-b01b-ea95d6d22b28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307086731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2307086
731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1425646105
Short name T1096
Test name
Test status
Simulation time 1199911425 ps
CPU time 8.11 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:19 PM PDT 24
Peak memory 207332 kb
Host smart-7718d38e-ec94-4deb-9650-cc5cecfd9d02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425646105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1425646
105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3518256528
Short name T1091
Test name
Test status
Simulation time 101940572 ps
CPU time 1.12 seconds
Started Jun 30 05:03:12 PM PDT 24
Finished Jun 30 05:03:14 PM PDT 24
Peak memory 207400 kb
Host smart-a98951c3-6b94-4e2d-95e8-fb7d5220f7a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518256528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3518256
528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2469656892
Short name T1112
Test name
Test status
Simulation time 134657185 ps
CPU time 1.56 seconds
Started Jun 30 05:03:11 PM PDT 24
Finished Jun 30 05:03:14 PM PDT 24
Peak memory 215544 kb
Host smart-25686bab-1a3d-43a2-82c9-009bec7e7b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469656892 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2469656892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3191240296
Short name T1093
Test name
Test status
Simulation time 22147980 ps
CPU time 0.95 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 207100 kb
Host smart-2f4805ca-5d41-4bc3-92ae-b71e51814cef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191240296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3191240296 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2883475922
Short name T1221
Test name
Test status
Simulation time 50873901 ps
CPU time 0.77 seconds
Started Jun 30 05:03:11 PM PDT 24
Finished Jun 30 05:03:13 PM PDT 24
Peak memory 206964 kb
Host smart-501255a8-1c50-4e2a-ad5a-eeb39a97c819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883475922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2883475922 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2796575846
Short name T1080
Test name
Test status
Simulation time 52285087 ps
CPU time 1.15 seconds
Started Jun 30 05:03:11 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 215444 kb
Host smart-dc2e32ca-a534-4b13-a548-d05350995ae6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796575846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.2796575846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3996163600
Short name T1147
Test name
Test status
Simulation time 40560138 ps
CPU time 0.72 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 207000 kb
Host smart-0792467e-1e4c-4875-9eb5-6f677e58490a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996163600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3996163600
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1144209892
Short name T1135
Test name
Test status
Simulation time 54921954 ps
CPU time 1.62 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 215524 kb
Host smart-3e806815-0f15-4138-b932-289f40576671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144209892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1144209892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.774194125
Short name T108
Test name
Test status
Simulation time 26432875 ps
CPU time 0.98 seconds
Started Jun 30 05:03:10 PM PDT 24
Finished Jun 30 05:03:11 PM PDT 24
Peak memory 215684 kb
Host smart-8bd85ac8-c00b-4cfd-9bec-60eefdf2cce0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774194125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e
rrors.774194125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2849023691
Short name T120
Test name
Test status
Simulation time 81336732 ps
CPU time 2.29 seconds
Started Jun 30 05:03:09 PM PDT 24
Finished Jun 30 05:03:12 PM PDT 24
Peak memory 215480 kb
Host smart-4c1f53b8-2c1c-4493-aea5-af8f0d52659a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849023691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2849023691 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.299284303
Short name T1102
Test name
Test status
Simulation time 23857996 ps
CPU time 0.78 seconds
Started Jun 30 05:04:22 PM PDT 24
Finished Jun 30 05:04:23 PM PDT 24
Peak memory 207000 kb
Host smart-d6d8caad-4e60-4f55-bf9b-2b95dbe0b37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299284303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.299284303 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.1623112038
Short name T1209
Test name
Test status
Simulation time 19315823 ps
CPU time 0.8 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:20 PM PDT 24
Peak memory 207016 kb
Host smart-8b7df9b9-1eeb-4b7d-a55b-9dd1c305b46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623112038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1623112038 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.651410852
Short name T1175
Test name
Test status
Simulation time 36080303 ps
CPU time 0.76 seconds
Started Jun 30 05:04:20 PM PDT 24
Finished Jun 30 05:04:22 PM PDT 24
Peak memory 206924 kb
Host smart-e2f66489-a245-4fbd-b20e-ed8d402486ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651410852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.651410852 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2526920332
Short name T1145
Test name
Test status
Simulation time 11814857 ps
CPU time 0.76 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 207004 kb
Host smart-3db3512d-3e0f-4e6f-bdcb-8f90fd69c5f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526920332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2526920332 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.4284038743
Short name T168
Test name
Test status
Simulation time 33257032 ps
CPU time 0.76 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 207004 kb
Host smart-5d43b3a7-2a96-4358-b98f-d40e7d04c0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284038743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.4284038743 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.4109406819
Short name T1235
Test name
Test status
Simulation time 40070908 ps
CPU time 0.79 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 207024 kb
Host smart-f966ef58-d07e-49cd-8d2a-d1e4f5e1b2d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109406819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.4109406819 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.3033903645
Short name T1157
Test name
Test status
Simulation time 21584506 ps
CPU time 0.75 seconds
Started Jun 30 05:04:18 PM PDT 24
Finished Jun 30 05:04:19 PM PDT 24
Peak memory 206872 kb
Host smart-7ac77da7-7eef-441a-86a7-e8f32a9a3893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033903645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3033903645 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2992005618
Short name T1111
Test name
Test status
Simulation time 16281483 ps
CPU time 0.79 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 206964 kb
Host smart-260987ba-e2fd-45ab-b65b-4d02398e58f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992005618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2992005618 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.219269133
Short name T1143
Test name
Test status
Simulation time 21668045 ps
CPU time 0.81 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:20 PM PDT 24
Peak memory 207012 kb
Host smart-122a10de-7d19-4761-a407-d088f21db5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219269133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.219269133 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.1665753671
Short name T1122
Test name
Test status
Simulation time 18509943 ps
CPU time 0.79 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 207024 kb
Host smart-7b352e78-168f-490b-91d1-5bf21594b20e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665753671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1665753671 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3593693996
Short name T1098
Test name
Test status
Simulation time 132611135 ps
CPU time 7.83 seconds
Started Jun 30 05:03:16 PM PDT 24
Finished Jun 30 05:03:24 PM PDT 24
Peak memory 215548 kb
Host smart-b6560333-c29c-4cd3-ad80-90e1ed452280
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593693996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3593693
996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1299922928
Short name T1176
Test name
Test status
Simulation time 998471901 ps
CPU time 18.42 seconds
Started Jun 30 05:03:20 PM PDT 24
Finished Jun 30 05:03:39 PM PDT 24
Peak memory 207388 kb
Host smart-2f87f28d-e494-4576-a0fc-fb95f983eb22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299922928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1299922
928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.61198169
Short name T1108
Test name
Test status
Simulation time 22393857 ps
CPU time 0.96 seconds
Started Jun 30 05:03:17 PM PDT 24
Finished Jun 30 05:03:19 PM PDT 24
Peak memory 207176 kb
Host smart-18d45a71-9003-4b58-b34e-c2aef9c6b886
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61198169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.61198169
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1673524398
Short name T1215
Test name
Test status
Simulation time 52696607 ps
CPU time 2.34 seconds
Started Jun 30 05:03:19 PM PDT 24
Finished Jun 30 05:03:22 PM PDT 24
Peak memory 216708 kb
Host smart-fb45e258-5015-403f-b217-a80ed7f48c59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673524398 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1673524398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.344429028
Short name T1211
Test name
Test status
Simulation time 27655632 ps
CPU time 1.01 seconds
Started Jun 30 05:03:19 PM PDT 24
Finished Jun 30 05:03:20 PM PDT 24
Peak memory 207324 kb
Host smart-0bbe860f-ac9a-4ee4-91c5-bc9371c25440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344429028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.344429028 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1484244500
Short name T1115
Test name
Test status
Simulation time 22118182 ps
CPU time 0.71 seconds
Started Jun 30 05:03:21 PM PDT 24
Finished Jun 30 05:03:22 PM PDT 24
Peak memory 207000 kb
Host smart-542cc1db-c929-4a77-98cc-9969cbbd58e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484244500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1484244500 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1873932701
Short name T138
Test name
Test status
Simulation time 104702176 ps
CPU time 1.15 seconds
Started Jun 30 05:03:17 PM PDT 24
Finished Jun 30 05:03:18 PM PDT 24
Peak memory 215376 kb
Host smart-8d05295f-a832-4b24-b958-bfb5317484f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873932701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.1873932701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3188070675
Short name T1156
Test name
Test status
Simulation time 18292569 ps
CPU time 0.74 seconds
Started Jun 30 05:03:18 PM PDT 24
Finished Jun 30 05:03:20 PM PDT 24
Peak memory 207104 kb
Host smart-9e40fee0-c9d5-4631-8a2f-164b80f4ebaa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188070675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3188070675
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4124390602
Short name T1140
Test name
Test status
Simulation time 117549301 ps
CPU time 2.6 seconds
Started Jun 30 05:03:17 PM PDT 24
Finished Jun 30 05:03:21 PM PDT 24
Peak memory 215900 kb
Host smart-4672dfa1-8f54-4235-ac6b-d577f136dc9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124390602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.4124390602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3707128456
Short name T99
Test name
Test status
Simulation time 40306132 ps
CPU time 0.99 seconds
Started Jun 30 05:03:21 PM PDT 24
Finished Jun 30 05:03:22 PM PDT 24
Peak memory 215696 kb
Host smart-f9176d7d-bf35-4565-9da5-9b022fa6c24c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707128456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.3707128456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1580742067
Short name T102
Test name
Test status
Simulation time 240565021 ps
CPU time 1.93 seconds
Started Jun 30 05:03:17 PM PDT 24
Finished Jun 30 05:03:20 PM PDT 24
Peak memory 215920 kb
Host smart-e910783e-1427-43f6-915e-77d49c0b64f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580742067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.1580742067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.835880881
Short name T1164
Test name
Test status
Simulation time 76002827 ps
CPU time 2.35 seconds
Started Jun 30 05:03:19 PM PDT 24
Finished Jun 30 05:03:22 PM PDT 24
Peak memory 223584 kb
Host smart-4eb5f8d0-8151-4902-92ad-179ddb83720d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835880881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.835880881 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.847478482
Short name T175
Test name
Test status
Simulation time 1645958056 ps
CPU time 4.25 seconds
Started Jun 30 05:03:18 PM PDT 24
Finished Jun 30 05:03:22 PM PDT 24
Peak memory 215532 kb
Host smart-4df682b6-e493-4cb0-ade9-3134d37d683f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847478482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.847478
482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.4093503909
Short name T1224
Test name
Test status
Simulation time 39440853 ps
CPU time 0.7 seconds
Started Jun 30 05:04:17 PM PDT 24
Finished Jun 30 05:04:18 PM PDT 24
Peak memory 206904 kb
Host smart-f96441a2-e51b-4e36-a157-767d66d1fe32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093503909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.4093503909 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3739207074
Short name T1097
Test name
Test status
Simulation time 78243188 ps
CPU time 0.75 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:20 PM PDT 24
Peak memory 206976 kb
Host smart-c6eafb32-32cc-4cc8-b86f-7aa1cef57d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739207074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3739207074 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.2606598001
Short name T1185
Test name
Test status
Simulation time 14803839 ps
CPU time 0.76 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:20 PM PDT 24
Peak memory 206992 kb
Host smart-35b8eb15-3741-4364-b5a8-159362a558ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606598001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2606598001 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.3673707387
Short name T1095
Test name
Test status
Simulation time 26783443 ps
CPU time 0.74 seconds
Started Jun 30 05:04:20 PM PDT 24
Finished Jun 30 05:04:22 PM PDT 24
Peak memory 207012 kb
Host smart-67894db7-e3e7-4a87-94ab-661fff36a3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673707387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3673707387 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.2787467027
Short name T1088
Test name
Test status
Simulation time 14950490 ps
CPU time 0.74 seconds
Started Jun 30 05:04:20 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 207004 kb
Host smart-ed62500b-0c29-4b4e-bc0d-55d157311e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787467027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2787467027 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.989896251
Short name T171
Test name
Test status
Simulation time 47166184 ps
CPU time 0.79 seconds
Started Jun 30 05:04:20 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 207000 kb
Host smart-ff3836bc-1191-488b-b65e-05249945466b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989896251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.989896251 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.3499993116
Short name T170
Test name
Test status
Simulation time 16595632 ps
CPU time 0.8 seconds
Started Jun 30 05:04:19 PM PDT 24
Finished Jun 30 05:04:20 PM PDT 24
Peak memory 207016 kb
Host smart-6b9f59bf-8707-4aea-bc5c-ee6653dd4256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499993116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3499993116 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.1864991590
Short name T1225
Test name
Test status
Simulation time 42799595 ps
CPU time 0.75 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:27 PM PDT 24
Peak memory 206976 kb
Host smart-36448fc4-ac2d-41cf-b653-69e331d83691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864991590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1864991590 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.49313992
Short name T1182
Test name
Test status
Simulation time 99057909 ps
CPU time 0.74 seconds
Started Jun 30 05:04:25 PM PDT 24
Finished Jun 30 05:04:26 PM PDT 24
Peak memory 206980 kb
Host smart-40aadb2f-190d-4bc1-b810-623ec664edd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49313992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.49313992 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.54811590
Short name T1114
Test name
Test status
Simulation time 15423567 ps
CPU time 0.76 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:28 PM PDT 24
Peak memory 206920 kb
Host smart-92532ec7-a8ea-44fd-af9b-c504ffae261b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54811590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.54811590 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2712594646
Short name T1189
Test name
Test status
Simulation time 4479703851 ps
CPU time 4.92 seconds
Started Jun 30 05:03:26 PM PDT 24
Finished Jun 30 05:03:31 PM PDT 24
Peak memory 207296 kb
Host smart-3a62bc11-a7a1-4dbd-96c4-f0c019e90e68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712594646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2712594
646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1570219143
Short name T1208
Test name
Test status
Simulation time 1125010339 ps
CPU time 15.21 seconds
Started Jun 30 05:03:27 PM PDT 24
Finished Jun 30 05:03:42 PM PDT 24
Peak memory 207320 kb
Host smart-dcac145a-727a-4978-8df3-c41d118ff394
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570219143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1570219
143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1734366050
Short name T1233
Test name
Test status
Simulation time 31003552 ps
CPU time 1.03 seconds
Started Jun 30 05:03:27 PM PDT 24
Finished Jun 30 05:03:28 PM PDT 24
Peak memory 207356 kb
Host smart-72e9ec82-f50a-492e-aa75-08fc912638c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734366050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1734366
050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3743175327
Short name T1152
Test name
Test status
Simulation time 44386505 ps
CPU time 1.64 seconds
Started Jun 30 05:03:35 PM PDT 24
Finished Jun 30 05:03:38 PM PDT 24
Peak memory 216592 kb
Host smart-114fbe2a-5821-4b77-9450-a312251d5e1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743175327 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3743175327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2757509221
Short name T1120
Test name
Test status
Simulation time 58440773 ps
CPU time 1.09 seconds
Started Jun 30 05:03:27 PM PDT 24
Finished Jun 30 05:03:28 PM PDT 24
Peak memory 207300 kb
Host smart-41c0dcb5-fb76-4db1-b5a0-865fd06de24a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757509221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2757509221 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3416294506
Short name T1103
Test name
Test status
Simulation time 48188565 ps
CPU time 0.71 seconds
Started Jun 30 05:03:26 PM PDT 24
Finished Jun 30 05:03:27 PM PDT 24
Peak memory 207044 kb
Host smart-0f8e6bb1-d618-4444-a117-e78f92f5ac80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416294506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3416294506 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3835241031
Short name T136
Test name
Test status
Simulation time 112605772 ps
CPU time 1.42 seconds
Started Jun 30 05:03:27 PM PDT 24
Finished Jun 30 05:03:29 PM PDT 24
Peak memory 215444 kb
Host smart-2ef64cd1-f6c2-4bc8-a0b2-c0c1e9b3b2e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835241031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3835241031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1978290593
Short name T1161
Test name
Test status
Simulation time 14198518 ps
CPU time 0.72 seconds
Started Jun 30 05:03:28 PM PDT 24
Finished Jun 30 05:03:29 PM PDT 24
Peak memory 207056 kb
Host smart-446dab88-c4ae-44eb-bbfb-9480c870351f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978290593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1978290593
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2464658209
Short name T1213
Test name
Test status
Simulation time 110882032 ps
CPU time 1.64 seconds
Started Jun 30 05:03:35 PM PDT 24
Finished Jun 30 05:03:37 PM PDT 24
Peak memory 215900 kb
Host smart-165969b8-736a-49dc-bc45-a70011db3d7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464658209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.2464658209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1993368005
Short name T1186
Test name
Test status
Simulation time 32881204 ps
CPU time 1.17 seconds
Started Jun 30 05:03:29 PM PDT 24
Finished Jun 30 05:03:31 PM PDT 24
Peak memory 215876 kb
Host smart-aa48858f-972b-4d70-913e-aa2b01496193
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993368005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.1993368005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2835657360
Short name T1127
Test name
Test status
Simulation time 219082433 ps
CPU time 1.64 seconds
Started Jun 30 05:03:27 PM PDT 24
Finished Jun 30 05:03:29 PM PDT 24
Peak memory 215584 kb
Host smart-bbd4eb36-8216-468b-9e66-b4ab079a37d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835657360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.2835657360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.983871565
Short name T1133
Test name
Test status
Simulation time 164176775 ps
CPU time 2.28 seconds
Started Jun 30 05:03:27 PM PDT 24
Finished Jun 30 05:03:29 PM PDT 24
Peak memory 215496 kb
Host smart-1318ecfc-e816-4668-9f90-9de51e0a04bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983871565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.983871565 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1473965518
Short name T178
Test name
Test status
Simulation time 166313101 ps
CPU time 2.94 seconds
Started Jun 30 05:03:27 PM PDT 24
Finished Jun 30 05:03:31 PM PDT 24
Peak memory 215600 kb
Host smart-d9060718-6ec8-444a-ae87-7b08bd77a036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473965518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.14739
65518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.4170640964
Short name T152
Test name
Test status
Simulation time 14497011 ps
CPU time 0.77 seconds
Started Jun 30 05:04:25 PM PDT 24
Finished Jun 30 05:04:26 PM PDT 24
Peak memory 206996 kb
Host smart-21e3724f-993a-4605-8b58-8c462731712e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170640964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.4170640964 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.3764319371
Short name T1151
Test name
Test status
Simulation time 21684158 ps
CPU time 0.79 seconds
Started Jun 30 05:04:27 PM PDT 24
Finished Jun 30 05:04:29 PM PDT 24
Peak memory 206964 kb
Host smart-e3dd1ac6-1c8e-4625-acf7-a5f609018c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764319371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3764319371 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.578743582
Short name T116
Test name
Test status
Simulation time 15957242 ps
CPU time 0.78 seconds
Started Jun 30 05:04:25 PM PDT 24
Finished Jun 30 05:04:27 PM PDT 24
Peak memory 207024 kb
Host smart-fafcbdc3-1e0f-43d3-855f-e8e276023905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578743582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.578743582 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.656596289
Short name T172
Test name
Test status
Simulation time 40348059 ps
CPU time 0.76 seconds
Started Jun 30 05:04:30 PM PDT 24
Finished Jun 30 05:04:31 PM PDT 24
Peak memory 207012 kb
Host smart-62601a5b-d1e0-489c-aab9-955402906c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656596289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.656596289 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.153437365
Short name T1194
Test name
Test status
Simulation time 12216148 ps
CPU time 0.75 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:27 PM PDT 24
Peak memory 207012 kb
Host smart-eb35dab8-4e27-42dd-b170-e19d3fa909f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153437365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.153437365 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2790058108
Short name T1130
Test name
Test status
Simulation time 18046218 ps
CPU time 0.79 seconds
Started Jun 30 05:04:27 PM PDT 24
Finished Jun 30 05:04:29 PM PDT 24
Peak memory 206988 kb
Host smart-e29590d9-2e88-4655-872d-40fb06b36d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790058108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2790058108 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.4038261110
Short name T1124
Test name
Test status
Simulation time 15823177 ps
CPU time 0.75 seconds
Started Jun 30 05:04:28 PM PDT 24
Finished Jun 30 05:04:29 PM PDT 24
Peak memory 207004 kb
Host smart-47c53034-e118-46df-9201-ead43599c74b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038261110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.4038261110 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.3064166001
Short name T1196
Test name
Test status
Simulation time 16643001 ps
CPU time 0.83 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:28 PM PDT 24
Peak memory 206960 kb
Host smart-20e25d43-8e52-40bb-a140-705df0693705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064166001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3064166001 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2805270380
Short name T1121
Test name
Test status
Simulation time 14185793 ps
CPU time 0.81 seconds
Started Jun 30 05:04:30 PM PDT 24
Finished Jun 30 05:04:31 PM PDT 24
Peak memory 207008 kb
Host smart-12b5e298-27c0-46b7-82ff-cd28aa5aebee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805270380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2805270380 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1237326525
Short name T1142
Test name
Test status
Simulation time 12439361 ps
CPU time 0.74 seconds
Started Jun 30 05:04:26 PM PDT 24
Finished Jun 30 05:04:28 PM PDT 24
Peak memory 207016 kb
Host smart-0ec7f685-27aa-4017-818a-e6cca4e40296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237326525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1237326525 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.489295920
Short name T1220
Test name
Test status
Simulation time 60090984 ps
CPU time 1.82 seconds
Started Jun 30 05:03:35 PM PDT 24
Finished Jun 30 05:03:38 PM PDT 24
Peak memory 223640 kb
Host smart-49ad0c36-c99c-46d2-a184-60c3561e21d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489295920 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.489295920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1613415091
Short name T182
Test name
Test status
Simulation time 30229827 ps
CPU time 1.14 seconds
Started Jun 30 05:03:36 PM PDT 24
Finished Jun 30 05:03:37 PM PDT 24
Peak memory 207228 kb
Host smart-003c674d-7cc4-45a1-8047-a4093d8ffff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613415091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1613415091 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3448924446
Short name T1223
Test name
Test status
Simulation time 94169627 ps
CPU time 0.74 seconds
Started Jun 30 05:03:37 PM PDT 24
Finished Jun 30 05:03:38 PM PDT 24
Peak memory 206896 kb
Host smart-5666f9dc-48e1-4838-903b-dff5b5b3cded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448924446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3448924446 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2224994906
Short name T1226
Test name
Test status
Simulation time 487783057 ps
CPU time 2.4 seconds
Started Jun 30 05:03:35 PM PDT 24
Finished Jun 30 05:03:39 PM PDT 24
Peak memory 215488 kb
Host smart-5c1a79f4-8dff-47e5-8792-1a97953aefff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224994906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.2224994906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.517788968
Short name T105
Test name
Test status
Simulation time 84262091 ps
CPU time 1.06 seconds
Started Jun 30 05:03:35 PM PDT 24
Finished Jun 30 05:03:36 PM PDT 24
Peak memory 215816 kb
Host smart-34bf6c8c-4554-48cf-918b-c0144eb99c9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517788968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.517788968 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2356232089
Short name T106
Test name
Test status
Simulation time 138652060 ps
CPU time 2.84 seconds
Started Jun 30 05:03:36 PM PDT 24
Finished Jun 30 05:03:39 PM PDT 24
Peak memory 215604 kb
Host smart-8b2bdf56-ae8f-4f34-8c51-c994ded08930
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356232089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.2356232089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3304794568
Short name T1212
Test name
Test status
Simulation time 115219545 ps
CPU time 1.85 seconds
Started Jun 30 05:03:34 PM PDT 24
Finished Jun 30 05:03:37 PM PDT 24
Peak memory 215548 kb
Host smart-76640baf-a729-4882-adbb-f47abd10dc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304794568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3304794568 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2227710913
Short name T1139
Test name
Test status
Simulation time 100695931 ps
CPU time 2.37 seconds
Started Jun 30 05:03:34 PM PDT 24
Finished Jun 30 05:03:37 PM PDT 24
Peak memory 207352 kb
Host smart-0087d69a-9d3b-43f4-87ae-f2a249ad8848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227710913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.22277
10913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.563409209
Short name T1082
Test name
Test status
Simulation time 25243964 ps
CPU time 1.7 seconds
Started Jun 30 05:03:42 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 216224 kb
Host smart-a87d6576-084f-4a7f-804e-a4b5dd6cdd23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563409209 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.563409209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.50949917
Short name T1084
Test name
Test status
Simulation time 14973396 ps
CPU time 0.89 seconds
Started Jun 30 05:03:42 PM PDT 24
Finished Jun 30 05:03:43 PM PDT 24
Peak memory 207164 kb
Host smart-2cdbf05d-3d2c-4b04-9695-41be772ff122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50949917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.50949917 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2511038052
Short name T1081
Test name
Test status
Simulation time 87263649 ps
CPU time 2.37 seconds
Started Jun 30 05:03:45 PM PDT 24
Finished Jun 30 05:03:48 PM PDT 24
Peak memory 215432 kb
Host smart-82fb12fc-a0b3-4b87-ab2d-6ca607b99cdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511038052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.2511038052 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.233322333
Short name T97
Test name
Test status
Simulation time 35333114 ps
CPU time 1.77 seconds
Started Jun 30 05:03:37 PM PDT 24
Finished Jun 30 05:03:39 PM PDT 24
Peak memory 215860 kb
Host smart-276f6f37-a64b-4a73-8da8-362a5784e4a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233322333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_
shadow_reg_errors_with_csr_rw.233322333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.636927401
Short name T154
Test name
Test status
Simulation time 151932644 ps
CPU time 3.77 seconds
Started Jun 30 05:03:35 PM PDT 24
Finished Jun 30 05:03:39 PM PDT 24
Peak memory 215516 kb
Host smart-d066b3b2-5df8-4692-82b4-8ea32f8b871e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636927401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.636927401 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3638455201
Short name T1216
Test name
Test status
Simulation time 248410146 ps
CPU time 5.11 seconds
Started Jun 30 05:03:45 PM PDT 24
Finished Jun 30 05:03:50 PM PDT 24
Peak memory 218460 kb
Host smart-aabe9d47-dc10-4d23-9629-afb4843e5398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638455201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.36384
55201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2224140660
Short name T1173
Test name
Test status
Simulation time 64100699 ps
CPU time 1.41 seconds
Started Jun 30 05:03:42 PM PDT 24
Finished Jun 30 05:03:44 PM PDT 24
Peak memory 215368 kb
Host smart-4983046a-1c74-4d01-a560-898ddc4c006d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224140660 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2224140660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2286412632
Short name T1214
Test name
Test status
Simulation time 23049073 ps
CPU time 0.92 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 207168 kb
Host smart-6984b90c-9c9f-42eb-9dac-c445e0e01d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286412632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2286412632 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3780911457
Short name T1187
Test name
Test status
Simulation time 16803067 ps
CPU time 0.73 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 206924 kb
Host smart-356204ff-8850-411b-990a-1b6735b8a39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780911457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3780911457 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2024505769
Short name T1177
Test name
Test status
Simulation time 35751253 ps
CPU time 2.04 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:46 PM PDT 24
Peak memory 216068 kb
Host smart-c7385c9d-edf8-4912-98e9-0a9e8456b6ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024505769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2024505769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1818527997
Short name T104
Test name
Test status
Simulation time 751017559 ps
CPU time 1.39 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 216148 kb
Host smart-a1059bad-91bb-4d57-b442-bb50488db526
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818527997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1818527997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.916253156
Short name T1219
Test name
Test status
Simulation time 224146912 ps
CPU time 2.93 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:47 PM PDT 24
Peak memory 215532 kb
Host smart-ebb6f761-b1d2-4d09-b7c2-3636c7cd9e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916253156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.916253156 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.129171361
Short name T1198
Test name
Test status
Simulation time 383627581 ps
CPU time 2.67 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:46 PM PDT 24
Peak memory 215516 kb
Host smart-03118f2f-402d-49ef-b0a7-d4cc1388f3d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129171361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.129171
361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3095180830
Short name T151
Test name
Test status
Simulation time 62176345 ps
CPU time 1.74 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 223728 kb
Host smart-1eca0e95-815d-47a7-bdc7-4457ce2439ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095180830 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3095180830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.4030694849
Short name T1113
Test name
Test status
Simulation time 26583748 ps
CPU time 1.12 seconds
Started Jun 30 05:03:45 PM PDT 24
Finished Jun 30 05:03:47 PM PDT 24
Peak memory 207364 kb
Host smart-03c2bd2d-44d3-4f91-9e5d-32c0c338de81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030694849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4030694849 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.1009054926
Short name T1123
Test name
Test status
Simulation time 15885158 ps
CPU time 0.84 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 206916 kb
Host smart-2e40cd28-7e91-4162-90ff-76f3f71296ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009054926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1009054926 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1752167571
Short name T1086
Test name
Test status
Simulation time 36259986 ps
CPU time 2.14 seconds
Started Jun 30 05:03:42 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 215576 kb
Host smart-bd1c01f8-1e29-4277-af1c-48295c237e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752167571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.1752167571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2712689855
Short name T1117
Test name
Test status
Simulation time 40280042 ps
CPU time 1.03 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 215880 kb
Host smart-0d923236-3ac9-419d-a572-156381eaf531
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712689855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2712689855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2170269147
Short name T103
Test name
Test status
Simulation time 252548811 ps
CPU time 1.73 seconds
Started Jun 30 05:03:44 PM PDT 24
Finished Jun 30 05:03:46 PM PDT 24
Peak memory 215932 kb
Host smart-42e7731b-f76b-43be-ab14-85be84632559
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170269147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.2170269147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2104018601
Short name T132
Test name
Test status
Simulation time 94620879 ps
CPU time 1.81 seconds
Started Jun 30 05:03:43 PM PDT 24
Finished Jun 30 05:03:46 PM PDT 24
Peak memory 215492 kb
Host smart-e2234b2c-878d-4577-8d9d-b384b84eb1fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104018601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2104018601 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3037125957
Short name T114
Test name
Test status
Simulation time 173582025 ps
CPU time 4.13 seconds
Started Jun 30 05:03:45 PM PDT 24
Finished Jun 30 05:03:50 PM PDT 24
Peak memory 215560 kb
Host smart-dac60590-2c98-4ff7-81a7-e3b0cad74d61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037125957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.30371
25957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3535040257
Short name T1090
Test name
Test status
Simulation time 204297209 ps
CPU time 2.23 seconds
Started Jun 30 05:03:55 PM PDT 24
Finished Jun 30 05:03:58 PM PDT 24
Peak memory 216504 kb
Host smart-dd3b53aa-10bb-4ca2-a104-0e2cbe6272ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535040257 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3535040257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1553303719
Short name T145
Test name
Test status
Simulation time 197962882 ps
CPU time 1.12 seconds
Started Jun 30 05:03:56 PM PDT 24
Finished Jun 30 05:03:57 PM PDT 24
Peak memory 207404 kb
Host smart-9ba28b87-5071-4de0-8767-f9895b79e85d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553303719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1553303719 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.1412838423
Short name T1134
Test name
Test status
Simulation time 41597103 ps
CPU time 0.78 seconds
Started Jun 30 05:03:52 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 206924 kb
Host smart-c4291762-9011-4294-8e5e-58281f0de9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412838423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1412838423 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.614630204
Short name T1109
Test name
Test status
Simulation time 77447597 ps
CPU time 1.44 seconds
Started Jun 30 05:03:51 PM PDT 24
Finished Jun 30 05:03:53 PM PDT 24
Peak memory 215688 kb
Host smart-2d45e92d-951e-4246-8128-e92378e36137
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614630204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_
outstanding.614630204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.969796167
Short name T1232
Test name
Test status
Simulation time 66183827 ps
CPU time 1.75 seconds
Started Jun 30 05:03:42 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 215820 kb
Host smart-2ef021bd-eef8-47cd-ac2b-776842a6a7bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969796167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_
shadow_reg_errors_with_csr_rw.969796167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.202736880
Short name T122
Test name
Test status
Simulation time 129984987 ps
CPU time 3.05 seconds
Started Jun 30 05:03:45 PM PDT 24
Finished Jun 30 05:03:49 PM PDT 24
Peak memory 215412 kb
Host smart-bd05670b-5a8e-4ec4-b9f3-e761d5c77f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202736880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.202736880 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3503673317
Short name T1205
Test name
Test status
Simulation time 191040765 ps
CPU time 2.31 seconds
Started Jun 30 05:03:44 PM PDT 24
Finished Jun 30 05:03:48 PM PDT 24
Peak memory 207312 kb
Host smart-513638f2-21c1-405e-bc5a-006bd8d979cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503673317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.35036
73317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.1445845583
Short name T347
Test name
Test status
Simulation time 77687635 ps
CPU time 0.76 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 05:51:36 PM PDT 24
Peak memory 205628 kb
Host smart-b934f020-63da-4512-9fc5-e5c626e39251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445845583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1445845583 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.2580395145
Short name T694
Test name
Test status
Simulation time 3477328930 ps
CPU time 184.66 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 05:54:31 PM PDT 24
Peak memory 240112 kb
Host smart-64cbb469-1aad-4772-816e-8f55ba262fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580395145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2580395145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.2521159070
Short name T407
Test name
Test status
Simulation time 11477389170 ps
CPU time 185.51 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 05:54:32 PM PDT 24
Peak memory 237200 kb
Host smart-b0ccf7c7-4ae8-4264-af37-d528df6ef64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521159070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2521159070 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2923140955
Short name T778
Test name
Test status
Simulation time 21137065877 ps
CPU time 451.41 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 05:58:58 PM PDT 24
Peak memory 230252 kb
Host smart-0331f46b-bccf-4545-a1c6-f845dd9e98b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923140955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2923140955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.4253655014
Short name T607
Test name
Test status
Simulation time 2827565270 ps
CPU time 26.51 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 05:51:53 PM PDT 24
Peak memory 224276 kb
Host smart-16e3ca26-29cc-4020-9b57-172c634238d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253655014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.4253655014 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.2863450176
Short name T353
Test name
Test status
Simulation time 399956672 ps
CPU time 28.55 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:52:03 PM PDT 24
Peak memory 224132 kb
Host smart-57cc6c33-1682-48e9-bd71-753c9704b27e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2863450176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2863450176 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.2066250723
Short name T406
Test name
Test status
Simulation time 18918327365 ps
CPU time 50.01 seconds
Started Jun 30 05:51:31 PM PDT 24
Finished Jun 30 05:52:22 PM PDT 24
Peak memory 217460 kb
Host smart-1c0ee840-e33e-498b-b1fc-df69ec14df77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066250723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2066250723 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.1106374497
Short name T616
Test name
Test status
Simulation time 8648554331 ps
CPU time 133.32 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 05:53:40 PM PDT 24
Peak memory 236864 kb
Host smart-a7bfd956-f890-4449-ab83-62cd67378923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106374497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.1106374497 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.3766873386
Short name T166
Test name
Test status
Simulation time 877928221 ps
CPU time 68.28 seconds
Started Jun 30 05:51:25 PM PDT 24
Finished Jun 30 05:52:34 PM PDT 24
Peak memory 240684 kb
Host smart-d89c48dd-b758-497f-ab80-67c20f7753b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766873386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3766873386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.1203506085
Short name T557
Test name
Test status
Simulation time 1592916144 ps
CPU time 4.55 seconds
Started Jun 30 05:51:25 PM PDT 24
Finished Jun 30 05:51:30 PM PDT 24
Peak memory 207868 kb
Host smart-21d8b817-35b8-4c5d-a4ee-a00868610eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203506085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.1203506085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2250223972
Short name T363
Test name
Test status
Simulation time 26402765 ps
CPU time 1.15 seconds
Started Jun 30 05:51:32 PM PDT 24
Finished Jun 30 05:51:34 PM PDT 24
Peak memory 216152 kb
Host smart-5e236625-ce88-4b92-a111-e581b59a1341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250223972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2250223972 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.4247821490
Short name T1063
Test name
Test status
Simulation time 53799348431 ps
CPU time 1506.33 seconds
Started Jun 30 05:51:25 PM PDT 24
Finished Jun 30 06:16:32 PM PDT 24
Peak memory 367116 kb
Host smart-308db164-18a0-4238-9652-fdddb0146455
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247821490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.4247821490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.3870111689
Short name T300
Test name
Test status
Simulation time 1640143164 ps
CPU time 26.67 seconds
Started Jun 30 05:51:27 PM PDT 24
Finished Jun 30 05:51:54 PM PDT 24
Peak memory 224544 kb
Host smart-bf7574cc-c928-41f7-beeb-cfca1da77d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870111689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3870111689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1371432706
Short name T12
Test name
Test status
Simulation time 12490578979 ps
CPU time 32.9 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:52:06 PM PDT 24
Peak memory 248164 kb
Host smart-7c23c4eb-85f7-48f2-abee-ac1b5d33ba15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371432706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1371432706 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.2372295728
Short name T590
Test name
Test status
Simulation time 263485825 ps
CPU time 6.06 seconds
Started Jun 30 05:51:25 PM PDT 24
Finished Jun 30 05:51:32 PM PDT 24
Peak memory 224520 kb
Host smart-1153ac17-c583-4a41-af82-7f5cb4ccc770
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372295728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2372295728 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.1908940901
Short name T494
Test name
Test status
Simulation time 3236700597 ps
CPU time 44.62 seconds
Started Jun 30 05:51:24 PM PDT 24
Finished Jun 30 05:52:09 PM PDT 24
Peak memory 219828 kb
Host smart-879429c7-ea6a-44c7-a300-5924eff4db24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908940901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1908940901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.2534317105
Short name T1000
Test name
Test status
Simulation time 223956167553 ps
CPU time 1610.67 seconds
Started Jun 30 05:51:34 PM PDT 24
Finished Jun 30 06:18:26 PM PDT 24
Peak memory 414220 kb
Host smart-4bbdf059-47a8-4777-b221-3ab31c3a9ee2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2534317105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2534317105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.3750885635
Short name T1066
Test name
Test status
Simulation time 67581211 ps
CPU time 3.89 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 05:51:30 PM PDT 24
Peak memory 216104 kb
Host smart-7ebb6e04-7f8c-40b5-bcee-9db6a157a79e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750885635 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.3750885635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2486302154
Short name T310
Test name
Test status
Simulation time 657071834 ps
CPU time 4.56 seconds
Started Jun 30 05:51:24 PM PDT 24
Finished Jun 30 05:51:29 PM PDT 24
Peak memory 216224 kb
Host smart-6b741e0b-60b8-49cb-ac04-ddd24eb2289b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486302154 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2486302154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.217584907
Short name T688
Test name
Test status
Simulation time 84342976220 ps
CPU time 1566.97 seconds
Started Jun 30 05:51:25 PM PDT 24
Finished Jun 30 06:17:33 PM PDT 24
Peak memory 379024 kb
Host smart-5f69d811-a8d8-4c5a-9798-57df57329ba8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=217584907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.217584907 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.1596777572
Short name T382
Test name
Test status
Simulation time 384500641510 ps
CPU time 1953.91 seconds
Started Jun 30 05:51:25 PM PDT 24
Finished Jun 30 06:24:00 PM PDT 24
Peak memory 377836 kb
Host smart-4abccbb3-83a3-428b-8232-8ae1561d4739
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1596777572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1596777572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2463958318
Short name T1051
Test name
Test status
Simulation time 14308443176 ps
CPU time 1113.68 seconds
Started Jun 30 05:51:25 PM PDT 24
Finished Jun 30 06:09:59 PM PDT 24
Peak memory 336976 kb
Host smart-8e3cc3b9-bde2-46f0-b96d-dbb52456d010
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2463958318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2463958318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.322845319
Short name T268
Test name
Test status
Simulation time 48418099023 ps
CPU time 982.98 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 06:07:50 PM PDT 24
Peak memory 293636 kb
Host smart-55c016d7-93b0-432c-866e-66aceea5c06d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=322845319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.322845319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.4216968853
Short name T425
Test name
Test status
Simulation time 779539645192 ps
CPU time 4632.69 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 07:08:40 PM PDT 24
Peak memory 650836 kb
Host smart-a4be97e1-63a1-42d0-8166-520fdbe0214f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4216968853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.4216968853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.2546901141
Short name T595
Test name
Test status
Simulation time 86430948658 ps
CPU time 3523.19 seconds
Started Jun 30 05:51:26 PM PDT 24
Finished Jun 30 06:50:11 PM PDT 24
Peak memory 559380 kb
Host smart-836aacd6-c1d2-4cb8-83c4-0da7ca769663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2546901141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2546901141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.1759413217
Short name T662
Test name
Test status
Simulation time 52128532 ps
CPU time 0.89 seconds
Started Jun 30 05:51:43 PM PDT 24
Finished Jun 30 05:51:45 PM PDT 24
Peak memory 205620 kb
Host smart-6d96a382-03f8-4573-8a78-b1ca311bc8ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759413217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1759413217 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.889611950
Short name T163
Test name
Test status
Simulation time 4560915867 ps
CPU time 97.3 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 05:53:13 PM PDT 24
Peak memory 231472 kb
Host smart-64c7d13c-77a7-4bfb-b2a2-c56d03ec75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889611950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.889611950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.969278524
Short name T706
Test name
Test status
Simulation time 17603703620 ps
CPU time 128.69 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:53:43 PM PDT 24
Peak memory 233740 kb
Host smart-19cf8bca-20f2-402c-ba05-58a71e04819e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969278524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.969278524 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.3423905669
Short name T205
Test name
Test status
Simulation time 5032551037 ps
CPU time 83.97 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:52:57 PM PDT 24
Peak memory 220920 kb
Host smart-bc8798af-f270-4b25-b0e4-5a4cf8848a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423905669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3423905669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3255557038
Short name T784
Test name
Test status
Simulation time 1018265223 ps
CPU time 19.93 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:51:55 PM PDT 24
Peak memory 224232 kb
Host smart-370d5f70-f757-4dc6-baf1-a569ca904537
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3255557038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3255557038 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.3597375455
Short name T512
Test name
Test status
Simulation time 1329902450 ps
CPU time 36.07 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:52:10 PM PDT 24
Peak memory 221156 kb
Host smart-c0759712-758e-4007-8838-8f1dd0cbe205
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3597375455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3597375455 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.872717320
Short name T41
Test name
Test status
Simulation time 3451601413 ps
CPU time 40.85 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:52:15 PM PDT 24
Peak memory 217216 kb
Host smart-b1ae1cb1-29e2-4032-9249-751f6fd7ee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872717320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.872717320 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1075085660
Short name T306
Test name
Test status
Simulation time 22360239456 ps
CPU time 134.12 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:53:48 PM PDT 24
Peak memory 232756 kb
Host smart-46d6a6dc-841f-4b55-a80b-d077f0d00e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075085660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1075085660 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.68113224
Short name T1022
Test name
Test status
Simulation time 10528626895 ps
CPU time 214.78 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 05:55:10 PM PDT 24
Peak memory 256576 kb
Host smart-fd07a947-4317-4d1b-904d-f82cd0fbacc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68113224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.68113224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1025897981
Short name T824
Test name
Test status
Simulation time 7996057936 ps
CPU time 9.04 seconds
Started Jun 30 05:51:34 PM PDT 24
Finished Jun 30 05:51:44 PM PDT 24
Peak memory 207956 kb
Host smart-400b67d6-b2f8-4edd-b373-f95ada358e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025897981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1025897981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.3743472179
Short name T91
Test name
Test status
Simulation time 156207362 ps
CPU time 1.3 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:51:36 PM PDT 24
Peak memory 216044 kb
Host smart-561371eb-64b8-4d2c-b759-06abe869eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743472179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3743472179 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.3749742037
Short name T1047
Test name
Test status
Simulation time 10982630927 ps
CPU time 754.79 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 06:04:10 PM PDT 24
Peak memory 303992 kb
Host smart-624e8152-8438-4390-97ec-b90e357719e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749742037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.3749742037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.1764472183
Short name T1055
Test name
Test status
Simulation time 3879217380 ps
CPU time 44.67 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 05:52:21 PM PDT 24
Peak memory 224620 kb
Host smart-874bfb19-8214-47f6-82c5-01c69cf861b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764472183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1764472183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.1218295338
Short name T61
Test name
Test status
Simulation time 5677338371 ps
CPU time 37.45 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 05:52:11 PM PDT 24
Peak memory 255488 kb
Host smart-f861e09d-f19b-44cf-b7d4-065c5b98e101
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218295338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1218295338 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.3449849600
Short name T189
Test name
Test status
Simulation time 10239168718 ps
CPU time 290.84 seconds
Started Jun 30 05:51:34 PM PDT 24
Finished Jun 30 05:56:26 PM PDT 24
Peak memory 243412 kb
Host smart-f612cae6-efc2-4a57-aed6-62293501d225
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449849600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.3449849600 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.404966679
Short name T908
Test name
Test status
Simulation time 1643689860 ps
CPU time 28.15 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 05:52:04 PM PDT 24
Peak memory 219572 kb
Host smart-a684c4e7-5ea4-486f-a4ea-db959204daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404966679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.404966679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.2858295396
Short name T874
Test name
Test status
Simulation time 280723254811 ps
CPU time 826.18 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 06:05:22 PM PDT 24
Peak memory 319280 kb
Host smart-aab4037e-56b7-49f1-b315-0db3b12c5234
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2858295396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2858295396 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3687532818
Short name T733
Test name
Test status
Simulation time 173830866 ps
CPU time 4.38 seconds
Started Jun 30 05:51:32 PM PDT 24
Finished Jun 30 05:51:37 PM PDT 24
Peak memory 216124 kb
Host smart-179f745b-716b-456d-bc8c-1e89fe039f37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687532818 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3687532818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1508217734
Short name T804
Test name
Test status
Simulation time 1359852605 ps
CPU time 4.36 seconds
Started Jun 30 05:51:34 PM PDT 24
Finished Jun 30 05:51:39 PM PDT 24
Peak memory 216132 kb
Host smart-317687f0-e22f-4913-8a7d-8088642daea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508217734 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1508217734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.3253828489
Short name T980
Test name
Test status
Simulation time 67025944041 ps
CPU time 1784.28 seconds
Started Jun 30 05:51:32 PM PDT 24
Finished Jun 30 06:21:17 PM PDT 24
Peak memory 388536 kb
Host smart-1aedc7f7-95e6-429c-810c-b3c8a31b4ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3253828489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3253828489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.2346419734
Short name T774
Test name
Test status
Simulation time 251276886567 ps
CPU time 1586.22 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 06:18:02 PM PDT 24
Peak memory 369456 kb
Host smart-5e3945a0-ee5f-47a4-b1cd-881b89754955
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2346419734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2346419734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.2187064180
Short name T1016
Test name
Test status
Simulation time 18544055301 ps
CPU time 1059.59 seconds
Started Jun 30 05:51:35 PM PDT 24
Finished Jun 30 06:09:15 PM PDT 24
Peak memory 329876 kb
Host smart-175d6aaa-22e5-4bb3-b05c-61e1c48e9594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2187064180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2187064180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.3285052898
Short name T232
Test name
Test status
Simulation time 19247423659 ps
CPU time 808.86 seconds
Started Jun 30 05:51:34 PM PDT 24
Finished Jun 30 06:05:04 PM PDT 24
Peak memory 298084 kb
Host smart-03bccaee-62b8-403d-83d3-f284bf4f5477
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3285052898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3285052898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1278034765
Short name T66
Test name
Test status
Simulation time 1158025523048 ps
CPU time 5137.93 seconds
Started Jun 30 05:51:34 PM PDT 24
Finished Jun 30 07:17:14 PM PDT 24
Peak memory 639644 kb
Host smart-08e283fd-bdc0-41e8-82e8-111a4def347f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1278034765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1278034765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.2193481157
Short name T943
Test name
Test status
Simulation time 144768939282 ps
CPU time 3874.23 seconds
Started Jun 30 05:51:33 PM PDT 24
Finished Jun 30 06:56:09 PM PDT 24
Peak memory 558360 kb
Host smart-1b08d1bd-a6cc-4540-a00e-1978f9f451cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2193481157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2193481157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3735470860
Short name T866
Test name
Test status
Simulation time 22442559 ps
CPU time 0.88 seconds
Started Jun 30 05:52:48 PM PDT 24
Finished Jun 30 05:52:49 PM PDT 24
Peak memory 205620 kb
Host smart-3dbc3a29-8c2b-48ee-a631-0b3999de7431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735470860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3735470860 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.1756367924
Short name T552
Test name
Test status
Simulation time 10451459044 ps
CPU time 216.89 seconds
Started Jun 30 05:52:48 PM PDT 24
Finished Jun 30 05:56:26 PM PDT 24
Peak memory 242300 kb
Host smart-fa6b651a-dd09-4f60-89b4-8b3d6d90e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756367924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1756367924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.729165389
Short name T63
Test name
Test status
Simulation time 15584697974 ps
CPU time 343.29 seconds
Started Jun 30 05:52:41 PM PDT 24
Finished Jun 30 05:58:25 PM PDT 24
Peak memory 229800 kb
Host smart-b09913e2-0017-4f1a-8aa9-85c576c43222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729165389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.729165389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.4258344136
Short name T749
Test name
Test status
Simulation time 2265853845 ps
CPU time 5.48 seconds
Started Jun 30 05:52:49 PM PDT 24
Finished Jun 30 05:52:55 PM PDT 24
Peak memory 220804 kb
Host smart-ad32cc44-9d88-4e21-9e3a-affc55df8587
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4258344136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.4258344136 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.1743938907
Short name T533
Test name
Test status
Simulation time 2074402359 ps
CPU time 9.54 seconds
Started Jun 30 05:52:51 PM PDT 24
Finished Jun 30 05:53:01 PM PDT 24
Peak memory 224196 kb
Host smart-d09e2d30-a473-458c-b390-32432ba33b07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1743938907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1743938907 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2718830393
Short name T25
Test name
Test status
Simulation time 7695482067 ps
CPU time 35.05 seconds
Started Jun 30 05:52:48 PM PDT 24
Finished Jun 30 05:53:23 PM PDT 24
Peak memory 224380 kb
Host smart-a23e0368-f992-4579-b22e-15763559c137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718830393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2718830393 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_key_error.576918906
Short name T92
Test name
Test status
Simulation time 2131096145 ps
CPU time 2.07 seconds
Started Jun 30 05:52:48 PM PDT 24
Finished Jun 30 05:52:51 PM PDT 24
Peak memory 207888 kb
Host smart-8e663dd2-2647-49fd-a8d6-82d11e6c031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576918906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.576918906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.22695737
Short name T9
Test name
Test status
Simulation time 335388049 ps
CPU time 1.14 seconds
Started Jun 30 05:52:49 PM PDT 24
Finished Jun 30 05:52:50 PM PDT 24
Peak memory 216076 kb
Host smart-b2f2ed5c-d3e5-45a6-b749-38de11349e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22695737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.22695737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.1289189967
Short name T767
Test name
Test status
Simulation time 2469672960 ps
CPU time 48.71 seconds
Started Jun 30 05:52:44 PM PDT 24
Finished Jun 30 05:53:33 PM PDT 24
Peak memory 224376 kb
Host smart-af220fee-fde4-4aa3-a77f-5b28ce7deae9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289189967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.1289189967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2156637286
Short name T773
Test name
Test status
Simulation time 4685971708 ps
CPU time 26.43 seconds
Started Jun 30 05:52:42 PM PDT 24
Finished Jun 30 05:53:09 PM PDT 24
Peak memory 224440 kb
Host smart-a415ee50-c9f0-4f4a-85b8-dd33af66b305
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156637286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2156637286 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.3636809055
Short name T481
Test name
Test status
Simulation time 12773333507 ps
CPU time 52.24 seconds
Started Jun 30 05:52:42 PM PDT 24
Finished Jun 30 05:53:35 PM PDT 24
Peak memory 218184 kb
Host smart-7b0b53de-454d-4962-bddc-4a7aef3cb573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636809055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3636809055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2477857957
Short name T522
Test name
Test status
Simulation time 17074880531 ps
CPU time 324.19 seconds
Started Jun 30 05:52:50 PM PDT 24
Finished Jun 30 05:58:14 PM PDT 24
Peak memory 257360 kb
Host smart-fdd9e93c-bcfc-43d4-aad1-4e2829ef2bb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2477857957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2477857957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.1064042125
Short name T1013
Test name
Test status
Simulation time 642903118 ps
CPU time 4.19 seconds
Started Jun 30 05:52:49 PM PDT 24
Finished Jun 30 05:52:54 PM PDT 24
Peak memory 216184 kb
Host smart-b1162f38-a73e-48c2-a4cb-245cd31abff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064042125 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.1064042125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.2789255041
Short name T704
Test name
Test status
Simulation time 138384567 ps
CPU time 4.16 seconds
Started Jun 30 05:52:48 PM PDT 24
Finished Jun 30 05:52:53 PM PDT 24
Peak memory 216140 kb
Host smart-1dd549d4-43a9-44be-88f8-3d8d668b1087
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789255041 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.2789255041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3223283811
Short name T661
Test name
Test status
Simulation time 260870590942 ps
CPU time 1807.89 seconds
Started Jun 30 05:52:43 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 394308 kb
Host smart-da768eeb-0ee7-4728-9b97-e4b05f0d2dbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3223283811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3223283811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.2101128925
Short name T281
Test name
Test status
Simulation time 37760424151 ps
CPU time 1473.15 seconds
Started Jun 30 05:52:43 PM PDT 24
Finished Jun 30 06:17:17 PM PDT 24
Peak memory 389752 kb
Host smart-135574cb-b675-4595-8759-2be1755abdc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2101128925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2101128925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.2932103818
Short name T334
Test name
Test status
Simulation time 140333280207 ps
CPU time 1415.96 seconds
Started Jun 30 05:52:42 PM PDT 24
Finished Jun 30 06:16:19 PM PDT 24
Peak memory 335200 kb
Host smart-acb7d128-c863-446b-8b94-db762dc7ce2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2932103818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2932103818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.3311305288
Short name T230
Test name
Test status
Simulation time 97637458889 ps
CPU time 927.63 seconds
Started Jun 30 05:52:41 PM PDT 24
Finished Jun 30 06:08:10 PM PDT 24
Peak memory 290636 kb
Host smart-d2a940b8-d589-49d6-bf13-4f7d33d71e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3311305288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.3311305288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.3082504388
Short name T293
Test name
Test status
Simulation time 384971290815 ps
CPU time 3950.8 seconds
Started Jun 30 05:52:50 PM PDT 24
Finished Jun 30 06:58:42 PM PDT 24
Peak memory 635760 kb
Host smart-1f798778-7740-4f1c-b57d-afed3e5928a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3082504388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3082504388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.1980672941
Short name T429
Test name
Test status
Simulation time 151908231393 ps
CPU time 3902.4 seconds
Started Jun 30 05:52:48 PM PDT 24
Finished Jun 30 06:57:52 PM PDT 24
Peak memory 556340 kb
Host smart-58bfc5ac-c4f1-46f5-a4e0-f81b55247f11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1980672941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.1980672941 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_app.2661598545
Short name T997
Test name
Test status
Simulation time 18435269376 ps
CPU time 253.23 seconds
Started Jun 30 05:52:56 PM PDT 24
Finished Jun 30 05:57:10 PM PDT 24
Peak memory 244764 kb
Host smart-732671f4-b0c2-43fe-a8e9-6fbaa137f29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661598545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2661598545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.944454881
Short name T144
Test name
Test status
Simulation time 5888739766 ps
CPU time 384.05 seconds
Started Jun 30 05:52:57 PM PDT 24
Finished Jun 30 05:59:22 PM PDT 24
Peak memory 230816 kb
Host smart-acf94109-9389-4739-a2a5-1ba9e342f287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944454881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.944454881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.78297639
Short name T280
Test name
Test status
Simulation time 563670963 ps
CPU time 11.93 seconds
Started Jun 30 05:52:54 PM PDT 24
Finished Jun 30 05:53:07 PM PDT 24
Peak memory 224216 kb
Host smart-17d0ccdd-4f56-4206-8cf8-4d0f8545410a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78297639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.78297639 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1062724029
Short name T660
Test name
Test status
Simulation time 5725668084 ps
CPU time 30.67 seconds
Started Jun 30 05:52:57 PM PDT 24
Finished Jun 30 05:53:28 PM PDT 24
Peak memory 224268 kb
Host smart-afd61df6-040b-40ed-ae71-10e983a57aae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1062724029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1062724029 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.1846247529
Short name T504
Test name
Test status
Simulation time 31737945335 ps
CPU time 154.62 seconds
Started Jun 30 05:52:57 PM PDT 24
Finished Jun 30 05:55:32 PM PDT 24
Peak memory 234908 kb
Host smart-82f678ef-8da8-4245-bf83-0640619488b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846247529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1846247529 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.3250859309
Short name T692
Test name
Test status
Simulation time 28597467910 ps
CPU time 222.88 seconds
Started Jun 30 05:52:56 PM PDT 24
Finished Jun 30 05:56:39 PM PDT 24
Peak memory 249068 kb
Host smart-4053f0ca-2cbd-478a-b137-91f423674ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250859309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3250859309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.151342329
Short name T394
Test name
Test status
Simulation time 810375665 ps
CPU time 4.17 seconds
Started Jun 30 05:52:56 PM PDT 24
Finished Jun 30 05:53:00 PM PDT 24
Peak memory 215992 kb
Host smart-74ed8f82-71a0-4e9f-98a7-2d9e05480b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151342329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.151342329 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.3084453168
Short name T236
Test name
Test status
Simulation time 334667886463 ps
CPU time 2336.81 seconds
Started Jun 30 05:52:49 PM PDT 24
Finished Jun 30 06:31:47 PM PDT 24
Peak memory 450328 kb
Host smart-904ee271-79d3-49b1-86aa-8752c449f183
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084453168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.3084453168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.3114299828
Short name T690
Test name
Test status
Simulation time 20171074276 ps
CPU time 101.84 seconds
Started Jun 30 05:52:48 PM PDT 24
Finished Jun 30 05:54:30 PM PDT 24
Peak memory 227484 kb
Host smart-7092b287-489a-40d7-a0fb-7cd6a393bbbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114299828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3114299828 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.23887967
Short name T124
Test name
Test status
Simulation time 1256190258 ps
CPU time 32.97 seconds
Started Jun 30 05:52:49 PM PDT 24
Finished Jun 30 05:53:22 PM PDT 24
Peak memory 216152 kb
Host smart-ed533419-bca9-4dda-88e6-41a721e43f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23887967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.23887967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.3767315095
Short name T497
Test name
Test status
Simulation time 21984908284 ps
CPU time 200.21 seconds
Started Jun 30 05:52:55 PM PDT 24
Finished Jun 30 05:56:16 PM PDT 24
Peak memory 252620 kb
Host smart-a1b84122-e4c4-4d9b-8020-c61e2dc51b73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3767315095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3767315095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.2333494886
Short name T919
Test name
Test status
Simulation time 262114297 ps
CPU time 4.06 seconds
Started Jun 30 05:52:55 PM PDT 24
Finished Jun 30 05:53:00 PM PDT 24
Peak memory 216104 kb
Host smart-0ec0e1a6-4854-4afc-b34a-04e77c1bc1e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333494886 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.2333494886 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.3544014859
Short name T693
Test name
Test status
Simulation time 69016822 ps
CPU time 4.24 seconds
Started Jun 30 05:52:55 PM PDT 24
Finished Jun 30 05:53:00 PM PDT 24
Peak memory 216216 kb
Host smart-2e06ad37-06eb-41d1-b493-a4ab2f5d34b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544014859 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.3544014859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.2143675195
Short name T689
Test name
Test status
Simulation time 75950184970 ps
CPU time 1606.8 seconds
Started Jun 30 05:52:54 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 396032 kb
Host smart-c3259a23-135a-4a31-a5ce-731e82a57f11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2143675195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.2143675195 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.1200393631
Short name T884
Test name
Test status
Simulation time 81712962818 ps
CPU time 1679.88 seconds
Started Jun 30 05:52:57 PM PDT 24
Finished Jun 30 06:20:57 PM PDT 24
Peak memory 377556 kb
Host smart-f3d44cd3-51a2-46dc-8382-314ed16e86a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1200393631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.1200393631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.2312500793
Short name T327
Test name
Test status
Simulation time 193035703642 ps
CPU time 1261.42 seconds
Started Jun 30 05:52:54 PM PDT 24
Finished Jun 30 06:13:56 PM PDT 24
Peak memory 332436 kb
Host smart-19d8af3f-4935-46ad-8bf6-101db87d40c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2312500793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2312500793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.1504205573
Short name T339
Test name
Test status
Simulation time 9561406085 ps
CPU time 769.72 seconds
Started Jun 30 05:52:57 PM PDT 24
Finished Jun 30 06:05:47 PM PDT 24
Peak memory 296528 kb
Host smart-43741792-b487-45bc-b957-776e361e9833
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1504205573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.1504205573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.2167783586
Short name T505
Test name
Test status
Simulation time 911623703083 ps
CPU time 5555.04 seconds
Started Jun 30 05:52:55 PM PDT 24
Finished Jun 30 07:25:31 PM PDT 24
Peak memory 644236 kb
Host smart-ac91699f-95b5-4df4-b2ea-0decd631b5c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2167783586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.2167783586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.32887272
Short name T809
Test name
Test status
Simulation time 153759961180 ps
CPU time 4032.86 seconds
Started Jun 30 05:52:55 PM PDT 24
Finished Jun 30 07:00:09 PM PDT 24
Peak memory 565540 kb
Host smart-f7c3bd96-59df-4fdf-a911-3756b88f29f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=32887272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.32887272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.3297083915
Short name T900
Test name
Test status
Simulation time 95195561 ps
CPU time 0.93 seconds
Started Jun 30 05:53:09 PM PDT 24
Finished Jun 30 05:53:10 PM PDT 24
Peak memory 205648 kb
Host smart-7025889c-2090-48be-8b5c-42e0a9600ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297083915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3297083915 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.1012267663
Short name T634
Test name
Test status
Simulation time 2095060789 ps
CPU time 44 seconds
Started Jun 30 05:53:01 PM PDT 24
Finished Jun 30 05:53:46 PM PDT 24
Peak memory 221280 kb
Host smart-afa39977-ed7d-477c-9a1d-ce254e3d32f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012267663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1012267663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.76417407
Short name T366
Test name
Test status
Simulation time 9386204937 ps
CPU time 225.28 seconds
Started Jun 30 05:53:00 PM PDT 24
Finished Jun 30 05:56:45 PM PDT 24
Peak memory 224604 kb
Host smart-748fa6ac-fdd2-47e8-bc3a-309e5bbe4879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76417407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.76417407 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.662412607
Short name T578
Test name
Test status
Simulation time 453506487 ps
CPU time 31.8 seconds
Started Jun 30 05:53:09 PM PDT 24
Finished Jun 30 05:53:41 PM PDT 24
Peak memory 224236 kb
Host smart-767ed26e-0fbb-4b25-96e5-13bd5011f1c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=662412607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.662412607 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.1838585954
Short name T486
Test name
Test status
Simulation time 429661884 ps
CPU time 2.76 seconds
Started Jun 30 05:53:08 PM PDT 24
Finished Jun 30 05:53:11 PM PDT 24
Peak memory 217660 kb
Host smart-82ad2730-05ba-4ee7-8dc4-6dd4e99e6b60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1838585954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1838585954 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3138501997
Short name T819
Test name
Test status
Simulation time 26471587248 ps
CPU time 115.15 seconds
Started Jun 30 05:53:02 PM PDT 24
Finished Jun 30 05:54:57 PM PDT 24
Peak memory 229020 kb
Host smart-fd6619c6-1746-4457-ba30-705189f0e4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138501997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3138501997 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_key_error.2601843549
Short name T324
Test name
Test status
Simulation time 977758917 ps
CPU time 5.53 seconds
Started Jun 30 05:53:10 PM PDT 24
Finished Jun 30 05:53:15 PM PDT 24
Peak memory 216048 kb
Host smart-f649e621-2ea0-4311-8af3-ad56a78aa68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601843549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2601843549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.1455396028
Short name T680
Test name
Test status
Simulation time 1985988990 ps
CPU time 10.86 seconds
Started Jun 30 05:53:08 PM PDT 24
Finished Jun 30 05:53:19 PM PDT 24
Peak memory 224384 kb
Host smart-acee5c33-83a6-4236-8a22-a3335cd56945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455396028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1455396028 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.1493062618
Short name T729
Test name
Test status
Simulation time 89184218217 ps
CPU time 1799.12 seconds
Started Jun 30 05:52:54 PM PDT 24
Finished Jun 30 06:22:53 PM PDT 24
Peak memory 428488 kb
Host smart-4bb3a0a7-86bc-47cd-b916-706fd706bd60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493062618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.1493062618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.476934396
Short name T956
Test name
Test status
Simulation time 5908889760 ps
CPU time 240.72 seconds
Started Jun 30 05:52:54 PM PDT 24
Finished Jun 30 05:56:55 PM PDT 24
Peak memory 241028 kb
Host smart-bb4839b9-89ca-441f-8419-c711b56c54bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476934396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.476934396 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.1276079178
Short name T638
Test name
Test status
Simulation time 878355591 ps
CPU time 21.77 seconds
Started Jun 30 05:52:55 PM PDT 24
Finished Jun 30 05:53:17 PM PDT 24
Peak memory 216216 kb
Host smart-baa732c1-37c4-40d6-bb37-d036b27c342c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276079178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1276079178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1880801445
Short name T1012
Test name
Test status
Simulation time 147119677727 ps
CPU time 940.12 seconds
Started Jun 30 05:53:09 PM PDT 24
Finished Jun 30 06:08:49 PM PDT 24
Peak memory 339848 kb
Host smart-027af152-3a20-4ca1-b959-99492961ece2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1880801445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1880801445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.4132992346
Short name T536
Test name
Test status
Simulation time 99258389 ps
CPU time 4.03 seconds
Started Jun 30 05:53:01 PM PDT 24
Finished Jun 30 05:53:05 PM PDT 24
Peak memory 216104 kb
Host smart-3accf56b-f469-4934-9d69-210c819af09d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132992346 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.4132992346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1251336181
Short name T437
Test name
Test status
Simulation time 2375578954 ps
CPU time 5.52 seconds
Started Jun 30 05:53:03 PM PDT 24
Finished Jun 30 05:53:08 PM PDT 24
Peak memory 216192 kb
Host smart-d1fe107a-4dfc-4a4f-9825-10be95dd7b29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251336181 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1251336181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.639770728
Short name T262
Test name
Test status
Simulation time 68879116933 ps
CPU time 1871.78 seconds
Started Jun 30 05:53:02 PM PDT 24
Finished Jun 30 06:24:15 PM PDT 24
Peak memory 399072 kb
Host smart-c0ad06fa-ef46-4794-abb5-00fa34e4d156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=639770728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.639770728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3052434922
Short name T445
Test name
Test status
Simulation time 75792028172 ps
CPU time 1485.08 seconds
Started Jun 30 05:53:02 PM PDT 24
Finished Jun 30 06:17:47 PM PDT 24
Peak memory 390660 kb
Host smart-a19de2f1-f832-4f08-86ae-cb9e8415599e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3052434922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3052434922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.4218887570
Short name T87
Test name
Test status
Simulation time 92853557680 ps
CPU time 1295.03 seconds
Started Jun 30 05:53:03 PM PDT 24
Finished Jun 30 06:14:38 PM PDT 24
Peak memory 332680 kb
Host smart-fc5088b1-9470-4b30-88c2-99b74107cf0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4218887570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.4218887570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.848200162
Short name T95
Test name
Test status
Simulation time 50984400296 ps
CPU time 1012.1 seconds
Started Jun 30 05:53:01 PM PDT 24
Finished Jun 30 06:09:53 PM PDT 24
Peak memory 297972 kb
Host smart-668305ad-43d8-4e2c-92d4-ac81294aad27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=848200162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.848200162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.1248520352
Short name T214
Test name
Test status
Simulation time 1141836049166 ps
CPU time 5043.23 seconds
Started Jun 30 05:53:01 PM PDT 24
Finished Jun 30 07:17:06 PM PDT 24
Peak memory 646060 kb
Host smart-79a0298e-ccfd-479e-8536-c9b7b6f9bcd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1248520352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.1248520352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_alert_test.810224661
Short name T898
Test name
Test status
Simulation time 41506529 ps
CPU time 0.77 seconds
Started Jun 30 05:53:14 PM PDT 24
Finished Jun 30 05:53:15 PM PDT 24
Peak memory 205640 kb
Host smart-2dbb9baa-8df2-4336-a924-2bce6d32ff26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810224661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.810224661 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.3979464967
Short name T771
Test name
Test status
Simulation time 77899577733 ps
CPU time 299.86 seconds
Started Jun 30 05:53:15 PM PDT 24
Finished Jun 30 05:58:15 PM PDT 24
Peak memory 246624 kb
Host smart-18f82a8a-66b9-405d-bffb-d54e19fe0d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979464967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3979464967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.1864056948
Short name T844
Test name
Test status
Simulation time 56862288501 ps
CPU time 587.69 seconds
Started Jun 30 05:53:08 PM PDT 24
Finished Jun 30 06:02:57 PM PDT 24
Peak memory 231108 kb
Host smart-2ebd6c38-2d4b-42fb-82d1-400394a57633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864056948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1864056948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2057347141
Short name T1028
Test name
Test status
Simulation time 514554348 ps
CPU time 13.31 seconds
Started Jun 30 05:53:14 PM PDT 24
Finished Jun 30 05:53:28 PM PDT 24
Peak memory 220300 kb
Host smart-9b638716-f4dd-4f9e-b944-e2b69b85f752
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2057347141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2057347141 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.4028616088
Short name T877
Test name
Test status
Simulation time 3185285341 ps
CPU time 35.91 seconds
Started Jun 30 05:53:15 PM PDT 24
Finished Jun 30 05:53:51 PM PDT 24
Peak memory 224284 kb
Host smart-13afaf48-894e-4162-8ca5-da918b78ba99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4028616088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.4028616088 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.2409371514
Short name T317
Test name
Test status
Simulation time 51836326142 ps
CPU time 217.37 seconds
Started Jun 30 05:53:15 PM PDT 24
Finished Jun 30 05:56:53 PM PDT 24
Peak memory 238972 kb
Host smart-95e35efa-d308-4c31-9412-b8bb7b3436f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409371514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2409371514 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2604287709
Short name T796
Test name
Test status
Simulation time 105936360228 ps
CPU time 451.21 seconds
Started Jun 30 05:53:13 PM PDT 24
Finished Jun 30 06:00:45 PM PDT 24
Peak memory 255592 kb
Host smart-1cb9466e-7c16-41a7-bc94-026886691da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604287709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2604287709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.2719144374
Short name T1038
Test name
Test status
Simulation time 820536803 ps
CPU time 5.15 seconds
Started Jun 30 05:53:14 PM PDT 24
Finished Jun 30 05:53:20 PM PDT 24
Peak memory 216088 kb
Host smart-e134a9aa-e266-4181-b8e4-65c85002b0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719144374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2719144374 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2136213825
Short name T807
Test name
Test status
Simulation time 87710858 ps
CPU time 1.33 seconds
Started Jun 30 05:53:15 PM PDT 24
Finished Jun 30 05:53:16 PM PDT 24
Peak memory 216128 kb
Host smart-cd119f3e-0348-49cc-866c-3c5b2c2a14e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136213825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2136213825 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3123508509
Short name T954
Test name
Test status
Simulation time 9310371491 ps
CPU time 758.58 seconds
Started Jun 30 05:53:09 PM PDT 24
Finished Jun 30 06:05:48 PM PDT 24
Peak memory 303532 kb
Host smart-199d3f65-1a5f-4a82-a2fc-d0d2ae913a80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123508509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3123508509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.1705763470
Short name T379
Test name
Test status
Simulation time 13911597451 ps
CPU time 94.36 seconds
Started Jun 30 05:53:09 PM PDT 24
Finished Jun 30 05:54:44 PM PDT 24
Peak memory 227324 kb
Host smart-b130317b-1d8f-4f3c-9b07-ff8489a103bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705763470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1705763470 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.518451399
Short name T455
Test name
Test status
Simulation time 1578217396 ps
CPU time 20.11 seconds
Started Jun 30 05:53:09 PM PDT 24
Finished Jun 30 05:53:30 PM PDT 24
Peak memory 216104 kb
Host smart-08ad4da1-f4fc-4402-b662-3d5fb3b5497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518451399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.518451399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.4234936549
Short name T1073
Test name
Test status
Simulation time 87168361188 ps
CPU time 413.78 seconds
Started Jun 30 05:53:14 PM PDT 24
Finished Jun 30 06:00:08 PM PDT 24
Peak memory 249056 kb
Host smart-154c06d5-4fd5-490a-b830-79aaca21c804
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4234936549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.4234936549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3078354362
Short name T94
Test name
Test status
Simulation time 817592235 ps
CPU time 4.4 seconds
Started Jun 30 05:53:13 PM PDT 24
Finished Jun 30 05:53:18 PM PDT 24
Peak memory 216088 kb
Host smart-0821b081-487a-4c98-84f9-bb7664f1be68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078354362 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3078354362 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.375098357
Short name T995
Test name
Test status
Simulation time 220075587 ps
CPU time 3.87 seconds
Started Jun 30 05:53:15 PM PDT 24
Finished Jun 30 05:53:19 PM PDT 24
Peak memory 216232 kb
Host smart-b2b7f52d-a4fd-433e-83f6-6f6244adcffe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375098357 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.kmac_test_vectors_kmac_xof.375098357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.3275998944
Short name T610
Test name
Test status
Simulation time 19842760295 ps
CPU time 1636.54 seconds
Started Jun 30 05:53:10 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 396892 kb
Host smart-c24066fe-c827-4216-9b26-6eb0fbed3bca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3275998944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.3275998944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1283703437
Short name T868
Test name
Test status
Simulation time 180699619502 ps
CPU time 1836.15 seconds
Started Jun 30 05:53:07 PM PDT 24
Finished Jun 30 06:23:44 PM PDT 24
Peak memory 370236 kb
Host smart-7f64dd46-2c15-4169-8649-4251ba9d3d61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1283703437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1283703437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3188657911
Short name T252
Test name
Test status
Simulation time 28311097449 ps
CPU time 1111.8 seconds
Started Jun 30 05:53:08 PM PDT 24
Finished Jun 30 06:11:40 PM PDT 24
Peak memory 333780 kb
Host smart-b667a345-4c71-4ba3-a7dc-5469ad0c7297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3188657911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3188657911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.1572424761
Short name T287
Test name
Test status
Simulation time 38882862828 ps
CPU time 767.62 seconds
Started Jun 30 05:53:10 PM PDT 24
Finished Jun 30 06:05:58 PM PDT 24
Peak memory 299956 kb
Host smart-9f00bbb5-de09-4bdf-a8ac-f1f0a7ced8d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1572424761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.1572424761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.1024796862
Short name T846
Test name
Test status
Simulation time 102557408553 ps
CPU time 4099.65 seconds
Started Jun 30 05:53:08 PM PDT 24
Finished Jun 30 07:01:28 PM PDT 24
Peak memory 659316 kb
Host smart-1c113751-3370-460f-b049-69a2e8ee973c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1024796862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.1024796862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.627574842
Short name T493
Test name
Test status
Simulation time 266645518968 ps
CPU time 4107.54 seconds
Started Jun 30 05:53:14 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 558764 kb
Host smart-061d69cc-26a4-4862-a2b1-3f72f0e8ed2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=627574842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.627574842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1199667665
Short name T713
Test name
Test status
Simulation time 50649793 ps
CPU time 0.8 seconds
Started Jun 30 05:53:25 PM PDT 24
Finished Jun 30 05:53:27 PM PDT 24
Peak memory 205864 kb
Host smart-8a734cd7-7400-4160-b5a0-342081564288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199667665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1199667665 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.1384337083
Short name T266
Test name
Test status
Simulation time 560980136 ps
CPU time 19.62 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 05:53:39 PM PDT 24
Peak memory 224300 kb
Host smart-f0fbe794-e669-4cb8-8d0f-bc52898491ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384337083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1384337083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.3334323259
Short name T672
Test name
Test status
Simulation time 128861949875 ps
CPU time 771.33 seconds
Started Jun 30 05:53:13 PM PDT 24
Finished Jun 30 06:06:05 PM PDT 24
Peak memory 234216 kb
Host smart-1e208842-a02a-4d7c-a5d5-82cc19128fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334323259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3334323259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.2317050458
Short name T197
Test name
Test status
Simulation time 4219393034 ps
CPU time 20.3 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 05:53:40 PM PDT 24
Peak memory 224280 kb
Host smart-3371406e-3a17-4065-8eb3-1b24b6316d6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2317050458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2317050458 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.291464177
Short name T560
Test name
Test status
Simulation time 159780091 ps
CPU time 11.23 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 05:53:30 PM PDT 24
Peak memory 220608 kb
Host smart-d5ee5d79-f08c-4d0c-861e-373670cde835
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=291464177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.291464177 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.1468021288
Short name T532
Test name
Test status
Simulation time 3278631773 ps
CPU time 71.32 seconds
Started Jun 30 05:53:20 PM PDT 24
Finished Jun 30 05:54:32 PM PDT 24
Peak memory 226276 kb
Host smart-c7985afb-975e-432d-94c8-77407e97dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468021288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1468021288 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.225047468
Short name T644
Test name
Test status
Simulation time 6314923829 ps
CPU time 247.67 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 05:57:27 PM PDT 24
Peak memory 252256 kb
Host smart-ed962012-5f54-4a12-9112-821f35ee51a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225047468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.225047468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.3439502164
Short name T1064
Test name
Test status
Simulation time 662398926 ps
CPU time 2.3 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 05:53:22 PM PDT 24
Peak memory 207772 kb
Host smart-3ca56473-d783-485b-8ea8-fbc387e57ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439502164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3439502164 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3557362183
Short name T1009
Test name
Test status
Simulation time 29020868290 ps
CPU time 642.7 seconds
Started Jun 30 05:53:14 PM PDT 24
Finished Jun 30 06:03:57 PM PDT 24
Peak memory 287632 kb
Host smart-4c3b0170-db71-4303-a159-5e30922b89cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557362183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3557362183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.446418268
Short name T524
Test name
Test status
Simulation time 5098059397 ps
CPU time 69.44 seconds
Started Jun 30 05:53:13 PM PDT 24
Finished Jun 30 05:54:23 PM PDT 24
Peak memory 224764 kb
Host smart-1d4eedd4-9154-4bbc-8e71-e69d414461c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446418268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.446418268 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.1296555473
Short name T577
Test name
Test status
Simulation time 11719671597 ps
CPU time 57.7 seconds
Started Jun 30 05:53:14 PM PDT 24
Finished Jun 30 05:54:13 PM PDT 24
Peak memory 216200 kb
Host smart-c7be059f-5699-41da-bb56-b1d100b0cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296555473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1296555473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.2371525878
Short name T901
Test name
Test status
Simulation time 135616603855 ps
CPU time 591.17 seconds
Started Jun 30 05:53:26 PM PDT 24
Finished Jun 30 06:03:18 PM PDT 24
Peak memory 279324 kb
Host smart-0c811c9f-5b53-4563-bf39-5af66abc6cfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2371525878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2371525878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.1962299754
Short name T910
Test name
Test status
Simulation time 665554966 ps
CPU time 4.75 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 05:53:24 PM PDT 24
Peak memory 216152 kb
Host smart-617e2e32-bd21-4675-b56a-763114412594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962299754 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.1962299754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.2722943969
Short name T857
Test name
Test status
Simulation time 812421387 ps
CPU time 4.65 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 05:53:24 PM PDT 24
Peak memory 216144 kb
Host smart-10f35e97-72f6-4e24-bfea-7b945fb43718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722943969 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.2722943969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.2317535851
Short name T739
Test name
Test status
Simulation time 67106453111 ps
CPU time 1825.35 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 06:23:45 PM PDT 24
Peak memory 378072 kb
Host smart-30a84a88-5b0c-4e79-9f16-2880688db914
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2317535851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2317535851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.1224034727
Short name T301
Test name
Test status
Simulation time 378610600469 ps
CPU time 1974.11 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 06:26:14 PM PDT 24
Peak memory 372100 kb
Host smart-1f4e549d-b236-45d7-8570-95f0c6ccc517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1224034727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1224034727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1204730616
Short name T416
Test name
Test status
Simulation time 14032972153 ps
CPU time 1075.23 seconds
Started Jun 30 05:53:20 PM PDT 24
Finished Jun 30 06:11:16 PM PDT 24
Peak memory 338040 kb
Host smart-089e5ee4-eef5-4584-82e7-661275572ae2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1204730616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1204730616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.918584222
Short name T517
Test name
Test status
Simulation time 65656692079 ps
CPU time 954.45 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 06:09:14 PM PDT 24
Peak memory 292824 kb
Host smart-657ac5c4-5f4a-4f85-9f4d-1c0624b33453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=918584222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.918584222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.2449310652
Short name T259
Test name
Test status
Simulation time 201634994944 ps
CPU time 3988.38 seconds
Started Jun 30 05:53:19 PM PDT 24
Finished Jun 30 06:59:48 PM PDT 24
Peak memory 641564 kb
Host smart-bfd61367-835e-4e81-b118-349d207f447c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2449310652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.2449310652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.2463913504
Short name T617
Test name
Test status
Simulation time 45501568008 ps
CPU time 3424.69 seconds
Started Jun 30 05:53:21 PM PDT 24
Finished Jun 30 06:50:26 PM PDT 24
Peak memory 570144 kb
Host smart-018d4ca5-4aa3-4f16-91f1-17028f6e89c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2463913504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2463913504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.4081653830
Short name T1024
Test name
Test status
Simulation time 41174866 ps
CPU time 0.79 seconds
Started Jun 30 05:53:31 PM PDT 24
Finished Jun 30 05:53:32 PM PDT 24
Peak memory 205644 kb
Host smart-329bc74e-6dfe-4c17-a2a7-379e9816c097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081653830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.4081653830 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.3473700859
Short name T782
Test name
Test status
Simulation time 125552811574 ps
CPU time 200.78 seconds
Started Jun 30 05:53:25 PM PDT 24
Finished Jun 30 05:56:47 PM PDT 24
Peak memory 238204 kb
Host smart-aa097b7c-9ab1-43fd-ad40-ef0ca48e1bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473700859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3473700859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.929504785
Short name T960
Test name
Test status
Simulation time 33869300531 ps
CPU time 778.53 seconds
Started Jun 30 05:53:25 PM PDT 24
Finished Jun 30 06:06:23 PM PDT 24
Peak memory 232500 kb
Host smart-0c719818-023c-449c-a69a-4c63ab1f5433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929504785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.929504785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1882535598
Short name T930
Test name
Test status
Simulation time 300951878 ps
CPU time 4.14 seconds
Started Jun 30 05:53:33 PM PDT 24
Finished Jun 30 05:53:37 PM PDT 24
Peak memory 216888 kb
Host smart-f36ff6fd-9641-4593-bd4f-dd35e7ae83df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1882535598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1882535598 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.750166250
Short name T549
Test name
Test status
Simulation time 719088892 ps
CPU time 25.69 seconds
Started Jun 30 05:53:35 PM PDT 24
Finished Jun 30 05:54:01 PM PDT 24
Peak memory 219396 kb
Host smart-86b80d4c-d978-441e-8747-5f77a879fe3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=750166250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.750166250 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.2164635384
Short name T921
Test name
Test status
Simulation time 942653929 ps
CPU time 7.58 seconds
Started Jun 30 05:53:25 PM PDT 24
Finished Jun 30 05:53:34 PM PDT 24
Peak memory 221484 kb
Host smart-eef95c6d-7d86-4da0-b632-606fef812357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164635384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2164635384 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.3358931530
Short name T165
Test name
Test status
Simulation time 10557756368 ps
CPU time 185.71 seconds
Started Jun 30 05:53:32 PM PDT 24
Finished Jun 30 05:56:38 PM PDT 24
Peak memory 249872 kb
Host smart-86d539f8-3bb3-4670-8fdd-ef2b08eef2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358931530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3358931530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.2024414746
Short name T548
Test name
Test status
Simulation time 934439638 ps
CPU time 5.19 seconds
Started Jun 30 05:53:30 PM PDT 24
Finished Jun 30 05:53:36 PM PDT 24
Peak memory 207860 kb
Host smart-ef36ca8a-f8e7-4811-a6ee-d38c62ea8b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024414746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2024414746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3637957245
Short name T998
Test name
Test status
Simulation time 182488775 ps
CPU time 1.23 seconds
Started Jun 30 05:53:32 PM PDT 24
Finished Jun 30 05:53:33 PM PDT 24
Peak memory 216056 kb
Host smart-ffcb36c3-b264-4d3b-a080-edccb38ae989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637957245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3637957245 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.3984836394
Short name T134
Test name
Test status
Simulation time 77167488170 ps
CPU time 2254.53 seconds
Started Jun 30 05:53:29 PM PDT 24
Finished Jun 30 06:31:04 PM PDT 24
Peak memory 435068 kb
Host smart-f2c66342-3ea8-49a5-85e4-46d53ae7b4dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984836394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.3984836394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.2011392773
Short name T193
Test name
Test status
Simulation time 26857513273 ps
CPU time 132.73 seconds
Started Jun 30 05:53:29 PM PDT 24
Finished Jun 30 05:55:42 PM PDT 24
Peak memory 230984 kb
Host smart-f568273f-dc7d-4ce3-95cd-7152526548d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011392773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2011392773 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.2997827613
Short name T970
Test name
Test status
Simulation time 3358543527 ps
CPU time 45.5 seconds
Started Jun 30 05:53:26 PM PDT 24
Finished Jun 30 05:54:12 PM PDT 24
Peak memory 216156 kb
Host smart-f4ce6e80-dd8d-4b3b-b7ea-1d67977cd617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997827613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2997827613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.1125471253
Short name T703
Test name
Test status
Simulation time 34368177836 ps
CPU time 924.09 seconds
Started Jun 30 05:53:33 PM PDT 24
Finished Jun 30 06:08:57 PM PDT 24
Peak memory 332880 kb
Host smart-a14104d4-8c8f-4102-a18d-74452901951d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1125471253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1125471253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.2772191345
Short name T734
Test name
Test status
Simulation time 69029078 ps
CPU time 4.11 seconds
Started Jun 30 05:53:26 PM PDT 24
Finished Jun 30 05:53:30 PM PDT 24
Peak memory 209324 kb
Host smart-e0417b9f-7f9f-4bdd-bbad-42cf48b363c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772191345 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.2772191345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3136338977
Short name T637
Test name
Test status
Simulation time 257412904 ps
CPU time 4.04 seconds
Started Jun 30 05:53:26 PM PDT 24
Finished Jun 30 05:53:31 PM PDT 24
Peak memory 216092 kb
Host smart-096e32b9-d5d2-4f89-9c12-885b92ff6986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136338977 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3136338977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.3216546509
Short name T371
Test name
Test status
Simulation time 77045852672 ps
CPU time 1527.94 seconds
Started Jun 30 05:53:25 PM PDT 24
Finished Jun 30 06:18:54 PM PDT 24
Peak memory 400916 kb
Host smart-f44c0f2d-e023-430a-8893-fdcde53dee85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3216546509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.3216546509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.3123209996
Short name T1025
Test name
Test status
Simulation time 97207827089 ps
CPU time 1866.25 seconds
Started Jun 30 05:53:26 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 391376 kb
Host smart-75ffd7ed-58c7-4d47-b430-605906181027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3123209996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.3123209996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.3034688320
Short name T915
Test name
Test status
Simulation time 95144366017 ps
CPU time 1143.22 seconds
Started Jun 30 05:53:25 PM PDT 24
Finished Jun 30 06:12:29 PM PDT 24
Peak memory 329140 kb
Host smart-09f2087f-d432-408d-92ed-60992131ce79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3034688320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.3034688320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.4281504917
Short name T719
Test name
Test status
Simulation time 66918690199 ps
CPU time 899.93 seconds
Started Jun 30 05:53:29 PM PDT 24
Finished Jun 30 06:08:29 PM PDT 24
Peak memory 296628 kb
Host smart-3a92d1a0-f88b-40ce-a116-3c910aca4932
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4281504917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.4281504917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.3046138133
Short name T228
Test name
Test status
Simulation time 507772887892 ps
CPU time 5250.18 seconds
Started Jun 30 05:53:26 PM PDT 24
Finished Jun 30 07:20:57 PM PDT 24
Peak memory 641768 kb
Host smart-003f95fd-2f9a-4d49-b297-f6b7487ac4f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3046138133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.3046138133 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.1263936815
Short name T986
Test name
Test status
Simulation time 575696789043 ps
CPU time 3729.69 seconds
Started Jun 30 05:53:28 PM PDT 24
Finished Jun 30 06:55:38 PM PDT 24
Peak memory 552908 kb
Host smart-8116ce1b-fafb-4e23-8f5d-72bb96687986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1263936815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.1263936815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.3768779465
Short name T44
Test name
Test status
Simulation time 23338113 ps
CPU time 0.77 seconds
Started Jun 30 05:53:48 PM PDT 24
Finished Jun 30 05:53:49 PM PDT 24
Peak memory 205592 kb
Host smart-9db789c5-b9de-4dfa-89ac-bc608fe81f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768779465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3768779465 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.1652521708
Short name T958
Test name
Test status
Simulation time 49582371631 ps
CPU time 272.17 seconds
Started Jun 30 05:53:38 PM PDT 24
Finished Jun 30 05:58:11 PM PDT 24
Peak memory 242844 kb
Host smart-2220371f-a25d-43ce-ba3a-fa49cabd0767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652521708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1652521708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.3110324323
Short name T720
Test name
Test status
Simulation time 5314720299 ps
CPU time 428.01 seconds
Started Jun 30 05:53:32 PM PDT 24
Finished Jun 30 06:00:41 PM PDT 24
Peak memory 229264 kb
Host smart-c39aa705-6307-47e3-b75c-02e254c1929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110324323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3110324323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3075238293
Short name T1043
Test name
Test status
Simulation time 439721123 ps
CPU time 5.86 seconds
Started Jun 30 05:53:37 PM PDT 24
Finished Jun 30 05:53:44 PM PDT 24
Peak memory 222932 kb
Host smart-b29f6559-67ef-4510-971f-71e29883866f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3075238293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3075238293 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.684949501
Short name T321
Test name
Test status
Simulation time 15363719974 ps
CPU time 21.39 seconds
Started Jun 30 05:53:38 PM PDT 24
Finished Jun 30 05:54:00 PM PDT 24
Peak memory 224248 kb
Host smart-8ff4d5d5-d72a-41c6-b5fa-d2875efa8d48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=684949501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.684949501 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.2905833680
Short name T570
Test name
Test status
Simulation time 6386669416 ps
CPU time 109.88 seconds
Started Jun 30 05:53:39 PM PDT 24
Finished Jun 30 05:55:29 PM PDT 24
Peak memory 233132 kb
Host smart-d71e54f3-3d63-434e-be5a-6405fda8ebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905833680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2905833680 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.1715097482
Short name T260
Test name
Test status
Simulation time 2748233432 ps
CPU time 37.07 seconds
Started Jun 30 05:53:37 PM PDT 24
Finished Jun 30 05:54:15 PM PDT 24
Peak memory 239128 kb
Host smart-0cb54fb1-3687-4d75-b9e6-9f3c6ae52506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715097482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1715097482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.933405879
Short name T542
Test name
Test status
Simulation time 1982252789 ps
CPU time 5.47 seconds
Started Jun 30 05:53:41 PM PDT 24
Finished Jun 30 05:53:46 PM PDT 24
Peak memory 207804 kb
Host smart-c0ff9bd1-5847-4525-a73a-54f055f80ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933405879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.933405879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.3565339460
Short name T977
Test name
Test status
Simulation time 36970342 ps
CPU time 1.26 seconds
Started Jun 30 05:53:38 PM PDT 24
Finished Jun 30 05:53:40 PM PDT 24
Peak memory 219936 kb
Host smart-4f4283ea-69cc-441e-ad81-e02b08064f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565339460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3565339460 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1873250852
Short name T523
Test name
Test status
Simulation time 435126145017 ps
CPU time 1187.56 seconds
Started Jun 30 05:53:32 PM PDT 24
Finished Jun 30 06:13:21 PM PDT 24
Peak memory 313644 kb
Host smart-ab59beca-a27f-461e-aaeb-d99546e8d11c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873250852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1873250852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.3780064812
Short name T489
Test name
Test status
Simulation time 859687124 ps
CPU time 63.82 seconds
Started Jun 30 05:53:32 PM PDT 24
Finished Jun 30 05:54:36 PM PDT 24
Peak memory 224336 kb
Host smart-16c1f341-3c23-4263-a66c-ac9139d059ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780064812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3780064812 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.2421164437
Short name T601
Test name
Test status
Simulation time 3125404516 ps
CPU time 21.85 seconds
Started Jun 30 05:53:33 PM PDT 24
Finished Jun 30 05:53:55 PM PDT 24
Peak memory 216440 kb
Host smart-b3ed0906-b09b-4026-abfe-7b5cae8aa8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421164437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2421164437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.2445470707
Short name T936
Test name
Test status
Simulation time 300627065157 ps
CPU time 655.28 seconds
Started Jun 30 05:53:39 PM PDT 24
Finished Jun 30 06:04:34 PM PDT 24
Peak memory 293132 kb
Host smart-af7d4b20-87f1-42d0-b712-c475af8ed547
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2445470707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2445470707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.3078226389
Short name T920
Test name
Test status
Simulation time 658748824 ps
CPU time 4.57 seconds
Started Jun 30 05:53:37 PM PDT 24
Finished Jun 30 05:53:42 PM PDT 24
Peak memory 216136 kb
Host smart-54761c9a-f2a0-495e-8cae-1fedd3071701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078226389 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.3078226389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2681285895
Short name T253
Test name
Test status
Simulation time 1011307079 ps
CPU time 4.04 seconds
Started Jun 30 05:53:38 PM PDT 24
Finished Jun 30 05:53:43 PM PDT 24
Peak memory 216132 kb
Host smart-d71d5880-6452-40c4-be66-928eaf5358da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681285895 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2681285895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3861494053
Short name T613
Test name
Test status
Simulation time 96635863155 ps
CPU time 1977.49 seconds
Started Jun 30 05:53:31 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 390540 kb
Host smart-6612a694-70cf-4823-bd94-8bc756b9261a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3861494053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3861494053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.2953015193
Short name T392
Test name
Test status
Simulation time 18236882982 ps
CPU time 1381.37 seconds
Started Jun 30 05:53:31 PM PDT 24
Finished Jun 30 06:16:33 PM PDT 24
Peak memory 369772 kb
Host smart-b3436e6a-c541-4672-8ea4-090b57a3785b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2953015193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.2953015193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.2079965668
Short name T192
Test name
Test status
Simulation time 28517680688 ps
CPU time 1146.35 seconds
Started Jun 30 05:53:32 PM PDT 24
Finished Jun 30 06:12:39 PM PDT 24
Peak memory 336924 kb
Host smart-3a6f6cbb-4a4d-4861-9662-9e47f2c39155
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2079965668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.2079965668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.4072537209
Short name T520
Test name
Test status
Simulation time 83725391776 ps
CPU time 985.45 seconds
Started Jun 30 05:53:32 PM PDT 24
Finished Jun 30 06:09:59 PM PDT 24
Peak memory 291384 kb
Host smart-ab725969-bce5-4b65-981e-f78b73ea6c33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4072537209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.4072537209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.4274530243
Short name T1069
Test name
Test status
Simulation time 53179802521 ps
CPU time 4000.81 seconds
Started Jun 30 05:53:38 PM PDT 24
Finished Jun 30 07:00:20 PM PDT 24
Peak memory 654336 kb
Host smart-09afe6e6-ae6d-4e29-a7d1-3c66fc3bda7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4274530243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.4274530243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1587708991
Short name T922
Test name
Test status
Simulation time 89659600513 ps
CPU time 3323.21 seconds
Started Jun 30 05:53:41 PM PDT 24
Finished Jun 30 06:49:05 PM PDT 24
Peak memory 557732 kb
Host smart-3fc91dae-eea3-4b54-aaa7-e3bfacb19951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1587708991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1587708991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.2785562786
Short name T878
Test name
Test status
Simulation time 14333956 ps
CPU time 0.79 seconds
Started Jun 30 05:53:50 PM PDT 24
Finished Jun 30 05:53:51 PM PDT 24
Peak memory 205636 kb
Host smart-4a6d57a4-f373-4ba8-9526-5f1c57443ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785562786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2785562786 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.1032171159
Short name T454
Test name
Test status
Simulation time 769727524 ps
CPU time 35.88 seconds
Started Jun 30 05:53:51 PM PDT 24
Finished Jun 30 05:54:28 PM PDT 24
Peak memory 222072 kb
Host smart-b64c0e9b-dc36-48be-b962-bc69838dcac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032171159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1032171159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3121455085
Short name T568
Test name
Test status
Simulation time 126469068034 ps
CPU time 692.65 seconds
Started Jun 30 05:53:47 PM PDT 24
Finished Jun 30 06:05:20 PM PDT 24
Peak memory 231732 kb
Host smart-f81ac804-fde3-4ee0-9df8-4161bee4408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121455085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3121455085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.4163740064
Short name T666
Test name
Test status
Simulation time 1256943268 ps
CPU time 20.79 seconds
Started Jun 30 05:53:51 PM PDT 24
Finished Jun 30 05:54:13 PM PDT 24
Peak memory 224212 kb
Host smart-40e693f0-11e1-4e16-984e-0aa09c50e051
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4163740064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4163740064 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.677692268
Short name T562
Test name
Test status
Simulation time 4186605711 ps
CPU time 19.72 seconds
Started Jun 30 05:53:52 PM PDT 24
Finished Jun 30 05:54:12 PM PDT 24
Peak memory 224292 kb
Host smart-33c51a69-0351-4639-8438-e44804ba0a22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=677692268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.677692268 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.3149603173
Short name T348
Test name
Test status
Simulation time 24992458842 ps
CPU time 155.68 seconds
Started Jun 30 05:53:51 PM PDT 24
Finished Jun 30 05:56:28 PM PDT 24
Peak memory 237024 kb
Host smart-018adb6b-14f8-417c-9995-ff13e7d5929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149603173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3149603173 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.4257994332
Short name T29
Test name
Test status
Simulation time 258176923 ps
CPU time 9.71 seconds
Started Jun 30 05:53:51 PM PDT 24
Finished Jun 30 05:54:01 PM PDT 24
Peak memory 224536 kb
Host smart-3fb04d6c-39f8-48d2-b3c2-6ed2d37967f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257994332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.4257994332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.425333890
Short name T417
Test name
Test status
Simulation time 27102919722 ps
CPU time 12.79 seconds
Started Jun 30 05:53:52 PM PDT 24
Finished Jun 30 05:54:05 PM PDT 24
Peak memory 216120 kb
Host smart-cdff54af-06c8-495c-92de-990ddab801a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425333890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.425333890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.2465363366
Short name T326
Test name
Test status
Simulation time 145892500 ps
CPU time 1.27 seconds
Started Jun 30 05:53:51 PM PDT 24
Finished Jun 30 05:53:53 PM PDT 24
Peak memory 216124 kb
Host smart-9fe6fa02-5dee-4f09-ad0e-b816613b408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465363366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2465363366 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2900183747
Short name T902
Test name
Test status
Simulation time 27836392112 ps
CPU time 770.08 seconds
Started Jun 30 05:53:47 PM PDT 24
Finished Jun 30 06:06:38 PM PDT 24
Peak memory 297720 kb
Host smart-fb9ed83b-91fd-432e-84bd-c25da29bce17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900183747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2900183747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.3070061613
Short name T604
Test name
Test status
Simulation time 2316022347 ps
CPU time 186.25 seconds
Started Jun 30 05:53:44 PM PDT 24
Finished Jun 30 05:56:51 PM PDT 24
Peak memory 237448 kb
Host smart-f10012d4-196a-49a9-aa4a-65bcbaa4baac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070061613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3070061613 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.1326598689
Short name T975
Test name
Test status
Simulation time 54071652 ps
CPU time 3.16 seconds
Started Jun 30 05:53:44 PM PDT 24
Finished Jun 30 05:53:48 PM PDT 24
Peak memory 218296 kb
Host smart-e4523f36-6d03-48e5-b8ee-3851a4eead10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326598689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1326598689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.63000024
Short name T74
Test name
Test status
Simulation time 120749930331 ps
CPU time 2315.09 seconds
Started Jun 30 05:53:52 PM PDT 24
Finished Jun 30 06:32:28 PM PDT 24
Peak memory 518644 kb
Host smart-9d53c104-0624-49ab-b9b9-17d7508abb5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=63000024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.63000024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.1762741353
Short name T909
Test name
Test status
Simulation time 1781455998 ps
CPU time 5.34 seconds
Started Jun 30 05:53:48 PM PDT 24
Finished Jun 30 05:53:54 PM PDT 24
Peak memory 216204 kb
Host smart-dc7e0ab3-2773-4796-be4e-e8f56c859e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762741353 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.1762741353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.1469530717
Short name T196
Test name
Test status
Simulation time 972101735 ps
CPU time 4.74 seconds
Started Jun 30 05:53:51 PM PDT 24
Finished Jun 30 05:53:57 PM PDT 24
Peak memory 216148 kb
Host smart-b23e6c08-b542-41f7-b95f-97b35cb5f805
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469530717 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.1469530717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.1563964050
Short name T527
Test name
Test status
Simulation time 19058744117 ps
CPU time 1671.53 seconds
Started Jun 30 05:53:44 PM PDT 24
Finished Jun 30 06:21:36 PM PDT 24
Peak memory 397572 kb
Host smart-b1642a70-85a5-4b96-8c87-4659a61f2dc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1563964050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1563964050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3555700370
Short name T340
Test name
Test status
Simulation time 68498698338 ps
CPU time 1531.94 seconds
Started Jun 30 05:53:44 PM PDT 24
Finished Jun 30 06:19:17 PM PDT 24
Peak memory 372120 kb
Host smart-09930dc3-b5ea-4e20-b168-4cc23754a43a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3555700370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3555700370 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.1742049966
Short name T460
Test name
Test status
Simulation time 71656638374 ps
CPU time 1347.05 seconds
Started Jun 30 05:53:44 PM PDT 24
Finished Jun 30 06:16:11 PM PDT 24
Peak memory 332920 kb
Host smart-3bff05ed-695a-4317-a480-e89052b429b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1742049966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1742049966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.1781153340
Short name T718
Test name
Test status
Simulation time 63920433238 ps
CPU time 971.43 seconds
Started Jun 30 05:53:48 PM PDT 24
Finished Jun 30 06:10:00 PM PDT 24
Peak memory 297484 kb
Host smart-8a9cfec0-c516-4a9c-8011-5bea5e59efad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1781153340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1781153340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.3601648224
Short name T1060
Test name
Test status
Simulation time 1545093758621 ps
CPU time 4620.55 seconds
Started Jun 30 05:53:45 PM PDT 24
Finished Jun 30 07:10:46 PM PDT 24
Peak memory 638148 kb
Host smart-587d0fed-2c8a-4a47-8e5d-693f1353118a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3601648224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3601648224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.3868857050
Short name T794
Test name
Test status
Simulation time 219065126419 ps
CPU time 4525.25 seconds
Started Jun 30 05:53:47 PM PDT 24
Finished Jun 30 07:09:14 PM PDT 24
Peak memory 571464 kb
Host smart-8cace192-36c2-4eda-af5c-6b6491c0b513
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3868857050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3868857050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.4004872481
Short name T64
Test name
Test status
Simulation time 14846985 ps
CPU time 0.77 seconds
Started Jun 30 05:54:03 PM PDT 24
Finished Jun 30 05:54:04 PM PDT 24
Peak memory 205644 kb
Host smart-ed83ddbc-f110-4e43-b206-4c45f8d3c11a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004872481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.4004872481 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.2664440192
Short name T377
Test name
Test status
Simulation time 6494046852 ps
CPU time 72.71 seconds
Started Jun 30 05:53:57 PM PDT 24
Finished Jun 30 05:55:10 PM PDT 24
Peak memory 228084 kb
Host smart-b155c64f-4334-4f9c-811f-f225f79a7f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664440192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2664440192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.3799373379
Short name T1061
Test name
Test status
Simulation time 2846230004 ps
CPU time 35.62 seconds
Started Jun 30 05:54:04 PM PDT 24
Finished Jun 30 05:54:39 PM PDT 24
Peak memory 224676 kb
Host smart-7a958763-d572-4b4b-9f0d-3aca2d52ad16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799373379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3799373379 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2853629014
Short name T135
Test name
Test status
Simulation time 584417381 ps
CPU time 21.89 seconds
Started Jun 30 05:54:04 PM PDT 24
Finished Jun 30 05:54:27 PM PDT 24
Peak memory 221024 kb
Host smart-91e0059f-ca5f-4ab2-87e2-2fdb87c72b93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2853629014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2853629014 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.4018108783
Short name T240
Test name
Test status
Simulation time 10300895289 ps
CPU time 161.65 seconds
Started Jun 30 05:53:55 PM PDT 24
Finished Jun 30 05:56:37 PM PDT 24
Peak memory 237336 kb
Host smart-99b74625-2685-44a2-b0f2-c09f6364cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018108783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.4018108783 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.3092602505
Short name T477
Test name
Test status
Simulation time 2724696060 ps
CPU time 210.55 seconds
Started Jun 30 05:53:57 PM PDT 24
Finished Jun 30 05:57:28 PM PDT 24
Peak memory 251292 kb
Host smart-2625e68e-cfb7-4732-b696-262fdcc0e77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092602505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3092602505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.2943558997
Short name T845
Test name
Test status
Simulation time 698818591 ps
CPU time 3.85 seconds
Started Jun 30 05:54:05 PM PDT 24
Finished Jun 30 05:54:09 PM PDT 24
Peak memory 207772 kb
Host smart-1b67728d-11f7-49e1-b7eb-1805cdd539d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943558997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2943558997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1878284465
Short name T755
Test name
Test status
Simulation time 44503337 ps
CPU time 1.42 seconds
Started Jun 30 05:54:04 PM PDT 24
Finished Jun 30 05:54:06 PM PDT 24
Peak memory 216060 kb
Host smart-a07d0b38-9958-4824-af8a-866d6e27f930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878284465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1878284465 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.3504923616
Short name T390
Test name
Test status
Simulation time 6210256222 ps
CPU time 307.06 seconds
Started Jun 30 05:53:51 PM PDT 24
Finished Jun 30 05:58:59 PM PDT 24
Peak memory 251592 kb
Host smart-aae40b12-89c1-4f23-ac24-054f102ac252
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504923616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.3504923616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.4226858467
Short name T223
Test name
Test status
Simulation time 2391152854 ps
CPU time 63.1 seconds
Started Jun 30 05:53:56 PM PDT 24
Finished Jun 30 05:55:00 PM PDT 24
Peak memory 223604 kb
Host smart-21ddd161-bf5b-4e9b-bf9d-ee8b595e230d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226858467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.4226858467 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.573098230
Short name T200
Test name
Test status
Simulation time 8864771786 ps
CPU time 26.2 seconds
Started Jun 30 05:53:52 PM PDT 24
Finished Jun 30 05:54:19 PM PDT 24
Peak memory 219768 kb
Host smart-fdd8b736-619d-453f-9c87-22ec6a6bb741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573098230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.573098230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.1188260004
Short name T345
Test name
Test status
Simulation time 53481350111 ps
CPU time 1132.5 seconds
Started Jun 30 05:54:02 PM PDT 24
Finished Jun 30 06:12:55 PM PDT 24
Peak memory 332788 kb
Host smart-56576683-8621-467b-9c7b-15585d07267f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1188260004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1188260004 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.936489199
Short name T788
Test name
Test status
Simulation time 240746506 ps
CPU time 4.17 seconds
Started Jun 30 05:53:58 PM PDT 24
Finished Jun 30 05:54:02 PM PDT 24
Peak memory 209216 kb
Host smart-c088272c-b2b5-4431-bf88-6a1554a8aeb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936489199 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.936489199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3592962969
Short name T529
Test name
Test status
Simulation time 235418909 ps
CPU time 4.34 seconds
Started Jun 30 05:53:56 PM PDT 24
Finished Jun 30 05:54:01 PM PDT 24
Peak memory 216144 kb
Host smart-d77e7ac1-8981-4efb-a1cd-77a428a7f46a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592962969 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3592962969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.3063241987
Short name T421
Test name
Test status
Simulation time 320582733917 ps
CPU time 1871.11 seconds
Started Jun 30 05:53:56 PM PDT 24
Finished Jun 30 06:25:08 PM PDT 24
Peak memory 388360 kb
Host smart-807e286d-80fd-4a76-beab-d77c5551a48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3063241987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3063241987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.3351556878
Short name T257
Test name
Test status
Simulation time 176142027465 ps
CPU time 1726.68 seconds
Started Jun 30 05:53:56 PM PDT 24
Finished Jun 30 06:22:44 PM PDT 24
Peak memory 377868 kb
Host smart-a27e5657-fb81-4b15-9cad-deb9e4be9078
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3351556878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.3351556878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.2472712130
Short name T213
Test name
Test status
Simulation time 49019284649 ps
CPU time 1271.95 seconds
Started Jun 30 05:53:56 PM PDT 24
Finished Jun 30 06:15:08 PM PDT 24
Peak memory 338552 kb
Host smart-ce540da3-74f5-4509-8edb-4ea300eba7c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2472712130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.2472712130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.3464250630
Short name T955
Test name
Test status
Simulation time 9904309303 ps
CPU time 789.01 seconds
Started Jun 30 05:53:57 PM PDT 24
Finished Jun 30 06:07:07 PM PDT 24
Peak memory 297068 kb
Host smart-8e2c9704-fcec-4b34-bf9d-1399b13d2b1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3464250630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.3464250630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.3291555522
Short name T765
Test name
Test status
Simulation time 540514032305 ps
CPU time 5223.14 seconds
Started Jun 30 05:53:57 PM PDT 24
Finished Jun 30 07:21:01 PM PDT 24
Peak memory 660988 kb
Host smart-760087a3-1515-4c10-8a5b-cccfdc4fa6c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3291555522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.3291555522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.3990957585
Short name T653
Test name
Test status
Simulation time 308746993328 ps
CPU time 4295.58 seconds
Started Jun 30 05:53:56 PM PDT 24
Finished Jun 30 07:05:33 PM PDT 24
Peak memory 559620 kb
Host smart-ea3cf3d4-854f-4b5d-89ee-7992209c8aa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3990957585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.3990957585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2834178139
Short name T862
Test name
Test status
Simulation time 15121601 ps
CPU time 0.81 seconds
Started Jun 30 05:54:10 PM PDT 24
Finished Jun 30 05:54:11 PM PDT 24
Peak memory 205864 kb
Host smart-1ec4952c-e655-4503-bf62-9b0b92a16a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834178139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2834178139 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3872123151
Short name T864
Test name
Test status
Simulation time 3957704943 ps
CPU time 78.24 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 05:55:30 PM PDT 24
Peak memory 227484 kb
Host smart-113d69e6-4979-4f13-a9eb-a95140e96fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872123151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3872123151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.4151772404
Short name T913
Test name
Test status
Simulation time 47862630043 ps
CPU time 372.29 seconds
Started Jun 30 05:54:03 PM PDT 24
Finished Jun 30 06:00:15 PM PDT 24
Peak memory 228864 kb
Host smart-f24546e1-d034-4d7d-894b-d3fda93a948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151772404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.4151772404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3517158500
Short name T705
Test name
Test status
Simulation time 1726235508 ps
CPU time 26.54 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 05:54:38 PM PDT 24
Peak memory 224128 kb
Host smart-523b413f-ec3f-4ca7-859a-3f8e77ed2312
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3517158500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3517158500 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.2238371655
Short name T1017
Test name
Test status
Simulation time 59138523 ps
CPU time 4.09 seconds
Started Jun 30 05:54:08 PM PDT 24
Finished Jun 30 05:54:12 PM PDT 24
Peak memory 217084 kb
Host smart-37b3a4df-399a-49c0-b420-8f66e2d59020
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2238371655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2238371655 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.690220555
Short name T530
Test name
Test status
Simulation time 549574563 ps
CPU time 19.98 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 05:54:32 PM PDT 24
Peak memory 218736 kb
Host smart-13b9d9cb-280c-4af6-8581-0f01f9bba0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690220555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.690220555 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.1475298449
Short name T167
Test name
Test status
Simulation time 2395479950 ps
CPU time 61.93 seconds
Started Jun 30 05:54:10 PM PDT 24
Finished Jun 30 05:55:12 PM PDT 24
Peak memory 240764 kb
Host smart-687869d4-d31d-4bdf-95d9-d6712f88a7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475298449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1475298449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.4074917290
Short name T869
Test name
Test status
Simulation time 1186548519 ps
CPU time 3.55 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 05:54:15 PM PDT 24
Peak memory 207856 kb
Host smart-3fb09a49-ac7a-4765-8849-945391a56277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074917290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.4074917290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.187756894
Short name T730
Test name
Test status
Simulation time 170925700 ps
CPU time 1.25 seconds
Started Jun 30 05:54:10 PM PDT 24
Finished Jun 30 05:54:12 PM PDT 24
Peak memory 216032 kb
Host smart-a2c94bcd-00b3-4d0b-864b-7b458866aa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187756894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.187756894 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.4200606601
Short name T686
Test name
Test status
Simulation time 379721219677 ps
CPU time 1531.68 seconds
Started Jun 30 05:54:05 PM PDT 24
Finished Jun 30 06:19:37 PM PDT 24
Peak memory 356328 kb
Host smart-c7490615-6ba0-492b-8ad3-3df25d3ccc9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200606601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.4200606601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2071312069
Short name T722
Test name
Test status
Simulation time 24702163258 ps
CPU time 305.79 seconds
Started Jun 30 05:54:03 PM PDT 24
Finished Jun 30 05:59:09 PM PDT 24
Peak memory 244312 kb
Host smart-206a405f-4db8-43bf-a726-7a0c145d5692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071312069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2071312069 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.620637857
Short name T352
Test name
Test status
Simulation time 505076015 ps
CPU time 7.21 seconds
Started Jun 30 05:54:03 PM PDT 24
Finished Jun 30 05:54:10 PM PDT 24
Peak memory 219296 kb
Host smart-b704401f-7783-4cbf-a68d-5ebd43430d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620637857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.620637857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.2761849545
Short name T191
Test name
Test status
Simulation time 67882210 ps
CPU time 3.76 seconds
Started Jun 30 05:54:08 PM PDT 24
Finished Jun 30 05:54:12 PM PDT 24
Peak memory 216180 kb
Host smart-82ced22a-4e3c-423e-b4fb-f14914b8a0ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761849545 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.2761849545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3391805298
Short name T427
Test name
Test status
Simulation time 714845919 ps
CPU time 4.46 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 05:54:16 PM PDT 24
Peak memory 216196 kb
Host smart-69430a25-b66c-4ed4-82ab-7d8be68c2a8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391805298 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3391805298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.2113523693
Short name T923
Test name
Test status
Simulation time 145997004189 ps
CPU time 1472.37 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 06:18:44 PM PDT 24
Peak memory 395248 kb
Host smart-6756925e-303f-422a-8c89-8c1491de87cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2113523693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.2113523693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.4001949114
Short name T711
Test name
Test status
Simulation time 182142853982 ps
CPU time 1897.19 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 06:25:49 PM PDT 24
Peak memory 373460 kb
Host smart-3770d107-3d69-4389-aafe-8acd292a9473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4001949114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.4001949114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.2396767449
Short name T748
Test name
Test status
Simulation time 13549105640 ps
CPU time 1132.11 seconds
Started Jun 30 05:54:12 PM PDT 24
Finished Jun 30 06:13:04 PM PDT 24
Peak memory 328216 kb
Host smart-1e521b75-8c70-44d5-b859-9755a800016e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2396767449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2396767449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.2471750665
Short name T385
Test name
Test status
Simulation time 32046599631 ps
CPU time 882.92 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 06:08:54 PM PDT 24
Peak memory 292172 kb
Host smart-5c2a3715-11ed-4196-8398-4631e5c0d068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2471750665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.2471750665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.1460348306
Short name T981
Test name
Test status
Simulation time 663016202610 ps
CPU time 4917.87 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 07:16:10 PM PDT 24
Peak memory 664296 kb
Host smart-528a2790-bc62-49fc-91f4-962bdb4b06dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1460348306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1460348306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.1035597541
Short name T758
Test name
Test status
Simulation time 217289841346 ps
CPU time 4255.36 seconds
Started Jun 30 05:54:10 PM PDT 24
Finished Jun 30 07:05:06 PM PDT 24
Peak memory 562900 kb
Host smart-b11a02e9-69d6-474d-b3c0-62b0d1bb7124
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1035597541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1035597541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.3206987609
Short name T675
Test name
Test status
Simulation time 123878375 ps
CPU time 0.82 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:51:41 PM PDT 24
Peak memory 205596 kb
Host smart-0f0e44e4-525e-4a20-ab36-4d300aee2916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206987609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3206987609 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.602261472
Short name T247
Test name
Test status
Simulation time 10837644591 ps
CPU time 166 seconds
Started Jun 30 05:51:38 PM PDT 24
Finished Jun 30 05:54:25 PM PDT 24
Peak memory 238132 kb
Host smart-b3864dde-317a-4c38-a5dc-d38c31a31e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602261472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.602261472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.1668892626
Short name T258
Test name
Test status
Simulation time 15700804419 ps
CPU time 248.3 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:55:49 PM PDT 24
Peak memory 244564 kb
Host smart-10721b2f-8943-4e00-ad57-82a6696acbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668892626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1668892626 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2695830914
Short name T538
Test name
Test status
Simulation time 1619170678 ps
CPU time 11.63 seconds
Started Jun 30 05:51:41 PM PDT 24
Finished Jun 30 05:51:54 PM PDT 24
Peak memory 217432 kb
Host smart-966aea7c-c1ad-4462-ac48-0b66352674b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695830914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2695830914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.3995790022
Short name T269
Test name
Test status
Simulation time 810111832 ps
CPU time 11.95 seconds
Started Jun 30 05:51:38 PM PDT 24
Finished Jun 30 05:51:50 PM PDT 24
Peak memory 216116 kb
Host smart-bf7d0b5a-3c3e-466f-8d61-7288da817c27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3995790022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3995790022 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1170958155
Short name T563
Test name
Test status
Simulation time 6479296986 ps
CPU time 34.5 seconds
Started Jun 30 05:51:43 PM PDT 24
Finished Jun 30 05:52:18 PM PDT 24
Peak memory 224280 kb
Host smart-2557bfe0-b48d-45b1-88fa-f5676dbf4e82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1170958155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1170958155 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.178417988
Short name T996
Test name
Test status
Simulation time 30502814606 ps
CPU time 63.39 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:52:43 PM PDT 24
Peak memory 224516 kb
Host smart-e7d0184e-f749-40d6-8273-883569a43910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178417988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.178417988 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.657408321
Short name T822
Test name
Test status
Simulation time 1194295532 ps
CPU time 85.72 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:53:05 PM PDT 24
Peak memory 240696 kb
Host smart-9dec4992-49eb-4bf7-805c-2154def75e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657408321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.657408321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.1463778934
Short name T962
Test name
Test status
Simulation time 1607141725 ps
CPU time 2.53 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:51:43 PM PDT 24
Peak memory 207748 kb
Host smart-af1e37f6-29f6-4397-afcd-b988fe19802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463778934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1463778934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.3471214885
Short name T211
Test name
Test status
Simulation time 238830216508 ps
CPU time 1479.12 seconds
Started Jun 30 05:51:38 PM PDT 24
Finished Jun 30 06:16:18 PM PDT 24
Peak memory 354920 kb
Host smart-481773c1-6099-4134-a7ab-4a13f50e704a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471214885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.3471214885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.872903819
Short name T836
Test name
Test status
Simulation time 4804441071 ps
CPU time 116.34 seconds
Started Jun 30 05:51:41 PM PDT 24
Finished Jun 30 05:53:38 PM PDT 24
Peak memory 231672 kb
Host smart-bad3922e-3629-439b-ad47-1cd1e207257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872903819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.872903819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.3207090465
Short name T11
Test name
Test status
Simulation time 8169818035 ps
CPU time 58.55 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:52:39 PM PDT 24
Peak memory 264272 kb
Host smart-067a97ae-1e2b-4842-bfc1-683bdbead0d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207090465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3207090465 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.4050230679
Short name T963
Test name
Test status
Simulation time 960144200 ps
CPU time 24.06 seconds
Started Jun 30 05:51:37 PM PDT 24
Finished Jun 30 05:52:01 PM PDT 24
Peak memory 224256 kb
Host smart-c4139e48-3e45-45b3-a63e-76e03dc312f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050230679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.4050230679 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.571124051
Short name T444
Test name
Test status
Simulation time 4171195339 ps
CPU time 54.59 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:52:35 PM PDT 24
Peak memory 217788 kb
Host smart-6c876a38-4900-4abe-8895-7fa713de782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571124051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.571124051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.4121012957
Short name T349
Test name
Test status
Simulation time 76376302692 ps
CPU time 263.2 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 05:56:03 PM PDT 24
Peak memory 251376 kb
Host smart-d14cb433-7cd0-4f0d-ba6b-52a20fb35bad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4121012957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.4121012957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.2086212586
Short name T47
Test name
Test status
Simulation time 55865607482 ps
CPU time 1221.04 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 06:12:02 PM PDT 24
Peak memory 338980 kb
Host smart-1bdc3d2b-f40e-4fb0-afe6-996d10276ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086212586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.2086212586 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.1104366729
Short name T592
Test name
Test status
Simulation time 68908340 ps
CPU time 3.95 seconds
Started Jun 30 05:51:38 PM PDT 24
Finished Jun 30 05:51:43 PM PDT 24
Peak memory 216136 kb
Host smart-5c7bd967-e7b6-4bb7-908c-3e4d378031ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104366729 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.1104366729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.954522778
Short name T935
Test name
Test status
Simulation time 327318626 ps
CPU time 5.04 seconds
Started Jun 30 05:51:40 PM PDT 24
Finished Jun 30 05:51:46 PM PDT 24
Peak memory 216136 kb
Host smart-4d2bf4a4-c349-41e4-9665-14c491bffad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954522778 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.954522778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.1548174114
Short name T451
Test name
Test status
Simulation time 19468427953 ps
CPU time 1535.21 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 06:17:16 PM PDT 24
Peak memory 393480 kb
Host smart-06ac42d3-0b77-4ba6-97ca-d38ca57f9259
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1548174114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1548174114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.11060789
Short name T833
Test name
Test status
Simulation time 18553527510 ps
CPU time 1473.53 seconds
Started Jun 30 05:51:38 PM PDT 24
Finished Jun 30 06:16:13 PM PDT 24
Peak memory 375576 kb
Host smart-cb4b5a05-ee17-4155-b373-2fb7d2bdd842
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11060789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.11060789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.633933729
Short name T947
Test name
Test status
Simulation time 284751729526 ps
CPU time 1561.84 seconds
Started Jun 30 05:51:44 PM PDT 24
Finished Jun 30 06:17:47 PM PDT 24
Peak memory 338600 kb
Host smart-e7afc978-b34b-41d0-8b35-aba53365d83f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=633933729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.633933729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2151952695
Short name T684
Test name
Test status
Simulation time 102441061415 ps
CPU time 1049.4 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 06:09:09 PM PDT 24
Peak memory 296688 kb
Host smart-93b53d58-863d-4449-a5f9-33cd01f83d43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2151952695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2151952695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.2235252293
Short name T521
Test name
Test status
Simulation time 100620452068 ps
CPU time 4035.55 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 06:58:56 PM PDT 24
Peak memory 639188 kb
Host smart-7c2b2645-bb2b-44b7-9c53-bf6f8725e784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2235252293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2235252293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.4128741381
Short name T569
Test name
Test status
Simulation time 218110021171 ps
CPU time 4400.1 seconds
Started Jun 30 05:51:39 PM PDT 24
Finished Jun 30 07:05:00 PM PDT 24
Peak memory 569752 kb
Host smart-33833cf2-8f1a-498a-ade5-521112a3c5d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4128741381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.4128741381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.2660919255
Short name T436
Test name
Test status
Simulation time 21662106 ps
CPU time 0.82 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:54:21 PM PDT 24
Peak memory 205612 kb
Host smart-8cdf744b-ef11-4af6-93cb-658a0d74ef2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660919255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2660919255 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.3050384225
Short name T1026
Test name
Test status
Simulation time 1512004163 ps
CPU time 30.52 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:54:50 PM PDT 24
Peak memory 224312 kb
Host smart-29ebeea0-1a53-40b3-a6a8-bb387ec02dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050384225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3050384225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2581218186
Short name T142
Test name
Test status
Simulation time 27162718638 ps
CPU time 137.73 seconds
Started Jun 30 05:54:10 PM PDT 24
Finished Jun 30 05:56:28 PM PDT 24
Peak memory 223344 kb
Host smart-295929e7-0d3d-4bbf-bbc7-75ccae02d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581218186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2581218186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.3033901267
Short name T405
Test name
Test status
Simulation time 9519924339 ps
CPU time 193.91 seconds
Started Jun 30 05:54:20 PM PDT 24
Finished Jun 30 05:57:34 PM PDT 24
Peak memory 237352 kb
Host smart-581f5a12-6083-438d-8a90-b9625c9eb216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033901267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3033901267 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.275978647
Short name T914
Test name
Test status
Simulation time 14329157465 ps
CPU time 287.93 seconds
Started Jun 30 05:54:18 PM PDT 24
Finished Jun 30 05:59:06 PM PDT 24
Peak memory 257176 kb
Host smart-57da68f5-45dc-4ad7-b746-a216f8dc3d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275978647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.275978647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.2834887180
Short name T1031
Test name
Test status
Simulation time 638478489 ps
CPU time 3.98 seconds
Started Jun 30 05:54:18 PM PDT 24
Finished Jun 30 05:54:22 PM PDT 24
Peak memory 207836 kb
Host smart-bc7cd88d-fec9-49a9-b91b-6cbd2d9fe636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834887180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2834887180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3045327122
Short name T383
Test name
Test status
Simulation time 21329759245 ps
CPU time 1791.36 seconds
Started Jun 30 05:54:09 PM PDT 24
Finished Jun 30 06:24:01 PM PDT 24
Peak memory 421880 kb
Host smart-c67b35aa-e999-4388-a6c5-20777231d8c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045327122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3045327122 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.3219892816
Short name T978
Test name
Test status
Simulation time 134740845 ps
CPU time 5.06 seconds
Started Jun 30 05:54:10 PM PDT 24
Finished Jun 30 05:54:15 PM PDT 24
Peak memory 220628 kb
Host smart-37588581-3689-45a8-8286-e590dc38ce09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219892816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3219892816 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.1098088320
Short name T875
Test name
Test status
Simulation time 2848431750 ps
CPU time 24.97 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 05:54:37 PM PDT 24
Peak memory 219260 kb
Host smart-45620d8c-aa56-4d1b-9bf8-dd36f83f1d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098088320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1098088320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2440160462
Short name T942
Test name
Test status
Simulation time 460687539 ps
CPU time 8.25 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:54:27 PM PDT 24
Peak memory 218924 kb
Host smart-c86e06c1-367d-4c58-9ee0-83ccfc6cd9b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2440160462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2440160462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.2566542342
Short name T323
Test name
Test status
Simulation time 67373479 ps
CPU time 3.84 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:54:23 PM PDT 24
Peak memory 216088 kb
Host smart-67773693-76ce-4d1a-87a8-1f1da3df00a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566542342 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.2566542342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.72579560
Short name T905
Test name
Test status
Simulation time 170320802 ps
CPU time 4.04 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:54:23 PM PDT 24
Peak memory 216112 kb
Host smart-a0b2a1dc-d110-437d-8eec-e461ffa78551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72579560 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.kmac_test_vectors_kmac_xof.72579560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.2568470033
Short name T291
Test name
Test status
Simulation time 312697854908 ps
CPU time 1697.92 seconds
Started Jun 30 05:54:11 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 391880 kb
Host smart-bbfed29e-c4ed-4e33-9f88-6ff653b83ab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2568470033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2568470033 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.4240072572
Short name T141
Test name
Test status
Simulation time 97473155993 ps
CPU time 1854.96 seconds
Started Jun 30 05:54:20 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 389484 kb
Host smart-cc550090-d044-442e-b61c-3cf77c58c6bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4240072572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.4240072572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.3248405750
Short name T791
Test name
Test status
Simulation time 13463826805 ps
CPU time 1094.07 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 06:12:33 PM PDT 24
Peak memory 331164 kb
Host smart-b1d17e1a-5fef-49ab-809d-6ebf2f4275a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3248405750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.3248405750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.2694948577
Short name T384
Test name
Test status
Simulation time 42612815900 ps
CPU time 923.17 seconds
Started Jun 30 05:54:18 PM PDT 24
Finished Jun 30 06:09:42 PM PDT 24
Peak memory 294884 kb
Host smart-18c5fa48-ae54-4f00-a525-cf871dc63f9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2694948577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.2694948577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2155281447
Short name T158
Test name
Test status
Simulation time 503673178963 ps
CPU time 4211.49 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 07:04:32 PM PDT 24
Peak memory 640944 kb
Host smart-e878192b-2862-421b-9ee7-a3cc8414cc66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2155281447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2155281447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.985451974
Short name T624
Test name
Test status
Simulation time 214837828678 ps
CPU time 3375.69 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 06:50:36 PM PDT 24
Peak memory 555896 kb
Host smart-a723cdec-3303-4706-96e2-89520391fbf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=985451974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.985451974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.404779808
Short name T887
Test name
Test status
Simulation time 44299480 ps
CPU time 0.82 seconds
Started Jun 30 05:54:33 PM PDT 24
Finished Jun 30 05:54:34 PM PDT 24
Peak memory 205648 kb
Host smart-1fc4d450-206c-4035-b207-f1d17a3a1b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404779808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.404779808 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.2293381198
Short name T817
Test name
Test status
Simulation time 2408704431 ps
CPU time 111.47 seconds
Started Jun 30 05:54:27 PM PDT 24
Finished Jun 30 05:56:19 PM PDT 24
Peak memory 233544 kb
Host smart-e9678a11-e6ef-452a-93d2-c9b1aff64646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293381198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2293381198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.2422382709
Short name T275
Test name
Test status
Simulation time 19139249337 ps
CPU time 244.72 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:58:24 PM PDT 24
Peak memory 225332 kb
Host smart-ec53e942-934c-4208-b8b3-417927ae9efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422382709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2422382709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.952524621
Short name T999
Test name
Test status
Simulation time 7804709644 ps
CPU time 139.31 seconds
Started Jun 30 05:54:28 PM PDT 24
Finished Jun 30 05:56:48 PM PDT 24
Peak memory 233640 kb
Host smart-74a87924-474f-483b-b7c4-9c9ee88fe32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952524621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.952524621 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.2939993137
Short name T71
Test name
Test status
Simulation time 3321529474 ps
CPU time 122.37 seconds
Started Jun 30 05:54:26 PM PDT 24
Finished Jun 30 05:56:28 PM PDT 24
Peak memory 248892 kb
Host smart-b55b5f1a-c98b-482d-a316-aa47286dd80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939993137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2939993137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.3102713608
Short name T775
Test name
Test status
Simulation time 5686293766 ps
CPU time 4.8 seconds
Started Jun 30 05:54:25 PM PDT 24
Finished Jun 30 05:54:30 PM PDT 24
Peak memory 216140 kb
Host smart-af6aaa81-94ca-4670-babc-083ee7413a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102713608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3102713608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.1259010992
Short name T1032
Test name
Test status
Simulation time 442010267 ps
CPU time 8.51 seconds
Started Jun 30 05:54:25 PM PDT 24
Finished Jun 30 05:54:34 PM PDT 24
Peak memory 217224 kb
Host smart-3a280949-d453-44e1-8e2c-be5a5742ed7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259010992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1259010992 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.3538114717
Short name T343
Test name
Test status
Simulation time 51938655851 ps
CPU time 1592.51 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 06:20:52 PM PDT 24
Peak memory 400524 kb
Host smart-f17afd22-9cb4-4347-9afc-c292407ec1e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538114717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.3538114717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.865163236
Short name T1037
Test name
Test status
Simulation time 1849262426 ps
CPU time 147.14 seconds
Started Jun 30 05:54:19 PM PDT 24
Finished Jun 30 05:56:47 PM PDT 24
Peak memory 233424 kb
Host smart-c35642d6-3a47-489c-942e-5a7061e542ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865163236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.865163236 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.3698850139
Short name T792
Test name
Test status
Simulation time 9577231069 ps
CPU time 42.17 seconds
Started Jun 30 05:54:18 PM PDT 24
Finished Jun 30 05:55:00 PM PDT 24
Peak memory 217520 kb
Host smart-91559461-7263-4ace-a8e3-7ab2214597f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698850139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3698850139 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.291148376
Short name T72
Test name
Test status
Simulation time 4469827742 ps
CPU time 84.92 seconds
Started Jun 30 05:54:25 PM PDT 24
Finished Jun 30 05:55:51 PM PDT 24
Peak memory 227912 kb
Host smart-0b3f2a7f-9876-43e6-8021-9750f851173f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=291148376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.291148376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.2672492148
Short name T554
Test name
Test status
Simulation time 1037313182 ps
CPU time 5.2 seconds
Started Jun 30 05:54:27 PM PDT 24
Finished Jun 30 05:54:33 PM PDT 24
Peak memory 216212 kb
Host smart-17d1960d-07e4-4c62-b7c0-7231b59eadb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672492148 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.2672492148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1581983484
Short name T676
Test name
Test status
Simulation time 592660532 ps
CPU time 4.63 seconds
Started Jun 30 05:54:25 PM PDT 24
Finished Jun 30 05:54:30 PM PDT 24
Peak memory 216132 kb
Host smart-04fc0c3b-42eb-40d2-95d6-abd6daba980d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581983484 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1581983484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1590380836
Short name T518
Test name
Test status
Simulation time 427973236820 ps
CPU time 1713.15 seconds
Started Jun 30 05:54:28 PM PDT 24
Finished Jun 30 06:23:02 PM PDT 24
Peak memory 388232 kb
Host smart-d3f61305-ffa7-493f-9044-331c7ed94ba0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1590380836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1590380836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2773752693
Short name T89
Test name
Test status
Simulation time 378191669105 ps
CPU time 1977.43 seconds
Started Jun 30 05:54:26 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 371372 kb
Host smart-351a9dfa-c99d-4834-bee5-d4ae2e359ce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2773752693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2773752693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.4229319684
Short name T208
Test name
Test status
Simulation time 56244639997 ps
CPU time 1162.52 seconds
Started Jun 30 05:54:25 PM PDT 24
Finished Jun 30 06:13:48 PM PDT 24
Peak memory 333108 kb
Host smart-28d31ab0-6e7a-4964-ad11-0b4a1e7edaf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4229319684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.4229319684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2404657875
Short name T15
Test name
Test status
Simulation time 173535043402 ps
CPU time 939.56 seconds
Started Jun 30 05:54:29 PM PDT 24
Finished Jun 30 06:10:09 PM PDT 24
Peak memory 292756 kb
Host smart-00597538-e8e1-42b0-af09-86e494306a39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2404657875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2404657875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.975631738
Short name T882
Test name
Test status
Simulation time 53400287335 ps
CPU time 4072.8 seconds
Started Jun 30 05:54:25 PM PDT 24
Finished Jun 30 07:02:19 PM PDT 24
Peak memory 658056 kb
Host smart-1616c4ff-2a53-4de0-bf35-30b72848d4ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=975631738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.975631738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.2609591368
Short name T156
Test name
Test status
Simulation time 312631122820 ps
CPU time 3505.69 seconds
Started Jun 30 05:54:26 PM PDT 24
Finished Jun 30 06:52:52 PM PDT 24
Peak memory 572256 kb
Host smart-a92d441c-ab94-4217-b0f2-ed4082a835e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2609591368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2609591368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2661699992
Short name T1062
Test name
Test status
Simulation time 50297014 ps
CPU time 0.81 seconds
Started Jun 30 05:54:36 PM PDT 24
Finished Jun 30 05:54:37 PM PDT 24
Peak memory 205828 kb
Host smart-e9925250-302c-45a2-9909-0c83665eb918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661699992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2661699992 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.2385403992
Short name T681
Test name
Test status
Simulation time 15834739988 ps
CPU time 97.14 seconds
Started Jun 30 05:54:39 PM PDT 24
Finished Jun 30 05:56:16 PM PDT 24
Peak memory 229444 kb
Host smart-23b414e0-0114-4502-b88d-3e6f8454e080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385403992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2385403992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.2044738652
Short name T289
Test name
Test status
Simulation time 31958348746 ps
CPU time 622.01 seconds
Started Jun 30 05:54:32 PM PDT 24
Finished Jun 30 06:04:55 PM PDT 24
Peak memory 231824 kb
Host smart-9d846ee4-72d9-48bf-ace2-d50867e350be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044738652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2044738652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.3815338740
Short name T420
Test name
Test status
Simulation time 608219911 ps
CPU time 20.4 seconds
Started Jun 30 05:54:36 PM PDT 24
Finished Jun 30 05:54:57 PM PDT 24
Peak memory 221596 kb
Host smart-9fae24bb-438a-48c3-930a-52adb7b08bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815338740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3815338740 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2189385296
Short name T561
Test name
Test status
Simulation time 45569136866 ps
CPU time 415.54 seconds
Started Jun 30 05:54:36 PM PDT 24
Finished Jun 30 06:01:32 PM PDT 24
Peak memory 257088 kb
Host smart-68edc4e6-4981-4c82-8bff-3d04970e9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189385296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2189385296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.609061726
Short name T440
Test name
Test status
Simulation time 411222316 ps
CPU time 9.17 seconds
Started Jun 30 05:54:39 PM PDT 24
Finished Jun 30 05:54:48 PM PDT 24
Peak memory 221776 kb
Host smart-e4ad6ef7-6caf-4555-a44d-e3a3adc567a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609061726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.609061726 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.2544942458
Short name T198
Test name
Test status
Simulation time 49896228655 ps
CPU time 1333.16 seconds
Started Jun 30 05:54:32 PM PDT 24
Finished Jun 30 06:16:46 PM PDT 24
Peak memory 352696 kb
Host smart-128534af-3b30-4692-8384-fc95fa8e64f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544942458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.2544942458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.1913216438
Short name T600
Test name
Test status
Simulation time 1271691569 ps
CPU time 26.99 seconds
Started Jun 30 05:54:32 PM PDT 24
Finished Jun 30 05:54:59 PM PDT 24
Peak memory 222852 kb
Host smart-833e704a-9667-4f50-9368-fd10ce3a9dc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913216438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1913216438 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.104788521
Short name T649
Test name
Test status
Simulation time 840369457 ps
CPU time 35.9 seconds
Started Jun 30 05:54:33 PM PDT 24
Finished Jun 30 05:55:09 PM PDT 24
Peak memory 218776 kb
Host smart-e91a175b-cd4f-4415-959d-f4af849cdf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104788521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.104788521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.1421163739
Short name T949
Test name
Test status
Simulation time 1078326104 ps
CPU time 54.11 seconds
Started Jun 30 05:54:37 PM PDT 24
Finished Jun 30 05:55:32 PM PDT 24
Peak memory 237324 kb
Host smart-99168167-8a05-419f-8932-f61dbb6597ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1421163739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1421163739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.41169338
Short name T1036
Test name
Test status
Simulation time 258582928 ps
CPU time 4.12 seconds
Started Jun 30 05:54:33 PM PDT 24
Finished Jun 30 05:54:37 PM PDT 24
Peak memory 216104 kb
Host smart-b052700b-d575-49e2-9422-6b7af2c995f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41169338 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.kmac_test_vectors_kmac.41169338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.2070370891
Short name T503
Test name
Test status
Simulation time 641879565 ps
CPU time 4.26 seconds
Started Jun 30 05:54:36 PM PDT 24
Finished Jun 30 05:54:41 PM PDT 24
Peak memory 216240 kb
Host smart-a2e70bfc-5ebb-4cf9-ad5b-181a69fd1002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070370891 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.2070370891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.119787281
Short name T328
Test name
Test status
Simulation time 19687590224 ps
CPU time 1656.19 seconds
Started Jun 30 05:54:32 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 394224 kb
Host smart-7b4cb3d1-ae95-4e1e-b9d4-e810d281ecf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=119787281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.119787281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.2292427162
Short name T463
Test name
Test status
Simulation time 166440640811 ps
CPU time 1765.1 seconds
Started Jun 30 05:54:31 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 377268 kb
Host smart-536c7ac7-672e-4e82-8521-bc9fe923ec40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2292427162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.2292427162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.1130904582
Short name T746
Test name
Test status
Simulation time 13983696996 ps
CPU time 1111.57 seconds
Started Jun 30 05:54:32 PM PDT 24
Finished Jun 30 06:13:05 PM PDT 24
Peak memory 330544 kb
Host smart-4bbb402c-8fab-49a2-8c30-6194a31ed4c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1130904582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1130904582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.418313884
Short name T202
Test name
Test status
Simulation time 40286248388 ps
CPU time 859.74 seconds
Started Jun 30 05:54:33 PM PDT 24
Finished Jun 30 06:08:53 PM PDT 24
Peak memory 299096 kb
Host smart-c13f3e5c-a2fb-4c9f-a58b-070d67b9ad82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=418313884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.418313884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.53193179
Short name T743
Test name
Test status
Simulation time 295798807973 ps
CPU time 5019.03 seconds
Started Jun 30 05:54:33 PM PDT 24
Finished Jun 30 07:18:13 PM PDT 24
Peak memory 652852 kb
Host smart-615bc1cb-8fb4-4921-8f7e-903164f1c38a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=53193179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.53193179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.4274140678
Short name T1065
Test name
Test status
Simulation time 151202544221 ps
CPU time 3762.71 seconds
Started Jun 30 05:54:35 PM PDT 24
Finished Jun 30 06:57:18 PM PDT 24
Peak memory 560620 kb
Host smart-e7377b52-6c86-44e9-92bc-ec2ce1f4d6aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4274140678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.4274140678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.3739267187
Short name T282
Test name
Test status
Simulation time 13352788 ps
CPU time 0.81 seconds
Started Jun 30 05:54:51 PM PDT 24
Finished Jun 30 05:54:53 PM PDT 24
Peak memory 205612 kb
Host smart-c18d77ba-2bfd-4f42-a78b-681e0e069160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739267187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3739267187 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.602454797
Short name T62
Test name
Test status
Simulation time 6233521033 ps
CPU time 66.95 seconds
Started Jun 30 05:54:46 PM PDT 24
Finished Jun 30 05:55:54 PM PDT 24
Peak memory 226076 kb
Host smart-0f8706c4-ed04-4003-8cdc-25b8ad70b186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602454797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.602454797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.2508333238
Short name T356
Test name
Test status
Simulation time 21922566595 ps
CPU time 673.67 seconds
Started Jun 30 05:54:44 PM PDT 24
Finished Jun 30 06:05:58 PM PDT 24
Peak memory 232548 kb
Host smart-7c889bfe-a1bf-4ee3-ae0c-f5ebc3b95415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508333238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2508333238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.2522146214
Short name T539
Test name
Test status
Simulation time 10284097366 ps
CPU time 157.75 seconds
Started Jun 30 05:54:44 PM PDT 24
Finished Jun 30 05:57:23 PM PDT 24
Peak memory 235196 kb
Host smart-e5673672-e940-402c-8551-f65295271e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522146214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2522146214 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.2668742465
Short name T472
Test name
Test status
Simulation time 10330690485 ps
CPU time 281.43 seconds
Started Jun 30 05:54:51 PM PDT 24
Finished Jun 30 05:59:33 PM PDT 24
Peak memory 255892 kb
Host smart-b2c71c07-2933-49ae-9e52-4f88a65e0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668742465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2668742465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.1117585761
Short name T360
Test name
Test status
Simulation time 561882440 ps
CPU time 3.12 seconds
Started Jun 30 05:54:51 PM PDT 24
Finished Jun 30 05:54:55 PM PDT 24
Peak memory 207756 kb
Host smart-0151d1bb-9325-4177-aa6a-0676118b3607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117585761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1117585761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.1847072314
Short name T86
Test name
Test status
Simulation time 42016986 ps
CPU time 1.31 seconds
Started Jun 30 05:54:51 PM PDT 24
Finished Jun 30 05:54:53 PM PDT 24
Peak memory 216068 kb
Host smart-a0b69ac5-ab1d-4a82-b831-b873e797a655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847072314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1847072314 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.3872491024
Short name T500
Test name
Test status
Simulation time 12273029230 ps
CPU time 945.41 seconds
Started Jun 30 05:54:44 PM PDT 24
Finished Jun 30 06:10:30 PM PDT 24
Peak memory 320192 kb
Host smart-5715b982-db29-4b69-a6f3-5d4bfbf226e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872491024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.3872491024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.1218900495
Short name T588
Test name
Test status
Simulation time 2030006848 ps
CPU time 156.27 seconds
Started Jun 30 05:54:43 PM PDT 24
Finished Jun 30 05:57:20 PM PDT 24
Peak memory 233196 kb
Host smart-303c3c35-6063-496a-ad03-474ae3d5b4ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218900495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1218900495 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1648306473
Short name T1001
Test name
Test status
Simulation time 6286967035 ps
CPU time 54.22 seconds
Started Jun 30 05:54:37 PM PDT 24
Finished Jun 30 05:55:31 PM PDT 24
Peak memory 220124 kb
Host smart-511fe305-005f-4438-b468-3169f68bc39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648306473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1648306473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.752820647
Short name T75
Test name
Test status
Simulation time 35335806033 ps
CPU time 810.66 seconds
Started Jun 30 05:54:51 PM PDT 24
Finished Jun 30 06:08:22 PM PDT 24
Peak memory 332960 kb
Host smart-be1be0a1-4fbb-4f23-a2b7-5ff8070f243a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=752820647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.752820647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.3978289135
Short name T945
Test name
Test status
Simulation time 198753149 ps
CPU time 4.5 seconds
Started Jun 30 05:54:44 PM PDT 24
Finished Jun 30 05:54:48 PM PDT 24
Peak memory 216132 kb
Host smart-93402c83-9799-4c14-bc60-bea849034323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978289135 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.3978289135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.33613104
Short name T308
Test name
Test status
Simulation time 71942487 ps
CPU time 4.02 seconds
Started Jun 30 05:54:44 PM PDT 24
Finished Jun 30 05:54:49 PM PDT 24
Peak memory 216100 kb
Host smart-a43fb6c7-ff31-4bb0-84c4-11a1fcaf5bf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33613104 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.kmac_test_vectors_kmac_xof.33613104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.1316461993
Short name T939
Test name
Test status
Simulation time 38625949207 ps
CPU time 1527.36 seconds
Started Jun 30 05:54:44 PM PDT 24
Finished Jun 30 06:20:12 PM PDT 24
Peak memory 379484 kb
Host smart-79deb75a-9c40-4480-a7a7-766c4e8794cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1316461993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.1316461993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.213088856
Short name T579
Test name
Test status
Simulation time 61833650353 ps
CPU time 1669.42 seconds
Started Jun 30 05:54:44 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 378348 kb
Host smart-ba142949-3e6e-4042-9e96-fa98809238ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=213088856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.213088856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.3312451941
Short name T335
Test name
Test status
Simulation time 213881814676 ps
CPU time 1349.4 seconds
Started Jun 30 05:54:45 PM PDT 24
Finished Jun 30 06:17:14 PM PDT 24
Peak memory 335640 kb
Host smart-bbfffc68-0ffd-452c-84ac-9338d2edec60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3312451941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.3312451941 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.2939568296
Short name T760
Test name
Test status
Simulation time 44095586286 ps
CPU time 893.78 seconds
Started Jun 30 05:54:46 PM PDT 24
Finished Jun 30 06:09:40 PM PDT 24
Peak memory 297020 kb
Host smart-2697172e-2ddd-4756-9c6e-a81ec8058055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2939568296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2939568296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.3047569824
Short name T1039
Test name
Test status
Simulation time 52024244051 ps
CPU time 3985.97 seconds
Started Jun 30 05:54:46 PM PDT 24
Finished Jun 30 07:01:13 PM PDT 24
Peak memory 653068 kb
Host smart-eee5470d-c9af-40fa-8fae-ead06dfa8095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3047569824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3047569824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.378227111
Short name T286
Test name
Test status
Simulation time 151355104530 ps
CPU time 3732.51 seconds
Started Jun 30 05:54:45 PM PDT 24
Finished Jun 30 06:56:58 PM PDT 24
Peak memory 561136 kb
Host smart-0e94c3a1-2eb5-47a5-b104-3f8a55e581b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=378227111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.378227111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.3791128461
Short name T987
Test name
Test status
Simulation time 22046304 ps
CPU time 0.75 seconds
Started Jun 30 05:55:05 PM PDT 24
Finished Jun 30 05:55:06 PM PDT 24
Peak memory 205364 kb
Host smart-2b1c8216-10bf-4510-ac88-e7f1744dc7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791128461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3791128461 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_burst_write.3169794474
Short name T1075
Test name
Test status
Simulation time 3292415221 ps
CPU time 68.76 seconds
Started Jun 30 05:54:53 PM PDT 24
Finished Jun 30 05:56:02 PM PDT 24
Peak memory 225948 kb
Host smart-6105704e-5c2e-42fd-9818-b51e18595704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169794474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3169794474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.362748835
Short name T485
Test name
Test status
Simulation time 7820647868 ps
CPU time 113.59 seconds
Started Jun 30 05:54:58 PM PDT 24
Finished Jun 30 05:56:52 PM PDT 24
Peak memory 229720 kb
Host smart-9ab00d8f-eea4-4b1c-a506-2db880bf4f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362748835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.362748835 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_key_error.1633489564
Short name T438
Test name
Test status
Simulation time 2622394705 ps
CPU time 5.35 seconds
Started Jun 30 05:55:05 PM PDT 24
Finished Jun 30 05:55:11 PM PDT 24
Peak memory 207704 kb
Host smart-efb97414-28e8-45f5-a9a2-526993fbee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633489564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1633489564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.1793970072
Short name T724
Test name
Test status
Simulation time 39894982 ps
CPU time 1.52 seconds
Started Jun 30 05:54:57 PM PDT 24
Finished Jun 30 05:54:59 PM PDT 24
Peak memory 218184 kb
Host smart-010c5747-3191-4f20-a7d4-c83dc2ec332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793970072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1793970072 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3060795875
Short name T423
Test name
Test status
Simulation time 46843884366 ps
CPU time 1225.72 seconds
Started Jun 30 05:54:52 PM PDT 24
Finished Jun 30 06:15:19 PM PDT 24
Peak memory 354904 kb
Host smart-585274e4-7c73-4da4-a262-23021a856194
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060795875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3060795875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3720106402
Short name T1041
Test name
Test status
Simulation time 36951940854 ps
CPU time 236.93 seconds
Started Jun 30 05:54:52 PM PDT 24
Finished Jun 30 05:58:49 PM PDT 24
Peak memory 240748 kb
Host smart-08dc6e09-afae-4850-ab01-56d69e454651
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720106402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3720106402 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.1478176097
Short name T374
Test name
Test status
Simulation time 18744595642 ps
CPU time 36.76 seconds
Started Jun 30 05:54:50 PM PDT 24
Finished Jun 30 05:55:27 PM PDT 24
Peak memory 221068 kb
Host smart-756e90f1-5592-4919-9b0f-d0b9feb85dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478176097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1478176097 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.1137107060
Short name T207
Test name
Test status
Simulation time 2091141029 ps
CPU time 31.26 seconds
Started Jun 30 05:54:58 PM PDT 24
Finished Jun 30 05:55:29 PM PDT 24
Peak memory 224272 kb
Host smart-fdc36006-3a38-47d4-8f6d-75db77a2fbbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1137107060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1137107060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3608549846
Short name T435
Test name
Test status
Simulation time 301020325 ps
CPU time 4.53 seconds
Started Jun 30 05:54:51 PM PDT 24
Finished Jun 30 05:54:55 PM PDT 24
Peak memory 216076 kb
Host smart-aa053b9b-86e1-48b2-b804-f748d19f1827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608549846 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3608549846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.3396735980
Short name T418
Test name
Test status
Simulation time 70321712 ps
CPU time 3.78 seconds
Started Jun 30 05:54:52 PM PDT 24
Finished Jun 30 05:54:56 PM PDT 24
Peak memory 216208 kb
Host smart-d4f40c48-b25b-4df0-9253-6654cc6a9800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396735980 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.3396735980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1909924465
Short name T582
Test name
Test status
Simulation time 286392950482 ps
CPU time 1724.37 seconds
Started Jun 30 05:54:50 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 374152 kb
Host smart-cc2137d4-9efa-4019-ac27-a63e1ccf64b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1909924465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1909924465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.307798067
Short name T140
Test name
Test status
Simulation time 83551390155 ps
CPU time 1786.94 seconds
Started Jun 30 05:54:52 PM PDT 24
Finished Jun 30 06:24:39 PM PDT 24
Peak memory 378008 kb
Host smart-2bac8582-6f38-423e-8db4-2ecc0d343125
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=307798067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.307798067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.203128791
Short name T721
Test name
Test status
Simulation time 13961159361 ps
CPU time 1239.49 seconds
Started Jun 30 05:54:50 PM PDT 24
Finished Jun 30 06:15:30 PM PDT 24
Peak memory 341980 kb
Host smart-dbb13cc6-db60-4277-867a-0899ff713251
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=203128791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.203128791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.2172893893
Short name T668
Test name
Test status
Simulation time 39119034847 ps
CPU time 702.05 seconds
Started Jun 30 05:54:50 PM PDT 24
Finished Jun 30 06:06:32 PM PDT 24
Peak memory 285388 kb
Host smart-3425db39-f6cb-44dc-8ee7-3f9524c7a544
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2172893893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2172893893 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3866714886
Short name T271
Test name
Test status
Simulation time 392884251851 ps
CPU time 4291.5 seconds
Started Jun 30 05:54:50 PM PDT 24
Finished Jun 30 07:06:22 PM PDT 24
Peak memory 654792 kb
Host smart-c0f6f4eb-fb3b-49e1-81c9-a105834ac8a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3866714886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3866714886 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.3578995554
Short name T555
Test name
Test status
Simulation time 171733838549 ps
CPU time 3216.7 seconds
Started Jun 30 05:54:51 PM PDT 24
Finished Jun 30 06:48:29 PM PDT 24
Peak memory 553644 kb
Host smart-05f3b88c-8fb8-495a-bd6f-b376026d9874
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3578995554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.3578995554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.4094706170
Short name T950
Test name
Test status
Simulation time 37699720 ps
CPU time 0.75 seconds
Started Jun 30 05:55:03 PM PDT 24
Finished Jun 30 05:55:04 PM PDT 24
Peak memory 205624 kb
Host smart-a67c03f1-ee44-44d2-bd8a-57a48815f607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094706170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.4094706170 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.3947902766
Short name T551
Test name
Test status
Simulation time 8101905781 ps
CPU time 82.45 seconds
Started Jun 30 05:55:05 PM PDT 24
Finished Jun 30 05:56:28 PM PDT 24
Peak memory 227612 kb
Host smart-5a937fcf-7113-494c-a8ea-1c83e801b379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947902766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3947902766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.779884670
Short name T984
Test name
Test status
Simulation time 45771381234 ps
CPU time 662.15 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 06:06:08 PM PDT 24
Peak memory 232152 kb
Host smart-906de6ff-0588-4843-b21c-4751a9006257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779884670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.779884670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.1759013142
Short name T597
Test name
Test status
Simulation time 27148271864 ps
CPU time 92.52 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 05:56:38 PM PDT 24
Peak memory 227976 kb
Host smart-92f3fa98-12fa-425b-98d8-e622b85587d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759013142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1759013142 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.336193196
Short name T478
Test name
Test status
Simulation time 1553193833 ps
CPU time 60.66 seconds
Started Jun 30 05:55:03 PM PDT 24
Finished Jun 30 05:56:04 PM PDT 24
Peak memory 240744 kb
Host smart-3b92cd7e-7119-4360-9106-1b8ac0278cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336193196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.336193196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.2283840022
Short name T707
Test name
Test status
Simulation time 3162604508 ps
CPU time 4.52 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 05:55:10 PM PDT 24
Peak memory 207876 kb
Host smart-46307b94-6f77-4044-ab0c-59a3b2a0dc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283840022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2283840022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.3106256675
Short name T4
Test name
Test status
Simulation time 701021053 ps
CPU time 5.81 seconds
Started Jun 30 05:55:03 PM PDT 24
Finished Jun 30 05:55:10 PM PDT 24
Peak memory 221320 kb
Host smart-c067638e-6906-40c6-9c5d-74f8f383b83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106256675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3106256675 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.3720857300
Short name T133
Test name
Test status
Simulation time 9387003302 ps
CPU time 782.1 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 06:08:08 PM PDT 24
Peak memory 305796 kb
Host smart-7c734de8-9858-47f3-9f6d-9be03151adb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720857300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.3720857300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.1402044429
Short name T591
Test name
Test status
Simulation time 7272221539 ps
CPU time 304.25 seconds
Started Jun 30 05:55:05 PM PDT 24
Finished Jun 30 06:00:10 PM PDT 24
Peak memory 245036 kb
Host smart-668e33ae-340d-4d9d-82f1-3aee7aa7d17e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402044429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1402044429 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1469864441
Short name T911
Test name
Test status
Simulation time 2837430627 ps
CPU time 38.47 seconds
Started Jun 30 05:54:56 PM PDT 24
Finished Jun 30 05:55:35 PM PDT 24
Peak memory 220016 kb
Host smart-af3091ce-bd36-4aa8-97d5-be0469664a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469864441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1469864441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3190886884
Short name T229
Test name
Test status
Simulation time 197342215258 ps
CPU time 1239.21 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 06:15:44 PM PDT 24
Peak memory 369708 kb
Host smart-70e8975c-0e23-4c36-af88-915011a0547e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3190886884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3190886884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.4192487372
Short name T203
Test name
Test status
Simulation time 353913919 ps
CPU time 4.72 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 05:55:09 PM PDT 24
Peak memory 209252 kb
Host smart-611782a4-981a-4d71-b5fd-f3da46bd1961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192487372 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.4192487372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.353963737
Short name T226
Test name
Test status
Simulation time 250814291 ps
CPU time 5 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 05:55:09 PM PDT 24
Peak memory 216068 kb
Host smart-ce563058-b27f-4f39-afcc-2abfe27b8083
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353963737 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.353963737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3314025473
Short name T336
Test name
Test status
Simulation time 63934721066 ps
CPU time 1754.05 seconds
Started Jun 30 05:54:57 PM PDT 24
Finished Jun 30 06:24:12 PM PDT 24
Peak memory 387188 kb
Host smart-feaa8abb-5db4-478e-a728-b994b7a9e245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3314025473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3314025473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.1080903834
Short name T510
Test name
Test status
Simulation time 93726982368 ps
CPU time 1853.64 seconds
Started Jun 30 05:54:57 PM PDT 24
Finished Jun 30 06:25:52 PM PDT 24
Peak memory 372172 kb
Host smart-59695ef3-0b34-424c-aa1c-c4b2691cf3b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1080903834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1080903834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.2440378229
Short name T618
Test name
Test status
Simulation time 60322901372 ps
CPU time 1089.69 seconds
Started Jun 30 05:55:04 PM PDT 24
Finished Jun 30 06:13:15 PM PDT 24
Peak memory 328228 kb
Host smart-875b7309-fee6-4d9f-bb02-536e91bf66fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2440378229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.2440378229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.2755816381
Short name T218
Test name
Test status
Simulation time 9707477497 ps
CPU time 794.97 seconds
Started Jun 30 05:55:03 PM PDT 24
Finished Jun 30 06:08:19 PM PDT 24
Peak memory 293376 kb
Host smart-b808eb7f-a5c0-4239-8bef-e2ee5009409c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2755816381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.2755816381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.1524790194
Short name T574
Test name
Test status
Simulation time 186136117617 ps
CPU time 3326.08 seconds
Started Jun 30 05:55:03 PM PDT 24
Finished Jun 30 06:50:30 PM PDT 24
Peak memory 553140 kb
Host smart-7878c5ca-9e52-447a-afa8-eac229ae242e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1524790194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.1524790194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.3651594332
Short name T525
Test name
Test status
Simulation time 23997380 ps
CPU time 0.79 seconds
Started Jun 30 05:55:18 PM PDT 24
Finished Jun 30 05:55:20 PM PDT 24
Peak memory 205636 kb
Host smart-eab32bac-378b-4081-bb53-a6c94a80bd2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651594332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3651594332 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.2570808466
Short name T1027
Test name
Test status
Simulation time 30560242355 ps
CPU time 153.18 seconds
Started Jun 30 05:55:11 PM PDT 24
Finished Jun 30 05:57:46 PM PDT 24
Peak memory 235924 kb
Host smart-2868cd5a-85b7-4982-85ca-d02dc84912a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570808466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2570808466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.2270485598
Short name T322
Test name
Test status
Simulation time 3403857416 ps
CPU time 278.97 seconds
Started Jun 30 05:55:11 PM PDT 24
Finished Jun 30 05:59:51 PM PDT 24
Peak memory 226508 kb
Host smart-e9a0c236-40fc-4585-ac61-cb75e1647228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270485598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2270485598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.2945625114
Short name T210
Test name
Test status
Simulation time 14290239998 ps
CPU time 289.01 seconds
Started Jun 30 05:55:11 PM PDT 24
Finished Jun 30 06:00:01 PM PDT 24
Peak memory 242152 kb
Host smart-3ef7b876-d4c8-4fa8-bd02-eb05ed1585f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945625114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2945625114 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.3054815292
Short name T535
Test name
Test status
Simulation time 3779442988 ps
CPU time 272.47 seconds
Started Jun 30 05:55:10 PM PDT 24
Finished Jun 30 05:59:43 PM PDT 24
Peak memory 257216 kb
Host smart-98eb2641-b30f-4825-9a34-3cffd50e755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054815292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3054815292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.2676738233
Short name T358
Test name
Test status
Simulation time 356920917 ps
CPU time 2.5 seconds
Started Jun 30 05:55:09 PM PDT 24
Finished Jun 30 05:55:12 PM PDT 24
Peak memory 215944 kb
Host smart-f1113ecd-7bb3-44f0-93a2-8ba3d96d5302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676738233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2676738233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.1258810380
Short name T826
Test name
Test status
Simulation time 41754649 ps
CPU time 1.2 seconds
Started Jun 30 05:55:10 PM PDT 24
Finished Jun 30 05:55:11 PM PDT 24
Peak memory 216068 kb
Host smart-2a606241-42c1-4844-a1c4-ff9a4e4877f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258810380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1258810380 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.1174305609
Short name T669
Test name
Test status
Simulation time 45367124771 ps
CPU time 807.85 seconds
Started Jun 30 05:55:10 PM PDT 24
Finished Jun 30 06:08:39 PM PDT 24
Peak memory 308784 kb
Host smart-d229cf12-d674-4687-a20b-bc4bd15018bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174305609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.1174305609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.538021029
Short name T13
Test name
Test status
Simulation time 4946717916 ps
CPU time 185.96 seconds
Started Jun 30 05:55:10 PM PDT 24
Finished Jun 30 05:58:16 PM PDT 24
Peak memory 240760 kb
Host smart-061da4ad-69e0-4776-8d29-de1c57087fcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538021029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.538021029 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2166695976
Short name T656
Test name
Test status
Simulation time 1074252989 ps
CPU time 53.26 seconds
Started Jun 30 05:55:12 PM PDT 24
Finished Jun 30 05:56:06 PM PDT 24
Peak memory 219704 kb
Host smart-dabf37cc-6773-4258-b9e5-950a417cf740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166695976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2166695976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.1342848236
Short name T745
Test name
Test status
Simulation time 321335959052 ps
CPU time 1673.67 seconds
Started Jun 30 05:55:18 PM PDT 24
Finished Jun 30 06:23:12 PM PDT 24
Peak memory 397492 kb
Host smart-59b11574-0dd3-4b2c-bb13-c8b150046a1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1342848236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1342848236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.332118921
Short name T753
Test name
Test status
Simulation time 567937755 ps
CPU time 4.31 seconds
Started Jun 30 05:55:10 PM PDT 24
Finished Jun 30 05:55:15 PM PDT 24
Peak memory 216104 kb
Host smart-23800199-87ed-43d5-ac3f-4c9070e21d16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332118921 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.kmac_test_vectors_kmac.332118921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.2374455724
Short name T848
Test name
Test status
Simulation time 153525993 ps
CPU time 3.93 seconds
Started Jun 30 05:55:11 PM PDT 24
Finished Jun 30 05:55:16 PM PDT 24
Peak memory 216124 kb
Host smart-84d21da3-324c-4d13-9fea-940f7fde3a8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374455724 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.2374455724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.3789140483
Short name T897
Test name
Test status
Simulation time 398954208647 ps
CPU time 1944.01 seconds
Started Jun 30 05:55:12 PM PDT 24
Finished Jun 30 06:27:37 PM PDT 24
Peak memory 387336 kb
Host smart-c24681a3-0711-4f2a-8408-7b6ac3d99925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3789140483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.3789140483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.3658916213
Short name T948
Test name
Test status
Simulation time 70486672102 ps
CPU time 1486.58 seconds
Started Jun 30 05:55:11 PM PDT 24
Finished Jun 30 06:19:59 PM PDT 24
Peak memory 372848 kb
Host smart-f2c2cb9d-3587-4bca-9bdc-bb4be9e60036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3658916213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.3658916213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.1414770891
Short name T667
Test name
Test status
Simulation time 58425277331 ps
CPU time 1209.26 seconds
Started Jun 30 05:55:10 PM PDT 24
Finished Jun 30 06:15:20 PM PDT 24
Peak memory 343092 kb
Host smart-3d1e540d-dd51-4974-b90b-9ee7965952a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1414770891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.1414770891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.4172226797
Short name T772
Test name
Test status
Simulation time 38066086222 ps
CPU time 768.14 seconds
Started Jun 30 05:55:09 PM PDT 24
Finished Jun 30 06:07:58 PM PDT 24
Peak memory 295620 kb
Host smart-0bf9550b-8591-4b0f-b8bb-670c8f2378c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4172226797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.4172226797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.2714987111
Short name T250
Test name
Test status
Simulation time 211708684864 ps
CPU time 3834 seconds
Started Jun 30 05:55:13 PM PDT 24
Finished Jun 30 06:59:08 PM PDT 24
Peak memory 650664 kb
Host smart-08c9f59c-dfa5-4e5e-81ef-4c7e73799a44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2714987111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2714987111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.2778643209
Short name T187
Test name
Test status
Simulation time 171318136001 ps
CPU time 3471.59 seconds
Started Jun 30 05:55:11 PM PDT 24
Finished Jun 30 06:53:04 PM PDT 24
Peak memory 552356 kb
Host smart-450945e8-42db-43dc-9727-843c728f5381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2778643209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.2778643209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.179884733
Short name T677
Test name
Test status
Simulation time 15400120 ps
CPU time 0.78 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 05:55:25 PM PDT 24
Peak memory 205644 kb
Host smart-b839ef2a-82e6-46ea-924e-1ccd9170982d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179884733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.179884733 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.343153293
Short name T110
Test name
Test status
Simulation time 10545461187 ps
CPU time 193.01 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 05:58:38 PM PDT 24
Peak memory 238216 kb
Host smart-7c57cc54-7a43-476e-b472-1318c5008a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343153293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.343153293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.2595684923
Short name T606
Test name
Test status
Simulation time 3524574451 ps
CPU time 45.08 seconds
Started Jun 30 05:55:20 PM PDT 24
Finished Jun 30 05:56:05 PM PDT 24
Peak memory 227712 kb
Host smart-4ea54ace-40f9-435a-a072-09e3cbfa5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595684923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2595684923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.2681843592
Short name T131
Test name
Test status
Simulation time 19774605027 ps
CPU time 202.17 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 05:58:47 PM PDT 24
Peak memory 240156 kb
Host smart-248615fa-c98b-4e2e-b541-89bafa548c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681843592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2681843592 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.2167975365
Short name T492
Test name
Test status
Simulation time 14745971393 ps
CPU time 227.03 seconds
Started Jun 30 05:55:23 PM PDT 24
Finished Jun 30 05:59:11 PM PDT 24
Peak memory 257064 kb
Host smart-c1dedc46-0567-413c-949d-a3b480282337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167975365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2167975365 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.1959426502
Short name T20
Test name
Test status
Simulation time 5235680973 ps
CPU time 8.18 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 05:55:33 PM PDT 24
Peak memory 207988 kb
Host smart-dbda633b-8e2e-4204-9f51-c64bc1a29902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959426502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1959426502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.721504277
Short name T422
Test name
Test status
Simulation time 92302086 ps
CPU time 1.38 seconds
Started Jun 30 05:55:25 PM PDT 24
Finished Jun 30 05:55:27 PM PDT 24
Peak memory 216176 kb
Host smart-57f7b6f8-3217-4ffd-9310-b33c04bd8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721504277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.721504277 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.2107502502
Short name T969
Test name
Test status
Simulation time 10938595751 ps
CPU time 951.36 seconds
Started Jun 30 05:55:16 PM PDT 24
Finished Jun 30 06:11:08 PM PDT 24
Peak memory 321508 kb
Host smart-66395c16-f4ed-498c-ad05-2d2f85556f7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107502502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.2107502502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.2986172824
Short name T761
Test name
Test status
Simulation time 3420168608 ps
CPU time 37.2 seconds
Started Jun 30 05:55:17 PM PDT 24
Finished Jun 30 05:55:55 PM PDT 24
Peak memory 224360 kb
Host smart-e6989681-95db-481e-a77e-9d9e79d398f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986172824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2986172824 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.1882558562
Short name T2
Test name
Test status
Simulation time 12902040670 ps
CPU time 57.99 seconds
Started Jun 30 05:55:18 PM PDT 24
Finished Jun 30 05:56:17 PM PDT 24
Peak memory 219816 kb
Host smart-ee07857a-fd4b-4232-9ee2-807880e57ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882558562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1882558562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.4123416288
Short name T708
Test name
Test status
Simulation time 30701485808 ps
CPU time 690.65 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 06:06:55 PM PDT 24
Peak memory 314536 kb
Host smart-6d44406d-7fcc-4cd2-811e-e52537a28e66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4123416288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.4123416288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.4286307314
Short name T470
Test name
Test status
Simulation time 248625229 ps
CPU time 4.32 seconds
Started Jun 30 05:55:19 PM PDT 24
Finished Jun 30 05:55:23 PM PDT 24
Peak memory 216148 kb
Host smart-2e7d9cd4-5c44-4af5-a573-a67dfe6421ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286307314 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.4286307314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.1454536700
Short name T309
Test name
Test status
Simulation time 701371194 ps
CPU time 4.86 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 05:55:29 PM PDT 24
Peak memory 216128 kb
Host smart-a6706059-3f9d-42c8-847d-1cabcf89f026
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454536700 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.1454536700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.4006516713
Short name T852
Test name
Test status
Simulation time 537185714695 ps
CPU time 1852.87 seconds
Started Jun 30 05:55:19 PM PDT 24
Finished Jun 30 06:26:13 PM PDT 24
Peak memory 389632 kb
Host smart-ff6cdc93-0a5c-4d8d-9e99-b96b7c074b8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4006516713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.4006516713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.688464487
Short name T389
Test name
Test status
Simulation time 60493226513 ps
CPU time 1715.9 seconds
Started Jun 30 05:55:19 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 366840 kb
Host smart-7ed287aa-a6d1-4c06-8ea6-c76547cd2c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=688464487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.688464487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.1314680112
Short name T573
Test name
Test status
Simulation time 124422761756 ps
CPU time 1197.2 seconds
Started Jun 30 05:55:19 PM PDT 24
Finished Jun 30 06:15:17 PM PDT 24
Peak memory 336892 kb
Host smart-32463d27-08ff-4e05-ba6b-05f5785b9d51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1314680112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1314680112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.647346300
Short name T889
Test name
Test status
Simulation time 84939603549 ps
CPU time 873.63 seconds
Started Jun 30 05:55:19 PM PDT 24
Finished Jun 30 06:09:53 PM PDT 24
Peak memory 292408 kb
Host smart-d0d5af2e-6978-453a-882d-e483a4e4cba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=647346300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.647346300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.2769712664
Short name T388
Test name
Test status
Simulation time 522503126651 ps
CPU time 5325.88 seconds
Started Jun 30 05:55:17 PM PDT 24
Finished Jun 30 07:24:04 PM PDT 24
Peak memory 648188 kb
Host smart-3368110b-7822-4b63-a3a3-1d8483efce5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2769712664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2769712664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.2814157567
Short name T940
Test name
Test status
Simulation time 43195575620 ps
CPU time 3530.7 seconds
Started Jun 30 05:55:18 PM PDT 24
Finished Jun 30 06:54:10 PM PDT 24
Peak memory 559572 kb
Host smart-97871fe7-e037-442f-9ac8-aaa1628af1be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2814157567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.2814157567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.2635571706
Short name T238
Test name
Test status
Simulation time 43127299 ps
CPU time 0.75 seconds
Started Jun 30 05:55:37 PM PDT 24
Finished Jun 30 05:55:38 PM PDT 24
Peak memory 205652 kb
Host smart-41b2dd22-93c2-431b-b494-20466c1d0a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635571706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2635571706 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1689318617
Short name T111
Test name
Test status
Simulation time 622524329 ps
CPU time 32.79 seconds
Started Jun 30 05:55:31 PM PDT 24
Finished Jun 30 05:56:04 PM PDT 24
Peak memory 224312 kb
Host smart-98683c70-7b65-49c6-b1d8-c925c8d3d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689318617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1689318617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1647455530
Short name T837
Test name
Test status
Simulation time 3321436719 ps
CPU time 268.38 seconds
Started Jun 30 05:55:32 PM PDT 24
Finished Jun 30 06:00:00 PM PDT 24
Peak memory 227256 kb
Host smart-3216fa8e-f609-40c9-94a0-0491d4e56e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647455530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1647455530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.4028046820
Short name T372
Test name
Test status
Simulation time 26285217745 ps
CPU time 244.38 seconds
Started Jun 30 05:55:37 PM PDT 24
Finished Jun 30 05:59:42 PM PDT 24
Peak memory 240320 kb
Host smart-391b8d61-51bb-4f06-9e0f-1a8f1eb70a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028046820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.4028046820 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.3788983526
Short name T762
Test name
Test status
Simulation time 7233252734 ps
CPU time 187.57 seconds
Started Jun 30 05:55:38 PM PDT 24
Finished Jun 30 05:58:46 PM PDT 24
Peak memory 249480 kb
Host smart-dff63336-cc79-41f7-a924-575ac45768ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788983526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3788983526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.838049574
Short name T728
Test name
Test status
Simulation time 1334399950 ps
CPU time 6.46 seconds
Started Jun 30 05:55:36 PM PDT 24
Finished Jun 30 05:55:42 PM PDT 24
Peak memory 207816 kb
Host smart-7a1f2169-dad0-47f2-861d-7f0c76eda02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838049574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.838049574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2300244434
Short name T375
Test name
Test status
Simulation time 75135953 ps
CPU time 1.26 seconds
Started Jun 30 05:55:37 PM PDT 24
Finished Jun 30 05:55:39 PM PDT 24
Peak memory 217248 kb
Host smart-a4e4b430-4a8e-4bc8-be0d-236f9e9efccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300244434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2300244434 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.4002661771
Short name T863
Test name
Test status
Simulation time 222140406512 ps
CPU time 1151.63 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 06:14:37 PM PDT 24
Peak memory 326824 kb
Host smart-9b724d61-9e56-49e1-b5d4-690361b14c32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002661771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.4002661771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.818668413
Short name T342
Test name
Test status
Simulation time 7303402265 ps
CPU time 154.09 seconds
Started Jun 30 05:55:30 PM PDT 24
Finished Jun 30 05:58:04 PM PDT 24
Peak memory 234416 kb
Host smart-dfaa2e37-8224-4d02-b0e5-6bddc20ea2ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818668413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.818668413 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1035450417
Short name T1052
Test name
Test status
Simulation time 2911547092 ps
CPU time 43.06 seconds
Started Jun 30 05:55:24 PM PDT 24
Finished Jun 30 05:56:08 PM PDT 24
Peak memory 216344 kb
Host smart-a4047fb0-d537-4fce-903d-a9c14e391453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035450417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1035450417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.1922995790
Short name T1048
Test name
Test status
Simulation time 5545949733 ps
CPU time 19.86 seconds
Started Jun 30 05:55:36 PM PDT 24
Finished Jun 30 05:55:57 PM PDT 24
Peak memory 224352 kb
Host smart-8ee668be-d898-49a0-ba69-cf701eda8b2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1922995790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1922995790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.3130333740
Short name T199
Test name
Test status
Simulation time 341020181 ps
CPU time 4.71 seconds
Started Jun 30 05:55:30 PM PDT 24
Finished Jun 30 05:55:35 PM PDT 24
Peak memory 216156 kb
Host smart-072c26de-a9d0-46d5-8113-af0332e5cb7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130333740 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.3130333740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.760852726
Short name T129
Test name
Test status
Simulation time 413439765 ps
CPU time 5.08 seconds
Started Jun 30 05:55:30 PM PDT 24
Finished Jun 30 05:55:36 PM PDT 24
Peak memory 216128 kb
Host smart-c6c59851-c624-414e-a5b3-5d4320566c30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760852726 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.kmac_test_vectors_kmac_xof.760852726 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.3805392622
Short name T519
Test name
Test status
Simulation time 19083828503 ps
CPU time 1658.68 seconds
Started Jun 30 05:55:32 PM PDT 24
Finished Jun 30 06:23:11 PM PDT 24
Peak memory 390264 kb
Host smart-e6149d0c-b9a2-4aa9-94c1-7dcb9f766b3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3805392622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3805392622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.1590948641
Short name T458
Test name
Test status
Simulation time 467841582896 ps
CPU time 1928.43 seconds
Started Jun 30 05:55:31 PM PDT 24
Finished Jun 30 06:27:40 PM PDT 24
Peak memory 364432 kb
Host smart-beed7012-55eb-403a-81be-5523695724cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1590948641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.1590948641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.351870702
Short name T781
Test name
Test status
Simulation time 56154908470 ps
CPU time 1099.5 seconds
Started Jun 30 05:55:31 PM PDT 24
Finished Jun 30 06:13:51 PM PDT 24
Peak memory 332272 kb
Host smart-7c0ce185-11ba-47f0-8007-07a17348226b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=351870702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.351870702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.1077794429
Short name T658
Test name
Test status
Simulation time 9942774716 ps
CPU time 815.03 seconds
Started Jun 30 05:55:32 PM PDT 24
Finished Jun 30 06:09:07 PM PDT 24
Peak memory 294632 kb
Host smart-2781b774-7a2f-432f-8eb9-e882a7b953e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1077794429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1077794429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.2769098542
Short name T974
Test name
Test status
Simulation time 246472081364 ps
CPU time 4268.1 seconds
Started Jun 30 05:55:31 PM PDT 24
Finished Jun 30 07:06:40 PM PDT 24
Peak memory 668456 kb
Host smart-78fd0402-1a87-4207-8b67-fa38f2e2a60d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2769098542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2769098542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.1117792575
Short name T442
Test name
Test status
Simulation time 254322675644 ps
CPU time 3560.57 seconds
Started Jun 30 05:55:31 PM PDT 24
Finished Jun 30 06:54:52 PM PDT 24
Peak memory 561924 kb
Host smart-ab54ba9d-1af2-4114-a573-9537827ae86c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1117792575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.1117792575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.764847241
Short name T716
Test name
Test status
Simulation time 112671117 ps
CPU time 0.74 seconds
Started Jun 30 05:55:48 PM PDT 24
Finished Jun 30 05:55:49 PM PDT 24
Peak memory 205552 kb
Host smart-f20b25e4-51e0-4277-a43f-1f29138cbf1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764847241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.764847241 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.3352339572
Short name T815
Test name
Test status
Simulation time 11338086404 ps
CPU time 259.31 seconds
Started Jun 30 05:55:45 PM PDT 24
Finished Jun 30 06:00:05 PM PDT 24
Peak memory 245308 kb
Host smart-461b5010-654b-4a53-858a-010a4374153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352339572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.3352339572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.1111960540
Short name T36
Test name
Test status
Simulation time 13976986780 ps
CPU time 309.46 seconds
Started Jun 30 05:55:43 PM PDT 24
Finished Jun 30 06:00:53 PM PDT 24
Peak memory 227252 kb
Host smart-b36c1126-9cb5-417d-b5f3-1c08005eccf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111960540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.1111960540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2818524222
Short name T581
Test name
Test status
Simulation time 768607461 ps
CPU time 13.61 seconds
Started Jun 30 05:55:56 PM PDT 24
Finished Jun 30 05:56:10 PM PDT 24
Peak memory 222004 kb
Host smart-c607d732-aac9-4ce8-9ab0-0d63d8296e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818524222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2818524222 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.1470246433
Short name T495
Test name
Test status
Simulation time 4117546440 ps
CPU time 316.27 seconds
Started Jun 30 05:55:49 PM PDT 24
Finished Jun 30 06:01:06 PM PDT 24
Peak memory 257136 kb
Host smart-4717a4ef-c4ed-4e4a-99b5-9a21ce5333b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470246433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1470246433 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.3514315800
Short name T58
Test name
Test status
Simulation time 842315461 ps
CPU time 5.35 seconds
Started Jun 30 05:55:50 PM PDT 24
Finished Jun 30 05:55:56 PM PDT 24
Peak memory 207808 kb
Host smart-ed3154ed-9ced-493c-993b-89c4c49a4399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514315800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3514315800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.90733969
Short name T83
Test name
Test status
Simulation time 78689891 ps
CPU time 1.28 seconds
Started Jun 30 05:55:49 PM PDT 24
Finished Jun 30 05:55:51 PM PDT 24
Peak memory 216048 kb
Host smart-e62b65c6-ad52-4ff1-9f74-afe94237ac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90733969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.90733969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.2811722676
Short name T457
Test name
Test status
Simulation time 245080263929 ps
CPU time 1717.28 seconds
Started Jun 30 05:55:38 PM PDT 24
Finished Jun 30 06:24:16 PM PDT 24
Peak memory 389764 kb
Host smart-44bfe82c-0735-4a0f-9e96-8d16804a1d6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811722676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.2811722676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.1465630589
Short name T359
Test name
Test status
Simulation time 55084675918 ps
CPU time 253.47 seconds
Started Jun 30 05:55:37 PM PDT 24
Finished Jun 30 05:59:51 PM PDT 24
Peak memory 240696 kb
Host smart-4d457357-7b2c-4d40-b4f6-52880be9a02c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465630589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1465630589 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.98217865
Short name T559
Test name
Test status
Simulation time 962321768 ps
CPU time 49.22 seconds
Started Jun 30 05:55:37 PM PDT 24
Finished Jun 30 05:56:26 PM PDT 24
Peak memory 216144 kb
Host smart-c41b3d80-e2ff-4d68-94d0-49d99a0b82f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98217865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.98217865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3030136460
Short name T787
Test name
Test status
Simulation time 25556568177 ps
CPU time 276.52 seconds
Started Jun 30 05:55:49 PM PDT 24
Finished Jun 30 06:00:26 PM PDT 24
Peak memory 259676 kb
Host smart-70fbaba6-3d71-4f23-a433-67a0b22b4f4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3030136460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3030136460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.1296701514
Short name T567
Test name
Test status
Simulation time 318688709 ps
CPU time 4.86 seconds
Started Jun 30 05:55:48 PM PDT 24
Finished Jun 30 05:55:53 PM PDT 24
Peak memory 216144 kb
Host smart-3b305267-59e4-46b4-929d-3868d30aa48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296701514 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.1296701514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.860786178
Short name T265
Test name
Test status
Simulation time 490297283 ps
CPU time 5.18 seconds
Started Jun 30 05:55:44 PM PDT 24
Finished Jun 30 05:55:50 PM PDT 24
Peak memory 216104 kb
Host smart-256bfc20-c1c5-4481-a8ff-6b95d5c354a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860786178 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.kmac_test_vectors_kmac_xof.860786178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.578590872
Short name T221
Test name
Test status
Simulation time 704995726233 ps
CPU time 2040.72 seconds
Started Jun 30 05:55:49 PM PDT 24
Finished Jun 30 06:29:50 PM PDT 24
Peak memory 398312 kb
Host smart-94649816-c78b-4843-96cd-dc321c3d2f85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=578590872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.578590872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.695564921
Short name T609
Test name
Test status
Simulation time 380670273346 ps
CPU time 2011.69 seconds
Started Jun 30 05:55:43 PM PDT 24
Finished Jun 30 06:29:16 PM PDT 24
Peak memory 374060 kb
Host smart-77d6cf80-4d75-4238-b9bc-0cb9c0d55326
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=695564921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.695564921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.719916950
Short name T292
Test name
Test status
Simulation time 176414732046 ps
CPU time 1343.94 seconds
Started Jun 30 05:55:43 PM PDT 24
Finished Jun 30 06:18:07 PM PDT 24
Peak memory 339532 kb
Host smart-cf29a3eb-0f99-4817-98a7-123c6882c75b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=719916950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.719916950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.2773855618
Short name T543
Test name
Test status
Simulation time 374257084992 ps
CPU time 986.76 seconds
Started Jun 30 05:55:48 PM PDT 24
Finished Jun 30 06:12:15 PM PDT 24
Peak memory 294672 kb
Host smart-9af16620-7590-4eaa-9189-ef50ffe1e2aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2773855618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.2773855618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1275634292
Short name T331
Test name
Test status
Simulation time 173131091913 ps
CPU time 4558.88 seconds
Started Jun 30 05:55:43 PM PDT 24
Finished Jun 30 07:11:43 PM PDT 24
Peak memory 657932 kb
Host smart-ca58d63f-4fcf-4949-a532-63687b0c1e3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1275634292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1275634292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.3729409540
Short name T502
Test name
Test status
Simulation time 181921057008 ps
CPU time 3551.36 seconds
Started Jun 30 05:55:45 PM PDT 24
Finished Jun 30 06:54:57 PM PDT 24
Peak memory 569064 kb
Host smart-6b060f79-21c0-48f6-820e-8b46178b9829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3729409540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3729409540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.2248013948
Short name T989
Test name
Test status
Simulation time 44508114 ps
CPU time 0.78 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 05:51:48 PM PDT 24
Peak memory 205552 kb
Host smart-cfca8a6b-dba7-4862-91c3-9a60070806d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248013948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.2248013948 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.3077831288
Short name T695
Test name
Test status
Simulation time 2464640482 ps
CPU time 119.18 seconds
Started Jun 30 05:51:45 PM PDT 24
Finished Jun 30 05:53:45 PM PDT 24
Peak memory 232800 kb
Host smart-85d200ab-cc76-468c-8542-c344b7e42b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077831288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3077831288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.2394572771
Short name T33
Test name
Test status
Simulation time 44236087245 ps
CPU time 161.16 seconds
Started Jun 30 05:51:47 PM PDT 24
Finished Jun 30 05:54:29 PM PDT 24
Peak memory 233340 kb
Host smart-1cebe418-146d-4a05-84e1-3d2a0e0fc534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394572771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2394572771 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.1317684668
Short name T127
Test name
Test status
Simulation time 7683343813 ps
CPU time 44.97 seconds
Started Jun 30 05:51:47 PM PDT 24
Finished Jun 30 05:52:33 PM PDT 24
Peak memory 221396 kb
Host smart-e9513338-9997-431c-be1b-6a29a83778ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317684668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1317684668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3767961213
Short name T79
Test name
Test status
Simulation time 542671956 ps
CPU time 20.39 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 05:52:08 PM PDT 24
Peak memory 236436 kb
Host smart-a1ad59be-a4dc-48eb-9569-c67e62553d76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3767961213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3767961213 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1868961456
Short name T227
Test name
Test status
Simulation time 771698244 ps
CPU time 14.64 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 05:52:02 PM PDT 24
Peak memory 219280 kb
Host smart-39356aaa-76ca-4171-b7ba-fa2aed6b93b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1868961456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1868961456 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.3944975294
Short name T587
Test name
Test status
Simulation time 2617382139 ps
CPU time 24.93 seconds
Started Jun 30 05:51:49 PM PDT 24
Finished Jun 30 05:52:14 PM PDT 24
Peak memory 224316 kb
Host smart-14b1bf74-7260-4c2b-9499-691faada1d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944975294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3944975294 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.3561304392
Short name T937
Test name
Test status
Simulation time 19813451660 ps
CPU time 335.21 seconds
Started Jun 30 05:51:47 PM PDT 24
Finished Jun 30 05:57:23 PM PDT 24
Peak memory 246444 kb
Host smart-e612422e-64e5-4095-97eb-8a7692d7f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561304392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3561304392 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.3583207189
Short name T589
Test name
Test status
Simulation time 28840171265 ps
CPU time 190.89 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 05:54:58 PM PDT 24
Peak memory 240736 kb
Host smart-5b741b78-3c35-4c4a-9759-bc480750e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583207189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3583207189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.1590209710
Short name T1056
Test name
Test status
Simulation time 1788963420 ps
CPU time 9.33 seconds
Started Jun 30 05:51:49 PM PDT 24
Finished Jun 30 05:51:58 PM PDT 24
Peak memory 207824 kb
Host smart-56dbdb7e-787d-42eb-9435-4386cf833c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590209710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1590209710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.1758067909
Short name T7
Test name
Test status
Simulation time 105262117 ps
CPU time 1.19 seconds
Started Jun 30 05:51:50 PM PDT 24
Finished Jun 30 05:51:52 PM PDT 24
Peak memory 216108 kb
Host smart-dac44e31-d9ce-4e45-9a36-54396cabdcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758067909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1758067909 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.4153740738
Short name T740
Test name
Test status
Simulation time 334910860156 ps
CPU time 1179.07 seconds
Started Jun 30 05:51:40 PM PDT 24
Finished Jun 30 06:11:20 PM PDT 24
Peak memory 324988 kb
Host smart-521772b0-85b8-4088-9e5a-e5cee4d050f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153740738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.4153740738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.3727411771
Short name T426
Test name
Test status
Simulation time 3424528813 ps
CPU time 94.84 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 05:53:21 PM PDT 24
Peak memory 230368 kb
Host smart-48e971bc-b4a7-42a9-aa89-45626140579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727411771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3727411771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.1607466044
Short name T246
Test name
Test status
Simulation time 27506974699 ps
CPU time 229.75 seconds
Started Jun 30 05:51:40 PM PDT 24
Finished Jun 30 05:55:30 PM PDT 24
Peak memory 239596 kb
Host smart-9d6ec349-1f69-4cdd-8f59-2f1747b57851
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607466044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1607466044 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.2647852744
Short name T1023
Test name
Test status
Simulation time 273394511 ps
CPU time 3.67 seconds
Started Jun 30 05:51:43 PM PDT 24
Finished Jun 30 05:51:48 PM PDT 24
Peak memory 219564 kb
Host smart-d8f57d16-87b0-4083-b964-9cdc78ed31f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647852744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2647852744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.3095394628
Short name T513
Test name
Test status
Simulation time 252248433542 ps
CPU time 857.88 seconds
Started Jun 30 05:51:47 PM PDT 24
Finished Jun 30 06:06:06 PM PDT 24
Peak memory 321404 kb
Host smart-2387dd14-2d2b-490e-a2de-a95ae2f6eedf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3095394628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3095394628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.4199492831
Short name T640
Test name
Test status
Simulation time 683489457 ps
CPU time 4.94 seconds
Started Jun 30 05:51:47 PM PDT 24
Finished Jun 30 05:51:53 PM PDT 24
Peak memory 216108 kb
Host smart-4df06d48-09d5-4672-b03d-0ac85e6f72cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199492831 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.4199492831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1344188445
Short name T508
Test name
Test status
Simulation time 341576751 ps
CPU time 4.35 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 05:51:52 PM PDT 24
Peak memory 216100 kb
Host smart-dab77a40-14da-4761-bd3f-267561fed8b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344188445 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1344188445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2818820427
Short name T159
Test name
Test status
Simulation time 80166965529 ps
CPU time 1598.53 seconds
Started Jun 30 05:51:48 PM PDT 24
Finished Jun 30 06:18:27 PM PDT 24
Peak memory 401200 kb
Host smart-90c888c0-39e7-4357-8e07-ee83d7b43334
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2818820427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2818820427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1714947044
Short name T779
Test name
Test status
Simulation time 702831928065 ps
CPU time 2062.59 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 06:26:10 PM PDT 24
Peak memory 374208 kb
Host smart-ccf7e1f1-eaa2-41af-9900-1471a3ad1ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1714947044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1714947044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.826605127
Short name T450
Test name
Test status
Simulation time 48259184799 ps
CPU time 1352.3 seconds
Started Jun 30 05:51:47 PM PDT 24
Finished Jun 30 06:14:20 PM PDT 24
Peak memory 343460 kb
Host smart-c2346ca3-8567-496f-9380-28df3f29c0d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=826605127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.826605127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1073326914
Short name T528
Test name
Test status
Simulation time 9649313139 ps
CPU time 725.85 seconds
Started Jun 30 05:51:48 PM PDT 24
Finished Jun 30 06:03:55 PM PDT 24
Peak memory 290580 kb
Host smart-dcb0ebcd-c5df-4980-b233-f623079623e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1073326914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1073326914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.846032778
Short name T402
Test name
Test status
Simulation time 51168407093 ps
CPU time 4165.01 seconds
Started Jun 30 05:51:46 PM PDT 24
Finished Jun 30 07:01:13 PM PDT 24
Peak memory 656532 kb
Host smart-7e453820-9502-449e-b462-e7c9d2df3ca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=846032778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.846032778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.3134234721
Short name T585
Test name
Test status
Simulation time 88304508845 ps
CPU time 3451.99 seconds
Started Jun 30 05:51:47 PM PDT 24
Finished Jun 30 06:49:20 PM PDT 24
Peak memory 562032 kb
Host smart-6a978ca0-71e2-4ea2-a31f-676f78ce55bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3134234721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3134234721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3812233408
Short name T498
Test name
Test status
Simulation time 183847942 ps
CPU time 0.82 seconds
Started Jun 30 05:56:03 PM PDT 24
Finished Jun 30 05:56:04 PM PDT 24
Peak memory 205652 kb
Host smart-f81167d0-a591-47c5-b949-fc6704f0e37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812233408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3812233408 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.3319158577
Short name T906
Test name
Test status
Simulation time 6441948976 ps
CPU time 28.17 seconds
Started Jun 30 05:55:58 PM PDT 24
Finished Jun 30 05:56:27 PM PDT 24
Peak memory 224380 kb
Host smart-eb3d81ea-709a-433f-866f-913a29b2bc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319158577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3319158577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.1370250528
Short name T367
Test name
Test status
Simulation time 48954891865 ps
CPU time 765.34 seconds
Started Jun 30 05:55:49 PM PDT 24
Finished Jun 30 06:08:35 PM PDT 24
Peak memory 232344 kb
Host smart-fc0ae757-e14c-46d8-b566-69721e345730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370250528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1370250528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.948727394
Short name T1074
Test name
Test status
Simulation time 42564016166 ps
CPU time 201.92 seconds
Started Jun 30 05:55:55 PM PDT 24
Finished Jun 30 05:59:18 PM PDT 24
Peak memory 237544 kb
Host smart-c795260a-b772-47e4-9ab5-555dd647e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948727394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.948727394 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.665612030
Short name T509
Test name
Test status
Simulation time 4133711152 ps
CPU time 305.69 seconds
Started Jun 30 05:56:03 PM PDT 24
Finished Jun 30 06:01:09 PM PDT 24
Peak memory 258276 kb
Host smart-21aa5c75-71b6-44a9-888d-caea5cab4293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665612030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.665612030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2401376971
Short name T1018
Test name
Test status
Simulation time 3072217524 ps
CPU time 5.07 seconds
Started Jun 30 05:56:05 PM PDT 24
Finished Jun 30 05:56:10 PM PDT 24
Peak memory 207936 kb
Host smart-4dcf2285-df46-4a5b-8171-adf778f98f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401376971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2401376971 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.687136363
Short name T456
Test name
Test status
Simulation time 42877801 ps
CPU time 1.37 seconds
Started Jun 30 05:56:03 PM PDT 24
Finished Jun 30 05:56:05 PM PDT 24
Peak memory 216044 kb
Host smart-2561c74c-0821-4c1c-aa58-5fde47f991c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687136363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.687136363 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.4157828514
Short name T789
Test name
Test status
Simulation time 232404261803 ps
CPU time 1407.04 seconds
Started Jun 30 05:55:55 PM PDT 24
Finished Jun 30 06:19:23 PM PDT 24
Peak memory 348836 kb
Host smart-cfe9033e-ea50-456d-89b3-7f95b0b2f04a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157828514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.4157828514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.2222659304
Short name T831
Test name
Test status
Simulation time 5095727170 ps
CPU time 36.96 seconds
Started Jun 30 05:55:50 PM PDT 24
Finished Jun 30 05:56:27 PM PDT 24
Peak memory 224372 kb
Host smart-acbce0a5-8661-4b1c-8276-17a00b0aa57a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222659304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2222659304 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.586884633
Short name T851
Test name
Test status
Simulation time 3358829294 ps
CPU time 21.76 seconds
Started Jun 30 05:55:50 PM PDT 24
Finished Jun 30 05:56:12 PM PDT 24
Peak memory 217540 kb
Host smart-d0600bf6-5c11-4bf5-a464-ae04aa9afae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586884633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.586884633 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.2503796341
Short name T73
Test name
Test status
Simulation time 124973332483 ps
CPU time 2301.21 seconds
Started Jun 30 05:56:05 PM PDT 24
Finished Jun 30 06:34:26 PM PDT 24
Peak memory 511468 kb
Host smart-30469404-7c20-4deb-b0b9-2ead96f6f088
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2503796341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2503796341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.3828440235
Short name T965
Test name
Test status
Simulation time 2334234033 ps
CPU time 5.06 seconds
Started Jun 30 05:55:55 PM PDT 24
Finished Jun 30 05:56:00 PM PDT 24
Peak memory 216180 kb
Host smart-8d4d9ee3-4cd5-42dc-a6bc-88c6f1ed8f6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828440235 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.3828440235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.1273166326
Short name T932
Test name
Test status
Simulation time 166489556 ps
CPU time 4.62 seconds
Started Jun 30 05:55:56 PM PDT 24
Finished Jun 30 05:56:01 PM PDT 24
Peak memory 216160 kb
Host smart-6a41ede5-4725-4bc2-9494-739548e1b3fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273166326 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.1273166326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.905441806
Short name T408
Test name
Test status
Simulation time 39873789967 ps
CPU time 1590.6 seconds
Started Jun 30 05:55:55 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 399260 kb
Host smart-bcfe947e-1679-45b4-9ac0-d852e0a81144
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=905441806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.905441806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.2448293626
Short name T376
Test name
Test status
Simulation time 18527766783 ps
CPU time 1451.48 seconds
Started Jun 30 05:55:52 PM PDT 24
Finished Jun 30 06:20:04 PM PDT 24
Peak memory 370036 kb
Host smart-296a42c8-2daf-40f9-a384-fd05faad1dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2448293626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2448293626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.253338755
Short name T648
Test name
Test status
Simulation time 55872873601 ps
CPU time 1092.98 seconds
Started Jun 30 05:55:50 PM PDT 24
Finished Jun 30 06:14:04 PM PDT 24
Peak memory 330576 kb
Host smart-ca1d01d0-3c60-41cc-93ba-63f4e2dd6a87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=253338755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.253338755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.1926044093
Short name T434
Test name
Test status
Simulation time 37104493588 ps
CPU time 820.01 seconds
Started Jun 30 05:55:51 PM PDT 24
Finished Jun 30 06:09:32 PM PDT 24
Peak memory 290820 kb
Host smart-09dda2df-d055-496c-ba05-8453f47f090f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1926044093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.1926044093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1431517683
Short name T185
Test name
Test status
Simulation time 1019932504330 ps
CPU time 4197.77 seconds
Started Jun 30 05:55:53 PM PDT 24
Finished Jun 30 07:05:51 PM PDT 24
Peak memory 653680 kb
Host smart-49f9fa73-7ab3-46cf-b5e8-4017b6c0e01b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1431517683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1431517683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.3592937187
Short name T465
Test name
Test status
Simulation time 400221507731 ps
CPU time 3860.9 seconds
Started Jun 30 05:55:57 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 561012 kb
Host smart-a9ae51b2-7d9d-4112-8634-1eb11c8302dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3592937187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3592937187 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1051883653
Short name T399
Test name
Test status
Simulation time 14803209 ps
CPU time 0.8 seconds
Started Jun 30 05:56:15 PM PDT 24
Finished Jun 30 05:56:17 PM PDT 24
Peak memory 205648 kb
Host smart-e417929c-fcf8-4dae-87a1-953ba3502e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051883653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1051883653 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3834303241
Short name T892
Test name
Test status
Simulation time 51383109657 ps
CPU time 269.96 seconds
Started Jun 30 05:56:09 PM PDT 24
Finished Jun 30 06:00:40 PM PDT 24
Peak memory 241932 kb
Host smart-21bbd5e0-8d78-4f66-99e0-28ac6ec9c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834303241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3834303241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.1167369958
Short name T313
Test name
Test status
Simulation time 22968617132 ps
CPU time 695.13 seconds
Started Jun 30 05:56:10 PM PDT 24
Finished Jun 30 06:07:46 PM PDT 24
Peak memory 231264 kb
Host smart-066952d6-ed84-4984-a5cd-ee659842ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167369958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1167369958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.128767631
Short name T233
Test name
Test status
Simulation time 2817465462 ps
CPU time 41.03 seconds
Started Jun 30 05:56:10 PM PDT 24
Finished Jun 30 05:56:51 PM PDT 24
Peak memory 221108 kb
Host smart-f2df3b6c-0eea-47e2-adcd-5b8c5d028836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128767631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.128767631 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.2816906949
Short name T398
Test name
Test status
Simulation time 11692047792 ps
CPU time 300.48 seconds
Started Jun 30 05:56:12 PM PDT 24
Finished Jun 30 06:01:13 PM PDT 24
Peak memory 257132 kb
Host smart-9e553e9a-49ee-4f25-af83-dd75980da6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816906949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2816906949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.2948411082
Short name T982
Test name
Test status
Simulation time 952225974 ps
CPU time 1.74 seconds
Started Jun 30 05:56:10 PM PDT 24
Finished Jun 30 05:56:12 PM PDT 24
Peak memory 207788 kb
Host smart-eba28d76-9896-46b9-aaac-4e08a454484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948411082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2948411082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.2013823005
Short name T31
Test name
Test status
Simulation time 23761740 ps
CPU time 1.28 seconds
Started Jun 30 05:56:10 PM PDT 24
Finished Jun 30 05:56:12 PM PDT 24
Peak memory 217624 kb
Host smart-455b3557-ce11-4ebd-9c3e-3f37e210438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013823005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2013823005 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.4209202268
Short name T1014
Test name
Test status
Simulation time 7510476677 ps
CPU time 663.85 seconds
Started Jun 30 05:56:01 PM PDT 24
Finished Jun 30 06:07:05 PM PDT 24
Peak memory 286940 kb
Host smart-55754691-b6c5-4741-a04a-1e58f3899e74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209202268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.4209202268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2576913025
Short name T895
Test name
Test status
Simulation time 1371979984 ps
CPU time 105.85 seconds
Started Jun 30 05:56:11 PM PDT 24
Finished Jun 30 05:57:57 PM PDT 24
Peak memory 228388 kb
Host smart-40f611c8-f640-4291-8e87-aab50e9ae608
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576913025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2576913025 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.1392232452
Short name T641
Test name
Test status
Simulation time 301560962 ps
CPU time 12.33 seconds
Started Jun 30 05:56:04 PM PDT 24
Finished Jun 30 05:56:17 PM PDT 24
Peak memory 222288 kb
Host smart-f5a418dc-b382-4715-bfa5-717dbc2ea2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392232452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1392232452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.3714885485
Short name T464
Test name
Test status
Simulation time 129427140838 ps
CPU time 753.35 seconds
Started Jun 30 05:56:15 PM PDT 24
Finished Jun 30 06:08:49 PM PDT 24
Peak memory 316656 kb
Host smart-b55ee28a-9386-4d54-914b-8ca1c86d1d5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3714885485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3714885485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.466595959
Short name T387
Test name
Test status
Simulation time 267767755 ps
CPU time 4.07 seconds
Started Jun 30 05:56:10 PM PDT 24
Finished Jun 30 05:56:15 PM PDT 24
Peak memory 216224 kb
Host smart-8cf60afd-d9f5-4522-ba32-0cc91c155b8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466595959 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.kmac_test_vectors_kmac.466595959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.3292781279
Short name T123
Test name
Test status
Simulation time 2602934652 ps
CPU time 5.48 seconds
Started Jun 30 05:56:09 PM PDT 24
Finished Jun 30 05:56:15 PM PDT 24
Peak memory 216288 kb
Host smart-81adbb93-e003-4a1d-9f00-00acbf2d23d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292781279 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.3292781279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.384227453
Short name T928
Test name
Test status
Simulation time 39907917965 ps
CPU time 1635.99 seconds
Started Jun 30 05:56:09 PM PDT 24
Finished Jun 30 06:23:26 PM PDT 24
Peak memory 391224 kb
Host smart-9b91bd3f-8939-41d7-a35b-5b7fad5f037a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=384227453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.384227453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.85391398
Short name T793
Test name
Test status
Simulation time 17762224497 ps
CPU time 1520.26 seconds
Started Jun 30 05:56:09 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 375024 kb
Host smart-5b4e0015-f69f-43a2-985e-e734973b2b46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=85391398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.85391398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.122472863
Short name T396
Test name
Test status
Simulation time 55633230711 ps
CPU time 1174.21 seconds
Started Jun 30 05:56:10 PM PDT 24
Finished Jun 30 06:15:45 PM PDT 24
Peak memory 341348 kb
Host smart-86831d33-a66d-46e7-bf3b-08e7f2d6ca64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=122472863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.122472863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.2303790376
Short name T797
Test name
Test status
Simulation time 10277253845 ps
CPU time 791.49 seconds
Started Jun 30 05:56:09 PM PDT 24
Finished Jun 30 06:09:21 PM PDT 24
Peak memory 302388 kb
Host smart-711a7209-b443-4932-b3a0-6f32e4987f29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2303790376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2303790376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.2298906592
Short name T224
Test name
Test status
Simulation time 295606054937 ps
CPU time 5049.36 seconds
Started Jun 30 05:56:11 PM PDT 24
Finished Jun 30 07:20:21 PM PDT 24
Peak memory 652976 kb
Host smart-f93f5369-fbe1-4138-9067-227244e73982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2298906592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.2298906592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.2678564638
Short name T511
Test name
Test status
Simulation time 174362967966 ps
CPU time 3707.84 seconds
Started Jun 30 05:56:10 PM PDT 24
Finished Jun 30 06:57:59 PM PDT 24
Peak memory 558560 kb
Host smart-a7d850a2-9490-4dc9-96cd-0c30dd3915bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2678564638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.2678564638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.884127089
Short name T702
Test name
Test status
Simulation time 31032843 ps
CPU time 0.88 seconds
Started Jun 30 05:56:32 PM PDT 24
Finished Jun 30 05:56:34 PM PDT 24
Peak memory 205616 kb
Host smart-a53ff252-d2b5-4f1d-b533-2c0ab848a7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884127089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.884127089 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_burst_write.3217010007
Short name T865
Test name
Test status
Simulation time 34659366635 ps
CPU time 663.08 seconds
Started Jun 30 05:56:17 PM PDT 24
Finished Jun 30 06:07:20 PM PDT 24
Peak memory 232156 kb
Host smart-6eaec0eb-bcd2-4c60-a031-94978a95e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217010007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3217010007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.48786333
Short name T683
Test name
Test status
Simulation time 3595480549 ps
CPU time 62.99 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 05:57:35 PM PDT 24
Peak memory 225768 kb
Host smart-6fe3fd2b-d97a-476b-8011-59f39851b249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48786333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.48786333 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3375833627
Short name T446
Test name
Test status
Simulation time 82577177723 ps
CPU time 413.89 seconds
Started Jun 30 05:56:32 PM PDT 24
Finished Jun 30 06:03:26 PM PDT 24
Peak memory 255388 kb
Host smart-c1edaa20-1399-489f-b60e-198ea7b84b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375833627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3375833627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2136457728
Short name T56
Test name
Test status
Simulation time 5785299709 ps
CPU time 5.25 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 05:56:37 PM PDT 24
Peak memory 207968 kb
Host smart-13ec266b-2267-4b67-a544-b4b1e9e6767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136457728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2136457728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3079540847
Short name T993
Test name
Test status
Simulation time 48371916 ps
CPU time 1.33 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 05:56:33 PM PDT 24
Peak memory 216072 kb
Host smart-85e898a2-f317-4ab8-8eca-3d845a0db4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079540847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3079540847 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.1862430242
Short name T723
Test name
Test status
Simulation time 25395328062 ps
CPU time 306.18 seconds
Started Jun 30 05:56:15 PM PDT 24
Finished Jun 30 06:01:21 PM PDT 24
Peak memory 249604 kb
Host smart-5c800421-dc52-4d87-a7ca-12b09406c2fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862430242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.1862430242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.1218102954
Short name T1019
Test name
Test status
Simulation time 19585647872 ps
CPU time 376.54 seconds
Started Jun 30 05:56:15 PM PDT 24
Finished Jun 30 06:02:32 PM PDT 24
Peak memory 248620 kb
Host smart-a7313623-82d0-421b-aeb0-9f3166eee838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218102954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1218102954 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3594305258
Short name T735
Test name
Test status
Simulation time 13902377899 ps
CPU time 65.66 seconds
Started Jun 30 05:56:16 PM PDT 24
Finished Jun 30 05:57:22 PM PDT 24
Peak memory 217244 kb
Host smart-ec7bd6d9-7528-432a-9a79-26649189f6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594305258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3594305258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.1656740613
Short name T750
Test name
Test status
Simulation time 142026813491 ps
CPU time 633.57 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 06:07:05 PM PDT 24
Peak memory 317244 kb
Host smart-80aebe58-c14e-4425-94e5-442967cc93c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1656740613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1656740613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.4273110242
Short name T307
Test name
Test status
Simulation time 2281375766 ps
CPU time 5.81 seconds
Started Jun 30 05:56:30 PM PDT 24
Finished Jun 30 05:56:37 PM PDT 24
Peak memory 216176 kb
Host smart-da91865f-9619-46e0-a29b-31cb2ad798c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273110242 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.4273110242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.4122985744
Short name T856
Test name
Test status
Simulation time 191993118 ps
CPU time 4.72 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 05:56:37 PM PDT 24
Peak memory 216140 kb
Host smart-33764c05-ea55-461f-879f-5602b1dd5ea4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122985744 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.4122985744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.4059283752
Short name T234
Test name
Test status
Simulation time 93748278222 ps
CPU time 1918.98 seconds
Started Jun 30 05:56:15 PM PDT 24
Finished Jun 30 06:28:15 PM PDT 24
Peak memory 372688 kb
Host smart-bf1dd048-b58f-49f1-ac01-e387824262e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4059283752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.4059283752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.1283511228
Short name T964
Test name
Test status
Simulation time 215058212644 ps
CPU time 1711.35 seconds
Started Jun 30 05:56:23 PM PDT 24
Finished Jun 30 06:24:55 PM PDT 24
Peak memory 388796 kb
Host smart-7a8094eb-7b4d-42bc-990a-1b3e08565d62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1283511228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.1283511228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2306106640
Short name T564
Test name
Test status
Simulation time 138845576805 ps
CPU time 1417.84 seconds
Started Jun 30 05:56:24 PM PDT 24
Finished Jun 30 06:20:03 PM PDT 24
Peak memory 327300 kb
Host smart-45aabf33-5468-49c1-811f-1b8ab69e29e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2306106640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2306106640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.2332515300
Short name T1011
Test name
Test status
Simulation time 49730935888 ps
CPU time 1047.79 seconds
Started Jun 30 05:56:24 PM PDT 24
Finished Jun 30 06:13:52 PM PDT 24
Peak memory 298500 kb
Host smart-1407c069-dd8b-4c5d-a480-18b4ad9d05b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2332515300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.2332515300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.2738576156
Short name T439
Test name
Test status
Simulation time 211278937581 ps
CPU time 4010.17 seconds
Started Jun 30 05:56:25 PM PDT 24
Finished Jun 30 07:03:16 PM PDT 24
Peak memory 647192 kb
Host smart-dbc2c7d9-69c8-4260-8dd6-338ad8a66f19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2738576156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.2738576156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.2480516761
Short name T625
Test name
Test status
Simulation time 1350057173637 ps
CPU time 4681.82 seconds
Started Jun 30 05:56:32 PM PDT 24
Finished Jun 30 07:14:35 PM PDT 24
Peak memory 559492 kb
Host smart-c7280758-978c-402d-9af2-d51acd16ae40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2480516761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2480516761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.2662093253
Short name T242
Test name
Test status
Simulation time 14431150 ps
CPU time 0.77 seconds
Started Jun 30 05:56:44 PM PDT 24
Finished Jun 30 05:56:45 PM PDT 24
Peak memory 205636 kb
Host smart-676c5d28-f02f-4b0d-bb4d-11fd7b4f6d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662093253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2662093253 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.1854241992
Short name T917
Test name
Test status
Simulation time 262512651 ps
CPU time 12.56 seconds
Started Jun 30 05:56:37 PM PDT 24
Finished Jun 30 05:56:50 PM PDT 24
Peak memory 223796 kb
Host smart-c9cbd925-7663-4482-ab45-7a60bac0b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854241992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1854241992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.4036381224
Short name T459
Test name
Test status
Simulation time 8151931416 ps
CPU time 743.34 seconds
Started Jun 30 05:56:35 PM PDT 24
Finished Jun 30 06:08:59 PM PDT 24
Peak memory 232044 kb
Host smart-ea7fc37e-9942-4d42-8e3b-f9e84f1023ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036381224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.4036381224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.3060089417
Short name T803
Test name
Test status
Simulation time 8968493099 ps
CPU time 191.09 seconds
Started Jun 30 05:56:44 PM PDT 24
Finished Jun 30 05:59:56 PM PDT 24
Peak memory 239724 kb
Host smart-bd5e3610-a633-48da-9a00-ac05de24d3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060089417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3060089417 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.75204669
Short name T959
Test name
Test status
Simulation time 26482464449 ps
CPU time 103.51 seconds
Started Jun 30 05:56:48 PM PDT 24
Finished Jun 30 05:58:32 PM PDT 24
Peak memory 237128 kb
Host smart-7364a09d-4ae6-474a-b0f6-18cca9e203dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75204669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.75204669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.865345910
Short name T873
Test name
Test status
Simulation time 3613323038 ps
CPU time 6.19 seconds
Started Jun 30 05:56:43 PM PDT 24
Finished Jun 30 05:56:50 PM PDT 24
Peak memory 207880 kb
Host smart-11d095bb-2fcf-4b7d-a10e-ec6115135a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865345910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.865345910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3854476392
Short name T482
Test name
Test status
Simulation time 26086186 ps
CPU time 1.14 seconds
Started Jun 30 05:56:44 PM PDT 24
Finished Jun 30 05:56:46 PM PDT 24
Peak memory 216172 kb
Host smart-cdf7f6e5-6339-4e96-86e6-6c4253686c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854476392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3854476392 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.427850818
Short name T799
Test name
Test status
Simulation time 261343575389 ps
CPU time 1423.82 seconds
Started Jun 30 05:56:35 PM PDT 24
Finished Jun 30 06:20:19 PM PDT 24
Peak memory 339248 kb
Host smart-3d256557-23e4-4008-8ef6-d66e3a6e19fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427850818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_an
d_output.427850818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.989479018
Short name T870
Test name
Test status
Simulation time 39614345925 ps
CPU time 283.33 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 06:01:15 PM PDT 24
Peak memory 242028 kb
Host smart-71dc258f-bf09-4e4a-a17e-cb7b043ce114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989479018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.989479018 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.3253541863
Short name T630
Test name
Test status
Simulation time 12036254956 ps
CPU time 71 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 05:57:43 PM PDT 24
Peak memory 222140 kb
Host smart-4ef4b3ab-59b9-4a0d-9954-3a6b304e4aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253541863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3253541863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.2433542397
Short name T1044
Test name
Test status
Simulation time 22089702762 ps
CPU time 710.7 seconds
Started Jun 30 05:56:43 PM PDT 24
Finished Jun 30 06:08:34 PM PDT 24
Peak memory 331116 kb
Host smart-3c752232-0c13-48f5-b67a-7b113f26df91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2433542397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2433542397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.382700261
Short name T983
Test name
Test status
Simulation time 120443474 ps
CPU time 3.92 seconds
Started Jun 30 05:56:37 PM PDT 24
Finished Jun 30 05:56:41 PM PDT 24
Peak memory 216108 kb
Host smart-467a257d-4568-404c-a560-76a94be24b89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382700261 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_test_vectors_kmac.382700261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3772568784
Short name T411
Test name
Test status
Simulation time 458945019 ps
CPU time 4.91 seconds
Started Jun 30 05:56:37 PM PDT 24
Finished Jun 30 05:56:42 PM PDT 24
Peak memory 216108 kb
Host smart-d147dc9a-ff4f-46b8-8b0e-5d05ef6f6fea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772568784 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3772568784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.3621560452
Short name T231
Test name
Test status
Simulation time 97567149650 ps
CPU time 1891.44 seconds
Started Jun 30 05:56:32 PM PDT 24
Finished Jun 30 06:28:04 PM PDT 24
Peak memory 375552 kb
Host smart-faf88dc4-649c-41ad-80a3-837692111a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3621560452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3621560452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.2324201751
Short name T586
Test name
Test status
Simulation time 388105570533 ps
CPU time 1855.76 seconds
Started Jun 30 05:56:31 PM PDT 24
Finished Jun 30 06:27:28 PM PDT 24
Peak memory 391656 kb
Host smart-45dfb7e4-c6d3-4438-a0cc-fea88e45c6cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2324201751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2324201751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.2581782440
Short name T972
Test name
Test status
Simulation time 250505048379 ps
CPU time 1355.4 seconds
Started Jun 30 05:56:30 PM PDT 24
Finished Jun 30 06:19:06 PM PDT 24
Peak memory 332072 kb
Host smart-562fdbd2-e0d4-445c-8d11-b691ddb971d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2581782440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.2581782440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3993932320
Short name T1033
Test name
Test status
Simulation time 147240945653 ps
CPU time 986.09 seconds
Started Jun 30 05:56:37 PM PDT 24
Finished Jun 30 06:13:03 PM PDT 24
Peak memory 302428 kb
Host smart-98163b42-d714-4749-88af-670293dc8ddd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3993932320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3993932320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3719965859
Short name T452
Test name
Test status
Simulation time 174684411147 ps
CPU time 4610.13 seconds
Started Jun 30 05:56:38 PM PDT 24
Finished Jun 30 07:13:29 PM PDT 24
Peak memory 656624 kb
Host smart-a775552f-d6a4-43f5-b095-f86f3d6b4cce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3719965859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3719965859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.2969434620
Short name T990
Test name
Test status
Simulation time 229935384722 ps
CPU time 3672.57 seconds
Started Jun 30 05:56:38 PM PDT 24
Finished Jun 30 06:57:51 PM PDT 24
Peak memory 545168 kb
Host smart-bf7b399f-7ad9-495b-b015-9e92e7ee4068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2969434620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2969434620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.2573084862
Short name T264
Test name
Test status
Simulation time 33507622 ps
CPU time 0.83 seconds
Started Jun 30 05:56:57 PM PDT 24
Finished Jun 30 05:56:58 PM PDT 24
Peak memory 205624 kb
Host smart-9fbbcd40-789c-4ae5-8011-6db3d0e22080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573084862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2573084862 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.2060504687
Short name T162
Test name
Test status
Simulation time 48787029898 ps
CPU time 253.22 seconds
Started Jun 30 05:56:57 PM PDT 24
Finished Jun 30 06:01:10 PM PDT 24
Peak memory 244356 kb
Host smart-65f537d7-ac56-4a1d-af1b-183ddae9d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060504687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2060504687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.1447866274
Short name T710
Test name
Test status
Simulation time 1647468642 ps
CPU time 124.4 seconds
Started Jun 30 05:56:47 PM PDT 24
Finished Jun 30 05:58:51 PM PDT 24
Peak memory 238004 kb
Host smart-018156b8-5e40-4bdb-962d-c1d8beb5b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447866274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1447866274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.3699061653
Short name T742
Test name
Test status
Simulation time 25127181040 ps
CPU time 257.04 seconds
Started Jun 30 05:56:52 PM PDT 24
Finished Jun 30 06:01:09 PM PDT 24
Peak memory 245040 kb
Host smart-47a70871-6315-4cfc-ae07-a5f83129d67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699061653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3699061653 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2858631194
Short name T447
Test name
Test status
Simulation time 2677043886 ps
CPU time 44.79 seconds
Started Jun 30 05:56:51 PM PDT 24
Finished Jun 30 05:57:36 PM PDT 24
Peak memory 240768 kb
Host smart-890e323c-cdb1-49f3-9ce4-d33bab163de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858631194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2858631194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.3228415945
Short name T55
Test name
Test status
Simulation time 2328753486 ps
CPU time 3.06 seconds
Started Jun 30 05:57:03 PM PDT 24
Finished Jun 30 05:57:06 PM PDT 24
Peak memory 207888 kb
Host smart-3e5df93c-2747-45a1-bb0b-12dec7e3d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228415945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3228415945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.299987989
Short name T8
Test name
Test status
Simulation time 42743367 ps
CPU time 1.38 seconds
Started Jun 30 05:56:58 PM PDT 24
Finished Jun 30 05:56:59 PM PDT 24
Peak memory 216036 kb
Host smart-367e7c4b-6ab8-4093-9216-31235d784220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299987989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.299987989 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2970073870
Short name T780
Test name
Test status
Simulation time 287170581324 ps
CPU time 2227.26 seconds
Started Jun 30 05:56:44 PM PDT 24
Finished Jun 30 06:33:52 PM PDT 24
Peak memory 432136 kb
Host smart-e512da77-cb0c-4058-b51d-eaf41400ad9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970073870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2970073870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3833020536
Short name T80
Test name
Test status
Simulation time 1402441508 ps
CPU time 24.66 seconds
Started Jun 30 05:56:47 PM PDT 24
Finished Jun 30 05:57:12 PM PDT 24
Peak memory 223392 kb
Host smart-1a03149b-eb6a-4c01-8a56-350500aa96e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833020536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3833020536 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.986182228
Short name T222
Test name
Test status
Simulation time 22432543016 ps
CPU time 29.96 seconds
Started Jun 30 05:56:47 PM PDT 24
Finished Jun 30 05:57:17 PM PDT 24
Peak memory 217432 kb
Host smart-b48d3b37-3382-4701-9754-a29f45da53da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986182228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.986182228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.974639351
Short name T77
Test name
Test status
Simulation time 20662086090 ps
CPU time 219.46 seconds
Started Jun 30 05:57:04 PM PDT 24
Finished Jun 30 06:00:44 PM PDT 24
Peak memory 273736 kb
Host smart-32501216-f24b-4e5f-b03a-724bb9b143e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=974639351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.974639351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1399323721
Short name T639
Test name
Test status
Simulation time 67246838 ps
CPU time 4.31 seconds
Started Jun 30 05:56:52 PM PDT 24
Finished Jun 30 05:56:57 PM PDT 24
Peak memory 216124 kb
Host smart-cd805949-607d-43b3-b991-b355644ff4a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399323721 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1399323721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.44445976
Short name T783
Test name
Test status
Simulation time 670219150 ps
CPU time 4.39 seconds
Started Jun 30 05:56:50 PM PDT 24
Finished Jun 30 05:56:54 PM PDT 24
Peak memory 216232 kb
Host smart-e8dbba39-c235-468f-97c2-ef04974705e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44445976 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.kmac_test_vectors_kmac_xof.44445976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.814141817
Short name T790
Test name
Test status
Simulation time 160987725986 ps
CPU time 1930.53 seconds
Started Jun 30 05:56:50 PM PDT 24
Finished Jun 30 06:29:01 PM PDT 24
Peak memory 390220 kb
Host smart-46afd88b-6a9c-4c6e-a086-3ce4ee498ac0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=814141817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.814141817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.2392342942
Short name T651
Test name
Test status
Simulation time 126127495542 ps
CPU time 1632.98 seconds
Started Jun 30 05:56:57 PM PDT 24
Finished Jun 30 06:24:10 PM PDT 24
Peak memory 378116 kb
Host smart-47055723-f049-4ece-98c6-385c380298c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2392342942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.2392342942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.205645919
Short name T643
Test name
Test status
Simulation time 137983437047 ps
CPU time 1424.68 seconds
Started Jun 30 05:56:50 PM PDT 24
Finished Jun 30 06:20:35 PM PDT 24
Peak memory 330428 kb
Host smart-9e0d1745-9c1e-4a02-840a-c1581fed8543
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=205645919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.205645919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2937467503
Short name T737
Test name
Test status
Simulation time 64838234341 ps
CPU time 911.88 seconds
Started Jun 30 05:56:50 PM PDT 24
Finished Jun 30 06:12:03 PM PDT 24
Peak memory 294292 kb
Host smart-927d767c-5be3-4919-b3ea-2d2a2bf71981
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2937467503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2937467503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.1762373632
Short name T545
Test name
Test status
Simulation time 347767483915 ps
CPU time 4374.64 seconds
Started Jun 30 05:56:57 PM PDT 24
Finished Jun 30 07:09:52 PM PDT 24
Peak memory 642096 kb
Host smart-a4e097c5-bde1-47a4-9d7b-43aa15cdca9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1762373632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.1762373632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.2189525079
Short name T808
Test name
Test status
Simulation time 88782928849 ps
CPU time 3604.73 seconds
Started Jun 30 05:56:50 PM PDT 24
Finished Jun 30 06:56:55 PM PDT 24
Peak memory 566960 kb
Host smart-8137a1b7-0850-48a0-944b-a76a62d694c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2189525079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.2189525079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.4259674119
Short name T45
Test name
Test status
Simulation time 23241212 ps
CPU time 0.74 seconds
Started Jun 30 05:57:18 PM PDT 24
Finished Jun 30 05:57:19 PM PDT 24
Peak memory 205632 kb
Host smart-fc76ec13-f767-476d-afab-216053eb12f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259674119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.4259674119 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.3893397607
Short name T547
Test name
Test status
Simulation time 1392523941 ps
CPU time 12.21 seconds
Started Jun 30 05:57:07 PM PDT 24
Finished Jun 30 05:57:20 PM PDT 24
Peak memory 224260 kb
Host smart-8df82017-cbbc-48c4-9a00-1b3bdfa224b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893397607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3893397607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.1232678028
Short name T386
Test name
Test status
Simulation time 1786245845 ps
CPU time 53.14 seconds
Started Jun 30 05:57:05 PM PDT 24
Finished Jun 30 05:57:59 PM PDT 24
Peak memory 224276 kb
Host smart-1633faf0-9d9e-4047-950a-61cdf71fde26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232678028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1232678028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.2642021556
Short name T1067
Test name
Test status
Simulation time 4314551149 ps
CPU time 175.95 seconds
Started Jun 30 05:57:08 PM PDT 24
Finished Jun 30 06:00:04 PM PDT 24
Peak memory 240752 kb
Host smart-7b23c9f5-67ba-4013-bd06-a06e540b333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642021556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2642021556 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3812640205
Short name T952
Test name
Test status
Simulation time 9378536364 ps
CPU time 152.29 seconds
Started Jun 30 05:57:03 PM PDT 24
Finished Jun 30 05:59:35 PM PDT 24
Peak memory 248904 kb
Host smart-ab2fd4fb-a6c5-49b2-b993-b0662906fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812640205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3812640205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.51905996
Short name T879
Test name
Test status
Simulation time 969138601 ps
CPU time 5.84 seconds
Started Jun 30 05:57:05 PM PDT 24
Finished Jun 30 05:57:11 PM PDT 24
Peak memory 216356 kb
Host smart-95fe5cfc-d1dc-4c85-b2cc-dad08cc3a31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51905996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.51905996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.4060817192
Short name T934
Test name
Test status
Simulation time 65830786 ps
CPU time 1.24 seconds
Started Jun 30 05:57:04 PM PDT 24
Finished Jun 30 05:57:06 PM PDT 24
Peak memory 216068 kb
Host smart-0901f1f8-0be9-4928-9bb0-c672fdaec097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060817192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4060817192 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2892867880
Short name T337
Test name
Test status
Simulation time 236312726924 ps
CPU time 1456.56 seconds
Started Jun 30 05:56:57 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 355832 kb
Host smart-e680f452-1fcc-4fd2-bf2b-f71e5faec149
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892867880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2892867880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.2293964717
Short name T488
Test name
Test status
Simulation time 2329994455 ps
CPU time 176.61 seconds
Started Jun 30 05:57:04 PM PDT 24
Finished Jun 30 06:00:01 PM PDT 24
Peak memory 237276 kb
Host smart-522cc9d8-fbe9-4235-911e-8b5df4a44905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293964717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2293964717 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.243390293
Short name T273
Test name
Test status
Simulation time 928437365 ps
CPU time 11.79 seconds
Started Jun 30 05:57:01 PM PDT 24
Finished Jun 30 05:57:13 PM PDT 24
Peak memory 219216 kb
Host smart-bfe0ba2c-af13-4e08-98e1-6f9dce371163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243390293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.243390293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.3981769815
Short name T571
Test name
Test status
Simulation time 308765611520 ps
CPU time 593.99 seconds
Started Jun 30 05:57:15 PM PDT 24
Finished Jun 30 06:07:10 PM PDT 24
Peak memory 301768 kb
Host smart-8fde46e7-cca8-414a-902b-95309358858d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3981769815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3981769815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.141338984
Short name T827
Test name
Test status
Simulation time 223925255 ps
CPU time 4.77 seconds
Started Jun 30 05:57:05 PM PDT 24
Finished Jun 30 05:57:11 PM PDT 24
Peak memory 216088 kb
Host smart-8ade99ac-08cc-4da6-9d6b-f08e768c754a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141338984 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.kmac_test_vectors_kmac.141338984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.3729987699
Short name T663
Test name
Test status
Simulation time 248550225 ps
CPU time 4.79 seconds
Started Jun 30 05:57:04 PM PDT 24
Finished Jun 30 05:57:09 PM PDT 24
Peak memory 216136 kb
Host smart-cb329092-2e3e-485d-aba0-e7f479e54b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729987699 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.3729987699 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2465257092
Short name T823
Test name
Test status
Simulation time 157006494558 ps
CPU time 1569.06 seconds
Started Jun 30 05:57:04 PM PDT 24
Finished Jun 30 06:23:13 PM PDT 24
Peak memory 393240 kb
Host smart-4f00db2a-a8b6-407f-ad3e-2e6f3d9fae1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2465257092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2465257092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.2809219929
Short name T806
Test name
Test status
Simulation time 320957067066 ps
CPU time 1912 seconds
Started Jun 30 05:57:08 PM PDT 24
Finished Jun 30 06:29:00 PM PDT 24
Peak memory 377780 kb
Host smart-1db49bf9-55e3-4729-8532-ce29421c136c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2809219929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.2809219929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.4253001305
Short name T516
Test name
Test status
Simulation time 137613135490 ps
CPU time 1393.2 seconds
Started Jun 30 05:57:05 PM PDT 24
Finished Jun 30 06:20:19 PM PDT 24
Peak memory 329580 kb
Host smart-eb8666b7-8345-4ae8-b7bf-eb8916d43668
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4253001305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.4253001305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.734151801
Short name T90
Test name
Test status
Simulation time 464244453248 ps
CPU time 1004.54 seconds
Started Jun 30 05:57:08 PM PDT 24
Finished Jun 30 06:13:53 PM PDT 24
Peak memory 292824 kb
Host smart-31c096c5-4155-4933-92c4-b7d15ebfd415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=734151801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.734151801 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.119402994
Short name T976
Test name
Test status
Simulation time 178655031711 ps
CPU time 4662.89 seconds
Started Jun 30 05:57:05 PM PDT 24
Finished Jun 30 07:14:49 PM PDT 24
Peak memory 658104 kb
Host smart-5e693b36-b332-45fc-a882-e6d6ffbf869d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=119402994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.119402994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.3986313703
Short name T430
Test name
Test status
Simulation time 182114209075 ps
CPU time 3732.05 seconds
Started Jun 30 05:57:06 PM PDT 24
Finished Jun 30 06:59:19 PM PDT 24
Peak memory 569504 kb
Host smart-bd50450d-a41e-45f4-b894-fb2bbe489ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3986313703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3986313703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.3741765240
Short name T881
Test name
Test status
Simulation time 21523974 ps
CPU time 0.75 seconds
Started Jun 30 05:57:26 PM PDT 24
Finished Jun 30 05:57:27 PM PDT 24
Peak memory 205596 kb
Host smart-44e36e30-f0a8-43cd-8cd7-80013b23fefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741765240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3741765240 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.1418911279
Short name T432
Test name
Test status
Simulation time 9356471645 ps
CPU time 96.06 seconds
Started Jun 30 05:57:17 PM PDT 24
Finished Jun 30 05:58:54 PM PDT 24
Peak memory 231024 kb
Host smart-1288ce4c-bbe0-4cc2-9db5-d86bd067b5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418911279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1418911279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3877774938
Short name T19
Test name
Test status
Simulation time 5119132637 ps
CPU time 134.53 seconds
Started Jun 30 05:57:12 PM PDT 24
Finished Jun 30 05:59:27 PM PDT 24
Peak memory 224608 kb
Host smart-4e0a53fc-aa7b-4c82-8b42-a8fa40bff621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877774938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3877774938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.1383584732
Short name T927
Test name
Test status
Simulation time 26425141129 ps
CPU time 180.63 seconds
Started Jun 30 05:57:17 PM PDT 24
Finished Jun 30 06:00:19 PM PDT 24
Peak memory 235948 kb
Host smart-2b9472c9-8b07-4b0b-876c-5006b33f8d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383584732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1383584732 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.2746955292
Short name T558
Test name
Test status
Simulation time 14668797052 ps
CPU time 256.68 seconds
Started Jun 30 05:57:18 PM PDT 24
Finished Jun 30 06:01:35 PM PDT 24
Peak memory 257576 kb
Host smart-5526ae9b-5b40-4332-85c6-68274e7c1cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746955292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2746955292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2523943744
Short name T414
Test name
Test status
Simulation time 244756107 ps
CPU time 1.84 seconds
Started Jun 30 05:57:25 PM PDT 24
Finished Jun 30 05:57:27 PM PDT 24
Peak memory 207884 kb
Host smart-24d19de8-184c-44bb-a6cf-e7ef0023cf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523943744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2523943744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.1783917039
Short name T1030
Test name
Test status
Simulation time 48178525 ps
CPU time 1.3 seconds
Started Jun 30 05:57:23 PM PDT 24
Finished Jun 30 05:57:25 PM PDT 24
Peak memory 217104 kb
Host smart-3b1d46d3-4d92-491c-84a2-0d9bb654356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783917039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1783917039 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2212682410
Short name T966
Test name
Test status
Simulation time 254447270204 ps
CPU time 1199.04 seconds
Started Jun 30 05:57:12 PM PDT 24
Finished Jun 30 06:17:11 PM PDT 24
Peak memory 325572 kb
Host smart-76e56bc8-694e-4741-9cf3-8f466170eb0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212682410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2212682410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.1344145044
Short name T303
Test name
Test status
Simulation time 29932825428 ps
CPU time 359.57 seconds
Started Jun 30 05:57:12 PM PDT 24
Finished Jun 30 06:03:12 PM PDT 24
Peak memory 250312 kb
Host smart-9e013325-4be4-46aa-b801-f945943603f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344145044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1344145044 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.862073544
Short name T861
Test name
Test status
Simulation time 8463074920 ps
CPU time 34.35 seconds
Started Jun 30 05:57:17 PM PDT 24
Finished Jun 30 05:57:52 PM PDT 24
Peak memory 221216 kb
Host smart-882e3724-f29e-4d6c-adcd-15b5cd72d96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862073544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.862073544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.1174765785
Short name T777
Test name
Test status
Simulation time 20507118883 ps
CPU time 421.41 seconds
Started Jun 30 05:57:26 PM PDT 24
Finished Jun 30 06:04:28 PM PDT 24
Peak memory 267060 kb
Host smart-9c778bc3-235d-44da-b1d8-b50f16bea669
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1174765785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1174765785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.3454825842
Short name T201
Test name
Test status
Simulation time 67588723 ps
CPU time 4.23 seconds
Started Jun 30 05:57:18 PM PDT 24
Finished Jun 30 05:57:23 PM PDT 24
Peak memory 209120 kb
Host smart-9bd88dfc-e423-4cef-bf0b-3a950d2b3abd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454825842 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.3454825842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.2686266009
Short name T893
Test name
Test status
Simulation time 380296974 ps
CPU time 4.23 seconds
Started Jun 30 05:57:17 PM PDT 24
Finished Jun 30 05:57:22 PM PDT 24
Peak memory 216132 kb
Host smart-ae57f2d7-14b6-40d8-8f5c-e66cea35c6d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686266009 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.2686266009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.579063005
Short name T766
Test name
Test status
Simulation time 65503699232 ps
CPU time 1875.21 seconds
Started Jun 30 05:57:17 PM PDT 24
Finished Jun 30 06:28:33 PM PDT 24
Peak memory 396540 kb
Host smart-a31cf1ed-fbc9-4f6b-8224-f0cdef2d1a8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=579063005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.579063005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.957283197
Short name T1035
Test name
Test status
Simulation time 437750099689 ps
CPU time 1860.41 seconds
Started Jun 30 05:57:17 PM PDT 24
Finished Jun 30 06:28:18 PM PDT 24
Peak memory 375840 kb
Host smart-509cac4b-20e2-4cdd-a677-32124eae4d97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=957283197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.957283197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.2963512792
Short name T696
Test name
Test status
Simulation time 28615191958 ps
CPU time 1166.76 seconds
Started Jun 30 05:57:11 PM PDT 24
Finished Jun 30 06:16:38 PM PDT 24
Peak memory 337024 kb
Host smart-e89351c8-64e3-4f02-b120-5a6b9bea60bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2963512792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2963512792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.3541061145
Short name T261
Test name
Test status
Simulation time 9882655046 ps
CPU time 813.24 seconds
Started Jun 30 05:57:12 PM PDT 24
Finished Jun 30 06:10:45 PM PDT 24
Peak memory 295184 kb
Host smart-5e8c929d-0e06-4a91-b280-323fcdd68be8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3541061145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3541061145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.1621287127
Short name T593
Test name
Test status
Simulation time 463682444210 ps
CPU time 4943.55 seconds
Started Jun 30 05:57:16 PM PDT 24
Finished Jun 30 07:19:41 PM PDT 24
Peak memory 649572 kb
Host smart-acd09442-bf78-4fd6-a19b-1be8c05e0005
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1621287127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1621287127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.3135499296
Short name T575
Test name
Test status
Simulation time 190112412326 ps
CPU time 3870.4 seconds
Started Jun 30 05:57:18 PM PDT 24
Finished Jun 30 07:01:49 PM PDT 24
Peak memory 567176 kb
Host smart-92654acd-a21b-48fa-a9b4-51d29247e407
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3135499296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3135499296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.2398375652
Short name T496
Test name
Test status
Simulation time 14244400 ps
CPU time 0.77 seconds
Started Jun 30 05:57:38 PM PDT 24
Finished Jun 30 05:57:39 PM PDT 24
Peak memory 205644 kb
Host smart-6a83e360-c4a0-42dc-9995-33bd4d18c13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398375652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2398375652 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.3791374347
Short name T576
Test name
Test status
Simulation time 5417207549 ps
CPU time 70.19 seconds
Started Jun 30 05:57:30 PM PDT 24
Finished Jun 30 05:58:41 PM PDT 24
Peak memory 228488 kb
Host smart-5ca252c9-919b-4eec-a3c9-2a6ea51e82ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791374347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3791374347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.490521252
Short name T752
Test name
Test status
Simulation time 17432783170 ps
CPU time 230.48 seconds
Started Jun 30 05:57:23 PM PDT 24
Finished Jun 30 06:01:14 PM PDT 24
Peak memory 225752 kb
Host smart-43205ac9-08b2-43e5-8749-1a68d6a50a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490521252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.490521252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.3537703953
Short name T364
Test name
Test status
Simulation time 4270169214 ps
CPU time 151.02 seconds
Started Jun 30 05:57:31 PM PDT 24
Finished Jun 30 06:00:03 PM PDT 24
Peak memory 237152 kb
Host smart-f6673e4f-a301-4896-a0ee-d57f7081cbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537703953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3537703953 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.3013532450
Short name T428
Test name
Test status
Simulation time 32684870774 ps
CPU time 220.88 seconds
Started Jun 30 05:57:31 PM PDT 24
Finished Jun 30 06:01:12 PM PDT 24
Peak memory 251000 kb
Host smart-6332fd16-ff6e-4f92-bde3-2da34e736ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013532450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3013532450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.4188037006
Short name T54
Test name
Test status
Simulation time 1449367486 ps
CPU time 2.38 seconds
Started Jun 30 05:57:36 PM PDT 24
Finished Jun 30 05:57:39 PM PDT 24
Peak memory 207800 kb
Host smart-85bee8a3-d21d-40b9-941d-fd91d1a278ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188037006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.4188037006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.4023382269
Short name T1054
Test name
Test status
Simulation time 110080985 ps
CPU time 1.21 seconds
Started Jun 30 05:57:37 PM PDT 24
Finished Jun 30 05:57:39 PM PDT 24
Peak memory 216044 kb
Host smart-ed256f3c-b026-48ac-be5c-d0e83b849e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023382269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.4023382269 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.2158587620
Short name T419
Test name
Test status
Simulation time 316868576953 ps
CPU time 2412.59 seconds
Started Jun 30 05:57:22 PM PDT 24
Finished Jun 30 06:37:35 PM PDT 24
Peak memory 492596 kb
Host smart-becc4fcb-b4d6-4812-b852-789341826c0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158587620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.2158587620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.115406948
Short name T602
Test name
Test status
Simulation time 4359310774 ps
CPU time 347.62 seconds
Started Jun 30 05:57:24 PM PDT 24
Finished Jun 30 06:03:12 PM PDT 24
Peak memory 250384 kb
Host smart-a36789bc-fb92-4183-8cf8-45807e19dfbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115406948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.115406948 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.1246572426
Short name T410
Test name
Test status
Simulation time 2221312002 ps
CPU time 13.9 seconds
Started Jun 30 05:57:26 PM PDT 24
Finished Jun 30 05:57:40 PM PDT 24
Peak memory 220984 kb
Host smart-55195dcc-2d93-4135-a18d-35a3715de0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246572426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1246572426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1764788965
Short name T664
Test name
Test status
Simulation time 55059238734 ps
CPU time 1868.48 seconds
Started Jun 30 05:57:36 PM PDT 24
Finished Jun 30 06:28:46 PM PDT 24
Peak memory 462080 kb
Host smart-c27e426a-a587-445a-af30-e813859f7d38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1764788965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1764788965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.2271267253
Short name T441
Test name
Test status
Simulation time 1583907660 ps
CPU time 5.48 seconds
Started Jun 30 05:57:31 PM PDT 24
Finished Jun 30 05:57:37 PM PDT 24
Peak memory 216144 kb
Host smart-6635b640-414e-482e-9799-0ec5d0b2b31f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271267253 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.2271267253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.4182238234
Short name T297
Test name
Test status
Simulation time 713952681 ps
CPU time 4.56 seconds
Started Jun 30 05:57:32 PM PDT 24
Finished Jun 30 05:57:37 PM PDT 24
Peak memory 216128 kb
Host smart-b3085cac-c5df-4368-9161-9eeee97eaf87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182238234 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.4182238234 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.933151649
Short name T397
Test name
Test status
Simulation time 45769752865 ps
CPU time 1557.91 seconds
Started Jun 30 05:57:25 PM PDT 24
Finished Jun 30 06:23:23 PM PDT 24
Peak memory 391400 kb
Host smart-4edd1cc4-4a94-491b-865e-992ad5e7308e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=933151649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.933151649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.2477688151
Short name T1010
Test name
Test status
Simulation time 258566365305 ps
CPU time 1745.33 seconds
Started Jun 30 05:57:23 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 387164 kb
Host smart-ddbfb05d-49b1-41ad-83c4-8778dc41d70c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2477688151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2477688151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.3572317487
Short name T491
Test name
Test status
Simulation time 55364634314 ps
CPU time 1138.08 seconds
Started Jun 30 05:57:31 PM PDT 24
Finished Jun 30 06:16:29 PM PDT 24
Peak memory 328620 kb
Host smart-0023f243-27c7-4148-b832-355fab981fcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3572317487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3572317487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.3363247767
Short name T709
Test name
Test status
Simulation time 51767871433 ps
CPU time 1008.57 seconds
Started Jun 30 05:57:32 PM PDT 24
Finished Jun 30 06:14:21 PM PDT 24
Peak memory 300904 kb
Host smart-1e41c2e2-5204-45f6-b6b2-f25bd6052e60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3363247767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3363247767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.612845235
Short name T611
Test name
Test status
Simulation time 682145990450 ps
CPU time 4754.5 seconds
Started Jun 30 05:57:33 PM PDT 24
Finished Jun 30 07:16:48 PM PDT 24
Peak memory 642136 kb
Host smart-c5535008-0497-4bf8-abbf-b95d4b186b94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=612845235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.612845235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.2235050119
Short name T381
Test name
Test status
Simulation time 187786167320 ps
CPU time 3964.3 seconds
Started Jun 30 05:57:31 PM PDT 24
Finished Jun 30 07:03:37 PM PDT 24
Peak memory 553620 kb
Host smart-e2361bbd-eef0-492e-9e57-7d8f87d28555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2235050119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2235050119 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.2885449881
Short name T829
Test name
Test status
Simulation time 16717481 ps
CPU time 0.8 seconds
Started Jun 30 05:57:57 PM PDT 24
Finished Jun 30 05:57:58 PM PDT 24
Peak memory 205624 kb
Host smart-0343a3a7-3c68-4d33-a92e-d551267565a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885449881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2885449881 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.3040303905
Short name T847
Test name
Test status
Simulation time 7572900086 ps
CPU time 163.4 seconds
Started Jun 30 05:57:50 PM PDT 24
Finished Jun 30 06:00:34 PM PDT 24
Peak memory 236548 kb
Host smart-2073b008-3d6c-48ae-bea3-592b7fc22fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040303905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3040303905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.3752912573
Short name T1002
Test name
Test status
Simulation time 91165222051 ps
CPU time 593.25 seconds
Started Jun 30 05:57:43 PM PDT 24
Finished Jun 30 06:07:37 PM PDT 24
Peak memory 231788 kb
Host smart-7a8cbcf6-23b3-4b16-ab7f-98b4334956f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752912573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3752912573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.301710848
Short name T161
Test name
Test status
Simulation time 63880792744 ps
CPU time 321.4 seconds
Started Jun 30 05:57:56 PM PDT 24
Finished Jun 30 06:03:18 PM PDT 24
Peak memory 245364 kb
Host smart-9f4d988f-6598-4651-98dd-0c4f25eeab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301710848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.301710848 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1131366469
Short name T629
Test name
Test status
Simulation time 85961779094 ps
CPU time 417.73 seconds
Started Jun 30 05:57:57 PM PDT 24
Finished Jun 30 06:04:55 PM PDT 24
Peak memory 265308 kb
Host smart-271dc290-48d5-430a-8ef7-53d29d8e55fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131366469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1131366469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.1448367771
Short name T53
Test name
Test status
Simulation time 2706805181 ps
CPU time 3.24 seconds
Started Jun 30 05:57:56 PM PDT 24
Finished Jun 30 05:57:59 PM PDT 24
Peak memory 207872 kb
Host smart-2756b3e3-f14d-4421-af3b-59d97b8ec618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448367771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1448367771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.1312254181
Short name T531
Test name
Test status
Simulation time 183885904 ps
CPU time 1.47 seconds
Started Jun 30 05:57:57 PM PDT 24
Finished Jun 30 05:57:59 PM PDT 24
Peak memory 216172 kb
Host smart-f7d0becb-2a1d-406f-8476-74cc4f97c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312254181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1312254181 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.4283879812
Short name T350
Test name
Test status
Simulation time 23570513996 ps
CPU time 2067.89 seconds
Started Jun 30 05:57:43 PM PDT 24
Finished Jun 30 06:32:12 PM PDT 24
Peak memory 449636 kb
Host smart-15b393c8-77ed-408d-b036-1a6f12397260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283879812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.4283879812 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2340371626
Short name T1015
Test name
Test status
Simulation time 6385951608 ps
CPU time 137.54 seconds
Started Jun 30 05:57:44 PM PDT 24
Finished Jun 30 06:00:02 PM PDT 24
Peak memory 231500 kb
Host smart-71f5ad18-81e3-4180-ac88-767d0db9fce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340371626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2340371626 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.2881118336
Short name T125
Test name
Test status
Simulation time 5695212333 ps
CPU time 56.64 seconds
Started Jun 30 05:57:43 PM PDT 24
Finished Jun 30 05:58:40 PM PDT 24
Peak memory 217740 kb
Host smart-1a0f2c4d-2737-49da-b4e5-5659bf362f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881118336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2881118336 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1598216981
Short name T37
Test name
Test status
Simulation time 13324427111 ps
CPU time 552.52 seconds
Started Jun 30 05:57:57 PM PDT 24
Finished Jun 30 06:07:10 PM PDT 24
Peak memory 265584 kb
Host smart-1a3dd88f-7423-4731-bae4-0c1019a501fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1598216981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1598216981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.1358307735
Short name T953
Test name
Test status
Simulation time 69147118 ps
CPU time 4.4 seconds
Started Jun 30 05:57:49 PM PDT 24
Finished Jun 30 05:57:54 PM PDT 24
Peak memory 216396 kb
Host smart-3201a3e8-6950-4fa6-b8b8-4b1c817848ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358307735 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.1358307735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.4240500046
Short name T961
Test name
Test status
Simulation time 450960868 ps
CPU time 3.96 seconds
Started Jun 30 05:57:49 PM PDT 24
Finished Jun 30 05:57:53 PM PDT 24
Peak memory 216112 kb
Host smart-af04b430-5491-4f93-9041-78f1e332809e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240500046 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.4240500046 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1554607686
Short name T770
Test name
Test status
Simulation time 645587841800 ps
CPU time 1989.84 seconds
Started Jun 30 05:57:41 PM PDT 24
Finished Jun 30 06:30:52 PM PDT 24
Peak memory 390016 kb
Host smart-3ca117bf-ce65-4681-bf02-a61418f18af9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1554607686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1554607686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1589256573
Short name T929
Test name
Test status
Simulation time 36766747556 ps
CPU time 1492.23 seconds
Started Jun 30 05:57:44 PM PDT 24
Finished Jun 30 06:22:37 PM PDT 24
Peak memory 373036 kb
Host smart-ff47cb5e-bc1d-48ba-af90-baae9cad76c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1589256573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1589256573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.883290165
Short name T785
Test name
Test status
Simulation time 56223424347 ps
CPU time 1224.21 seconds
Started Jun 30 05:57:49 PM PDT 24
Finished Jun 30 06:18:14 PM PDT 24
Peak memory 330348 kb
Host smart-a9da4df0-9fd2-4d98-988c-205c745bf9ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=883290165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.883290165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.2771246096
Short name T883
Test name
Test status
Simulation time 20205591623 ps
CPU time 811.78 seconds
Started Jun 30 05:57:50 PM PDT 24
Finished Jun 30 06:11:22 PM PDT 24
Peak memory 290876 kb
Host smart-f7d91477-c1a9-45a6-89ba-9a8ec49794ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2771246096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2771246096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.434398292
Short name T400
Test name
Test status
Simulation time 281840656871 ps
CPU time 4034.26 seconds
Started Jun 30 05:57:50 PM PDT 24
Finished Jun 30 07:05:05 PM PDT 24
Peak memory 649232 kb
Host smart-c94422cd-da00-4071-aa21-69a2cbee7a01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=434398292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.434398292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.714442069
Short name T731
Test name
Test status
Simulation time 1243219430814 ps
CPU time 4438.85 seconds
Started Jun 30 05:57:49 PM PDT 24
Finished Jun 30 07:11:49 PM PDT 24
Peak memory 554684 kb
Host smart-ccde5947-db66-4818-8ef1-fc7cc488d441
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=714442069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.714442069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.1971239330
Short name T751
Test name
Test status
Simulation time 270919320 ps
CPU time 0.85 seconds
Started Jun 30 05:58:15 PM PDT 24
Finished Jun 30 05:58:16 PM PDT 24
Peak memory 205632 kb
Host smart-4802135b-05d3-4efe-a32c-ab7270f17dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971239330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1971239330 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.721923032
Short name T507
Test name
Test status
Simulation time 8281054149 ps
CPU time 230.33 seconds
Started Jun 30 05:58:03 PM PDT 24
Finished Jun 30 06:01:54 PM PDT 24
Peak memory 242632 kb
Host smart-b2bb51ff-e7c9-43b6-9a5b-a5297471f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721923032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.721923032 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.109183970
Short name T272
Test name
Test status
Simulation time 31931838913 ps
CPU time 732.15 seconds
Started Jun 30 05:57:56 PM PDT 24
Finished Jun 30 06:10:09 PM PDT 24
Peak memory 233252 kb
Host smart-95696aee-8f58-426d-9a5a-bed722a0972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109183970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.109183970 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.1800956479
Short name T858
Test name
Test status
Simulation time 13107864539 ps
CPU time 97.67 seconds
Started Jun 30 05:58:02 PM PDT 24
Finished Jun 30 05:59:40 PM PDT 24
Peak memory 230984 kb
Host smart-3f54c051-1a1a-498e-aac8-c8855881b5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800956479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1800956479 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.291190408
Short name T725
Test name
Test status
Simulation time 6816827088 ps
CPU time 67 seconds
Started Jun 30 05:58:07 PM PDT 24
Finished Jun 30 05:59:15 PM PDT 24
Peak memory 233692 kb
Host smart-50eea6fb-ee3c-4725-aabb-23198cfa93e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291190408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.291190408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.3424995564
Short name T369
Test name
Test status
Simulation time 354489346 ps
CPU time 1.12 seconds
Started Jun 30 05:58:14 PM PDT 24
Finished Jun 30 05:58:15 PM PDT 24
Peak memory 207412 kb
Host smart-9cb2602a-e6e0-4668-b587-adde3d51a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424995564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3424995564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.826338935
Short name T52
Test name
Test status
Simulation time 78141568 ps
CPU time 1.08 seconds
Started Jun 30 05:58:15 PM PDT 24
Finished Jun 30 05:58:17 PM PDT 24
Peak memory 216080 kb
Host smart-350557ee-a51f-4b74-ade0-ef271a76b3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826338935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.826338935 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3483597523
Short name T475
Test name
Test status
Simulation time 15579494353 ps
CPU time 666.23 seconds
Started Jun 30 05:57:57 PM PDT 24
Finished Jun 30 06:09:03 PM PDT 24
Peak memory 287016 kb
Host smart-28633e68-e5db-4e25-81cd-b6923dc85f67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483597523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3483597523 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1419388496
Short name T346
Test name
Test status
Simulation time 1788750207 ps
CPU time 129.76 seconds
Started Jun 30 05:57:56 PM PDT 24
Finished Jun 30 06:00:06 PM PDT 24
Peak memory 232644 kb
Host smart-05ad44bf-9161-457c-9020-c70c5be7be74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419388496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1419388496 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.3173422330
Short name T650
Test name
Test status
Simulation time 5562553792 ps
CPU time 46.56 seconds
Started Jun 30 05:57:57 PM PDT 24
Finished Jun 30 05:58:44 PM PDT 24
Peak memory 221208 kb
Host smart-792a2ea0-09ce-4aa3-aa1c-7357f32177f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173422330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3173422330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.986580170
Short name T580
Test name
Test status
Simulation time 78694117028 ps
CPU time 1330.79 seconds
Started Jun 30 05:58:14 PM PDT 24
Finished Jun 30 06:20:26 PM PDT 24
Peak memory 395348 kb
Host smart-fc5f456c-4c18-4304-b18f-51c0a195e7dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=986580170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.986580170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.1770876333
Short name T816
Test name
Test status
Simulation time 819587419 ps
CPU time 4.54 seconds
Started Jun 30 05:58:04 PM PDT 24
Finished Jun 30 05:58:09 PM PDT 24
Peak memory 216096 kb
Host smart-313c0eea-45f6-46f1-bbc2-c05e2b44dc3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770876333 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.1770876333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3866132306
Short name T88
Test name
Test status
Simulation time 1505032912 ps
CPU time 5.15 seconds
Started Jun 30 05:58:03 PM PDT 24
Finished Jun 30 05:58:09 PM PDT 24
Peak memory 216084 kb
Host smart-d85e3b89-ab39-40cf-90dd-990dafa1a043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866132306 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3866132306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.2286252285
Short name T332
Test name
Test status
Simulation time 18511810101 ps
CPU time 1603.15 seconds
Started Jun 30 05:58:02 PM PDT 24
Finished Jun 30 06:24:46 PM PDT 24
Peak memory 378812 kb
Host smart-9585c137-5b5b-45ce-9b8a-701566ef76e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2286252285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2286252285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.1027817974
Short name T393
Test name
Test status
Simulation time 27168906125 ps
CPU time 1485.24 seconds
Started Jun 30 05:58:02 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 367244 kb
Host smart-a54aa10a-79f0-41ea-a8d0-f33f227a9991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1027817974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1027817974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.1696245666
Short name T217
Test name
Test status
Simulation time 106286195574 ps
CPU time 1392.42 seconds
Started Jun 30 05:58:02 PM PDT 24
Finished Jun 30 06:21:15 PM PDT 24
Peak memory 335248 kb
Host smart-e153c509-448e-4e8e-9f1f-5b0d6e88526f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1696245666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1696245666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2862454780
Short name T130
Test name
Test status
Simulation time 32660679120 ps
CPU time 845.66 seconds
Started Jun 30 05:58:01 PM PDT 24
Finished Jun 30 06:12:07 PM PDT 24
Peak memory 293636 kb
Host smart-f34fec76-29e3-425a-bacc-254012ae3105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2862454780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2862454780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1654679337
Short name T626
Test name
Test status
Simulation time 217502909750 ps
CPU time 4213.67 seconds
Started Jun 30 05:58:02 PM PDT 24
Finished Jun 30 07:08:17 PM PDT 24
Peak memory 555876 kb
Host smart-fac5266b-1575-43ad-94a6-d769a76a8876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1654679337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1654679337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3319856527
Short name T461
Test name
Test status
Simulation time 30198650 ps
CPU time 0.8 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 05:52:03 PM PDT 24
Peak memory 205652 kb
Host smart-8ae29134-12d8-4c25-a3f7-08eb43a53bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319856527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3319856527 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.4168276359
Short name T673
Test name
Test status
Simulation time 8571937100 ps
CPU time 79.28 seconds
Started Jun 30 05:51:54 PM PDT 24
Finished Jun 30 05:53:14 PM PDT 24
Peak memory 227036 kb
Host smart-5421ee02-670a-4c8a-a845-9963ba26d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168276359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.4168276359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.299251386
Short name T540
Test name
Test status
Simulation time 56747335403 ps
CPU time 265.51 seconds
Started Jun 30 05:51:52 PM PDT 24
Finished Jun 30 05:56:18 PM PDT 24
Peak memory 242668 kb
Host smart-b5b345c2-a299-413d-9964-66dfd48bf6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299251386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.299251386 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.1035880860
Short name T553
Test name
Test status
Simulation time 2111085420 ps
CPU time 162.46 seconds
Started Jun 30 05:51:53 PM PDT 24
Finished Jun 30 05:54:36 PM PDT 24
Peak memory 223648 kb
Host smart-374d6031-1301-4061-8c2d-a64e0d432462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035880860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1035880860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.1067032629
Short name T759
Test name
Test status
Simulation time 2069075028 ps
CPU time 9.32 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 05:52:10 PM PDT 24
Peak memory 224016 kb
Host smart-e6674d58-ae78-4d25-b584-e3c55e4dea77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1067032629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1067032629 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.1522159741
Short name T216
Test name
Test status
Simulation time 3213298851 ps
CPU time 29.79 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 05:52:32 PM PDT 24
Peak memory 224272 kb
Host smart-f169c25e-f3aa-4232-ab86-b71f964becbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522159741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1522159741 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1416880145
Short name T632
Test name
Test status
Simulation time 563207955 ps
CPU time 6.09 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 05:52:07 PM PDT 24
Peak memory 217168 kb
Host smart-37f73eb0-c257-47da-bc18-83f29c45ed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416880145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1416880145 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.2808251432
Short name T687
Test name
Test status
Simulation time 8589147928 ps
CPU time 174.14 seconds
Started Jun 30 05:51:57 PM PDT 24
Finished Jun 30 05:54:51 PM PDT 24
Peak memory 238160 kb
Host smart-d7ca1a4c-e4a6-4497-a0f9-0b50f2f9b5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808251432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.2808251432 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.4142993083
Short name T647
Test name
Test status
Simulation time 46911874705 ps
CPU time 237.2 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 05:55:59 PM PDT 24
Peak memory 248932 kb
Host smart-4a63d716-f090-4cf4-aa22-420272b97163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142993083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.4142993083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.3185476481
Short name T314
Test name
Test status
Simulation time 4357889077 ps
CPU time 7.41 seconds
Started Jun 30 05:52:03 PM PDT 24
Finished Jun 30 05:52:11 PM PDT 24
Peak memory 216080 kb
Host smart-a845bdfc-8fc9-42a8-8b80-a34c41fe2aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185476481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3185476481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.2508093548
Short name T860
Test name
Test status
Simulation time 45696569 ps
CPU time 1.24 seconds
Started Jun 30 05:52:03 PM PDT 24
Finished Jun 30 05:52:05 PM PDT 24
Peak memory 216112 kb
Host smart-1e43cee8-5039-4d8c-ad85-7833c2c5323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508093548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2508093548 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.551158857
Short name T462
Test name
Test status
Simulation time 15670802382 ps
CPU time 348.71 seconds
Started Jun 30 05:51:54 PM PDT 24
Finished Jun 30 05:57:43 PM PDT 24
Peak memory 257144 kb
Host smart-9c598a56-effc-45dc-9a01-4aab0987c693
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551158857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and
_output.551158857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.2692380190
Short name T424
Test name
Test status
Simulation time 1407367545 ps
CPU time 65.02 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 05:53:07 PM PDT 24
Peak memory 227220 kb
Host smart-ed13b325-ca1e-4237-bde8-768967866f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692380190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2692380190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.1762434116
Short name T60
Test name
Test status
Simulation time 19478567417 ps
CPU time 27.1 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 05:52:28 PM PDT 24
Peak memory 245760 kb
Host smart-ac331ae0-f80f-49dc-9968-d6ef35e9cf9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762434116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1762434116 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.830424223
Short name T315
Test name
Test status
Simulation time 3497391955 ps
CPU time 235.84 seconds
Started Jun 30 05:51:53 PM PDT 24
Finished Jun 30 05:55:50 PM PDT 24
Peak memory 244136 kb
Host smart-cf977e19-da08-406b-8c53-3b020ad8ec60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830424223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.830424223 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.4189585628
Short name T985
Test name
Test status
Simulation time 6937787833 ps
CPU time 30.81 seconds
Started Jun 30 05:51:54 PM PDT 24
Finished Jun 30 05:52:25 PM PDT 24
Peak memory 221816 kb
Host smart-47949c97-24f8-41a7-931a-cadc09ce8e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189585628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.4189585628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.4089507568
Short name T312
Test name
Test status
Simulation time 15212974744 ps
CPU time 115.14 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 05:53:57 PM PDT 24
Peak memory 240996 kb
Host smart-7e393aa1-92c7-4e36-a1ee-7a8fc2058bdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4089507568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.4089507568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.4224174985
Short name T241
Test name
Test status
Simulation time 67108869 ps
CPU time 3.77 seconds
Started Jun 30 05:51:53 PM PDT 24
Finished Jun 30 05:51:57 PM PDT 24
Peak memory 216140 kb
Host smart-db75ea75-7709-461b-bafb-443e7089c7a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224174985 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.4224174985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3013559226
Short name T938
Test name
Test status
Simulation time 259267575 ps
CPU time 3.9 seconds
Started Jun 30 05:51:52 PM PDT 24
Finished Jun 30 05:51:57 PM PDT 24
Peak memory 216148 kb
Host smart-9f1065aa-7ce1-42db-9507-c230813286db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013559226 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3013559226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.3696859391
Short name T302
Test name
Test status
Simulation time 636575595671 ps
CPU time 1909.9 seconds
Started Jun 30 05:51:53 PM PDT 24
Finished Jun 30 06:23:43 PM PDT 24
Peak memory 377736 kb
Host smart-b96e7426-c201-4b49-a3dd-1fa2a6a85d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3696859391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3696859391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.440199431
Short name T468
Test name
Test status
Simulation time 224745428218 ps
CPU time 1539.29 seconds
Started Jun 30 05:51:53 PM PDT 24
Finished Jun 30 06:17:33 PM PDT 24
Peak memory 379048 kb
Host smart-174f31fc-ea75-4b83-b8c8-7c7abd43d6a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=440199431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.440199431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.1267948813
Short name T18
Test name
Test status
Simulation time 73626482774 ps
CPU time 1338.95 seconds
Started Jun 30 05:51:54 PM PDT 24
Finished Jun 30 06:14:14 PM PDT 24
Peak memory 337484 kb
Host smart-13f5bc2a-38a6-4bda-8c27-41426ae60726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1267948813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1267948813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.1344952819
Short name T248
Test name
Test status
Simulation time 9665794569 ps
CPU time 800.57 seconds
Started Jun 30 05:51:57 PM PDT 24
Finished Jun 30 06:05:18 PM PDT 24
Peak memory 295172 kb
Host smart-ec6c1b78-3356-450b-94f2-d8feef9d5132
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1344952819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1344952819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.2774028455
Short name T594
Test name
Test status
Simulation time 294761083935 ps
CPU time 4182.97 seconds
Started Jun 30 05:51:55 PM PDT 24
Finished Jun 30 07:01:39 PM PDT 24
Peak memory 635968 kb
Host smart-cf999e02-51a8-4a38-9075-e1fbf64f5860
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2774028455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2774028455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.1514780307
Short name T853
Test name
Test status
Simulation time 175445685257 ps
CPU time 3333.04 seconds
Started Jun 30 05:51:53 PM PDT 24
Finished Jun 30 06:47:26 PM PDT 24
Peak memory 573296 kb
Host smart-06b8d9a1-8799-4a8a-9dc2-7e3881556662
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1514780307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1514780307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.464566587
Short name T274
Test name
Test status
Simulation time 43550429 ps
CPU time 0.78 seconds
Started Jun 30 05:58:34 PM PDT 24
Finished Jun 30 05:58:35 PM PDT 24
Peak memory 205644 kb
Host smart-7de8c641-82af-427b-9ef4-5735eb002bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464566587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.464566587 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.4239235739
Short name T828
Test name
Test status
Simulation time 25646525858 ps
CPU time 131.35 seconds
Started Jun 30 05:58:27 PM PDT 24
Finished Jun 30 06:00:38 PM PDT 24
Peak memory 232840 kb
Host smart-0c969ed5-0b17-4daa-a641-3b6867fc2ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239235739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.4239235739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.3604313177
Short name T584
Test name
Test status
Simulation time 30655932981 ps
CPU time 238.57 seconds
Started Jun 30 05:58:15 PM PDT 24
Finished Jun 30 06:02:14 PM PDT 24
Peak memory 225912 kb
Host smart-df778835-3a7e-4c1d-b234-822235f10acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604313177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3604313177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.584712706
Short name T357
Test name
Test status
Simulation time 20576659805 ps
CPU time 306.82 seconds
Started Jun 30 05:58:35 PM PDT 24
Finished Jun 30 06:03:42 PM PDT 24
Peak memory 246132 kb
Host smart-6c6a7e7b-bb8f-483b-b850-15ffd19f2bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584712706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.584712706 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.315802431
Short name T1053
Test name
Test status
Simulation time 2594785782 ps
CPU time 96.31 seconds
Started Jun 30 05:58:35 PM PDT 24
Finished Jun 30 06:00:12 PM PDT 24
Peak memory 240948 kb
Host smart-6e380300-28a9-40ea-ad2f-647ac7112256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315802431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.315802431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.1699426572
Short name T813
Test name
Test status
Simulation time 1513496595 ps
CPU time 4.15 seconds
Started Jun 30 05:58:34 PM PDT 24
Finished Jun 30 05:58:38 PM PDT 24
Peak memory 216032 kb
Host smart-f7a0a7d1-0286-4343-a2f2-ad42cc67b255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699426572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1699426572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.1420819882
Short name T855
Test name
Test status
Simulation time 148474754 ps
CPU time 1.35 seconds
Started Jun 30 05:58:34 PM PDT 24
Finished Jun 30 05:58:36 PM PDT 24
Peak memory 216264 kb
Host smart-83506498-9666-49ab-805b-2f3cfc049e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420819882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1420819882 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.3384102947
Short name T365
Test name
Test status
Simulation time 1560269228 ps
CPU time 37.12 seconds
Started Jun 30 05:58:16 PM PDT 24
Finished Jun 30 05:58:53 PM PDT 24
Peak memory 222076 kb
Host smart-05be0820-8bd3-491c-9cf1-869a1d0bb92d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384102947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.3384102947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.3659690896
Short name T697
Test name
Test status
Simulation time 4536348517 ps
CPU time 324.83 seconds
Started Jun 30 05:58:15 PM PDT 24
Finished Jun 30 06:03:40 PM PDT 24
Peak memory 251104 kb
Host smart-753fbe33-da10-48b2-a0db-77fcaa3821d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659690896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3659690896 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.92916167
Short name T67
Test name
Test status
Simulation time 2912355811 ps
CPU time 29.27 seconds
Started Jun 30 05:58:15 PM PDT 24
Finished Jun 30 05:58:44 PM PDT 24
Peak memory 224380 kb
Host smart-97a80340-4273-4735-990e-97f0ceea7055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92916167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.92916167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.2484279334
Short name T971
Test name
Test status
Simulation time 30505670943 ps
CPU time 321.43 seconds
Started Jun 30 05:58:34 PM PDT 24
Finished Jun 30 06:03:56 PM PDT 24
Peak memory 290148 kb
Host smart-c0e9b29f-9e27-4eb8-a4f1-6c1db5715227
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2484279334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2484279334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.3953806595
Short name T603
Test name
Test status
Simulation time 185033392 ps
CPU time 4.88 seconds
Started Jun 30 05:58:28 PM PDT 24
Finished Jun 30 05:58:33 PM PDT 24
Peak memory 216164 kb
Host smart-13f3173d-1f2f-46d4-863e-63b1c76e32d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953806595 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.3953806595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1081427514
Short name T608
Test name
Test status
Simulation time 66117807 ps
CPU time 3.88 seconds
Started Jun 30 05:58:29 PM PDT 24
Finished Jun 30 05:58:33 PM PDT 24
Peak memory 216188 kb
Host smart-3f94ffb1-7f71-4a55-9953-6f943cc20a71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081427514 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1081427514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.3183210021
Short name T899
Test name
Test status
Simulation time 1054248197200 ps
CPU time 1949.51 seconds
Started Jun 30 05:58:14 PM PDT 24
Finished Jun 30 06:30:44 PM PDT 24
Peak memory 376628 kb
Host smart-83045dd6-e78a-49b6-93cd-0f603959318a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3183210021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3183210021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.4092512079
Short name T631
Test name
Test status
Simulation time 160467005462 ps
CPU time 1733.81 seconds
Started Jun 30 05:58:21 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 378884 kb
Host smart-e8833f84-080f-4221-b2e3-a4352af451a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4092512079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.4092512079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.1142056912
Short name T17
Test name
Test status
Simulation time 49165248722 ps
CPU time 1266.08 seconds
Started Jun 30 05:58:23 PM PDT 24
Finished Jun 30 06:19:29 PM PDT 24
Peak memory 337308 kb
Host smart-dc11571d-03f0-4a88-91be-ee6745f94c02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1142056912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.1142056912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1242598420
Short name T449
Test name
Test status
Simulation time 85119009533 ps
CPU time 866.31 seconds
Started Jun 30 05:58:22 PM PDT 24
Finished Jun 30 06:12:48 PM PDT 24
Peak memory 289020 kb
Host smart-7ad91d7a-6acd-421d-a41b-9537f676a517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1242598420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1242598420 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.1356197753
Short name T212
Test name
Test status
Simulation time 282741340558 ps
CPU time 3950.75 seconds
Started Jun 30 05:58:20 PM PDT 24
Finished Jun 30 07:04:11 PM PDT 24
Peak memory 651880 kb
Host smart-f3482362-c63c-44ab-ad53-c7f77bb33a2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1356197753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.1356197753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.468930026
Short name T679
Test name
Test status
Simulation time 223718932081 ps
CPU time 4243.03 seconds
Started Jun 30 05:58:21 PM PDT 24
Finished Jun 30 07:09:05 PM PDT 24
Peak memory 553924 kb
Host smart-b7b537e3-c72e-4368-94ce-7ea693a43b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=468930026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.468930026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.441465041
Short name T1029
Test name
Test status
Simulation time 96863863 ps
CPU time 0.84 seconds
Started Jun 30 05:59:04 PM PDT 24
Finished Jun 30 05:59:05 PM PDT 24
Peak memory 205552 kb
Host smart-e6f4e0fa-b125-43fe-8845-cdbfcd7cfae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441465041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.441465041 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2164826669
Short name T68
Test name
Test status
Simulation time 11782087787 ps
CPU time 109.22 seconds
Started Jun 30 05:58:52 PM PDT 24
Finished Jun 30 06:00:42 PM PDT 24
Peak memory 231744 kb
Host smart-73cdc812-9825-4bc0-9f93-2de948fbc042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164826669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2164826669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.74426511
Short name T143
Test name
Test status
Simulation time 31432167013 ps
CPU time 721.85 seconds
Started Jun 30 05:58:40 PM PDT 24
Finished Jun 30 06:10:43 PM PDT 24
Peak memory 232112 kb
Host smart-3bc04da0-6222-45d7-9c9c-27ceb2a25f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74426511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.74426511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_error.1811142190
Short name T42
Test name
Test status
Simulation time 2833161453 ps
CPU time 207.84 seconds
Started Jun 30 05:58:52 PM PDT 24
Finished Jun 30 06:02:20 PM PDT 24
Peak memory 252392 kb
Host smart-32f00a50-5d67-4032-bde6-62ceb20d2cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811142190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1811142190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.2889645347
Short name T354
Test name
Test status
Simulation time 795967685 ps
CPU time 4.63 seconds
Started Jun 30 05:58:52 PM PDT 24
Finished Jun 30 05:58:57 PM PDT 24
Peak memory 207856 kb
Host smart-c64c306d-5603-4b6c-a0da-3e8740c89b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889645347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2889645347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.2641863083
Short name T173
Test name
Test status
Simulation time 152886969 ps
CPU time 1.29 seconds
Started Jun 30 05:58:53 PM PDT 24
Finished Jun 30 05:58:54 PM PDT 24
Peak memory 216032 kb
Host smart-01e9d76b-10b5-41ea-bf6c-498ed3e330a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641863083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2641863083 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.2736679768
Short name T278
Test name
Test status
Simulation time 628846416 ps
CPU time 7.87 seconds
Started Jun 30 05:58:35 PM PDT 24
Finished Jun 30 05:58:43 PM PDT 24
Peak memory 216132 kb
Host smart-c5ad0c6a-ea20-4122-8912-c7dd4bee92bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736679768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.2736679768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2366057248
Short name T944
Test name
Test status
Simulation time 8422254998 ps
CPU time 336.25 seconds
Started Jun 30 05:58:35 PM PDT 24
Finished Jun 30 06:04:12 PM PDT 24
Peak memory 250964 kb
Host smart-0e1d688d-8521-4c8b-82e4-37c525b67248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366057248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2366057248 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.2353281484
Short name T635
Test name
Test status
Simulation time 1027374049 ps
CPU time 7.08 seconds
Started Jun 30 05:58:33 PM PDT 24
Finished Jun 30 05:58:41 PM PDT 24
Peak memory 219360 kb
Host smart-454bfa76-59ef-43b3-abee-476cc8c9ff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353281484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2353281484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.441218091
Short name T891
Test name
Test status
Simulation time 21143023717 ps
CPU time 582.8 seconds
Started Jun 30 05:58:58 PM PDT 24
Finished Jun 30 06:08:41 PM PDT 24
Peak memory 306292 kb
Host smart-49294951-bc69-477a-92ff-2ff263ece763
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=441218091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.441218091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.1289243068
Short name T299
Test name
Test status
Simulation time 412215900 ps
CPU time 4.2 seconds
Started Jun 30 05:58:51 PM PDT 24
Finished Jun 30 05:58:55 PM PDT 24
Peak memory 216184 kb
Host smart-2e38d687-7c51-4e83-879d-e1fcc40aaab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289243068 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.1289243068 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2431121226
Short name T840
Test name
Test status
Simulation time 1010986030 ps
CPU time 5.03 seconds
Started Jun 30 05:58:50 PM PDT 24
Finished Jun 30 05:58:56 PM PDT 24
Peak memory 216136 kb
Host smart-92848662-4fde-485d-b7c2-c97dc765d7d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431121226 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2431121226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.3274847235
Short name T1072
Test name
Test status
Simulation time 19925473821 ps
CPU time 1548.46 seconds
Started Jun 30 05:58:40 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 392772 kb
Host smart-f0d48777-a9eb-41e2-aaa7-c76e7ed66eb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3274847235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.3274847235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.2086531048
Short name T69
Test name
Test status
Simulation time 83336683397 ps
CPU time 1619.12 seconds
Started Jun 30 05:58:46 PM PDT 24
Finished Jun 30 06:25:45 PM PDT 24
Peak memory 394188 kb
Host smart-7ee65cbd-b68f-4410-8524-f4a4b94f9b54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2086531048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.2086531048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2230699394
Short name T747
Test name
Test status
Simulation time 255206545193 ps
CPU time 1380.18 seconds
Started Jun 30 05:58:48 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 336556 kb
Host smart-a523b8b5-a8ad-48f5-a363-8587552c67bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2230699394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2230699394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.2770933632
Short name T1076
Test name
Test status
Simulation time 63826264930 ps
CPU time 890.51 seconds
Started Jun 30 05:58:45 PM PDT 24
Finished Jun 30 06:13:36 PM PDT 24
Peak memory 291320 kb
Host smart-dc8118ad-698d-4c02-8a09-b9a6e353de18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2770933632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.2770933632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.2109712613
Short name T1071
Test name
Test status
Simulation time 232533843745 ps
CPU time 4863.91 seconds
Started Jun 30 05:58:46 PM PDT 24
Finished Jun 30 07:19:51 PM PDT 24
Peak memory 653160 kb
Host smart-f80defe0-ef40-46f6-9e5b-5b8091d3e361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2109712613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.2109712613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2463666587
Short name T886
Test name
Test status
Simulation time 150245528114 ps
CPU time 3952.22 seconds
Started Jun 30 05:58:48 PM PDT 24
Finished Jun 30 07:04:41 PM PDT 24
Peak memory 564444 kb
Host smart-9a3adb97-d854-4cd4-af81-103432627344
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2463666587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2463666587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.268526868
Short name T285
Test name
Test status
Simulation time 18101359 ps
CPU time 0.76 seconds
Started Jun 30 05:59:31 PM PDT 24
Finished Jun 30 05:59:33 PM PDT 24
Peak memory 205632 kb
Host smart-e27a9d7f-8a29-4f93-87b0-acac672a979d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268526868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.268526868 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2636882096
Short name T506
Test name
Test status
Simulation time 1638866228 ps
CPU time 30.6 seconds
Started Jun 30 05:59:17 PM PDT 24
Finished Jun 30 05:59:48 PM PDT 24
Peak memory 219484 kb
Host smart-d514ab82-f85f-4925-801e-ecc7cd4a0d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636882096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2636882096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.3996491903
Short name T1057
Test name
Test status
Simulation time 9344508224 ps
CPU time 103.84 seconds
Started Jun 30 05:59:17 PM PDT 24
Finished Jun 30 06:01:01 PM PDT 24
Peak memory 232048 kb
Host smart-b247d0a2-bc18-4007-bb6f-0d76dd3ffb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996491903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3996491903 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.3421637601
Short name T27
Test name
Test status
Simulation time 5923648236 ps
CPU time 121.38 seconds
Started Jun 30 05:59:16 PM PDT 24
Finished Jun 30 06:01:17 PM PDT 24
Peak memory 240824 kb
Host smart-d24c6fd5-25b9-4a26-97b7-9d6eb2d583c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421637601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3421637601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3513696800
Short name T82
Test name
Test status
Simulation time 96650709 ps
CPU time 1.24 seconds
Started Jun 30 05:59:31 PM PDT 24
Finished Jun 30 05:59:32 PM PDT 24
Peak memory 216144 kb
Host smart-4b790b7a-f0c1-4574-bc6a-ec4e36b84175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513696800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3513696800 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.2195164577
Short name T244
Test name
Test status
Simulation time 7558022166 ps
CPU time 313.94 seconds
Started Jun 30 05:59:04 PM PDT 24
Finished Jun 30 06:04:18 PM PDT 24
Peak memory 252184 kb
Host smart-47df32fd-9eec-4e82-8569-38dcd27d85a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195164577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.2195164577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.15831267
Short name T885
Test name
Test status
Simulation time 2481446110 ps
CPU time 44.1 seconds
Started Jun 30 05:59:10 PM PDT 24
Finished Jun 30 05:59:54 PM PDT 24
Peak memory 223312 kb
Host smart-159bd17e-f1ea-4126-9835-28dd0a32f8d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15831267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.15831267 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.647803921
Short name T251
Test name
Test status
Simulation time 4794471325 ps
CPU time 44.13 seconds
Started Jun 30 05:59:04 PM PDT 24
Finished Jun 30 05:59:49 PM PDT 24
Peak memory 219972 kb
Host smart-9b2e3324-364e-4569-9bb8-5e9f892b3693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647803921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.647803921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.3788919041
Short name T700
Test name
Test status
Simulation time 924386456 ps
CPU time 16.73 seconds
Started Jun 30 05:59:30 PM PDT 24
Finished Jun 30 05:59:47 PM PDT 24
Peak memory 223176 kb
Host smart-2f9960d0-bb79-4b9c-b92c-1c489da42ee5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3788919041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3788919041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.3475700367
Short name T854
Test name
Test status
Simulation time 1209401023 ps
CPU time 4.93 seconds
Started Jun 30 05:59:16 PM PDT 24
Finished Jun 30 05:59:22 PM PDT 24
Peak memory 216164 kb
Host smart-78226ceb-c3eb-47b2-8f1b-08fed09ed1e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475700367 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.3475700367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2891331701
Short name T646
Test name
Test status
Simulation time 140172071 ps
CPU time 4.41 seconds
Started Jun 30 05:59:17 PM PDT 24
Finished Jun 30 05:59:22 PM PDT 24
Peak memory 216136 kb
Host smart-579b61d9-fb2a-4c3f-811a-5aeb11bbdb5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891331701 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2891331701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.1883910993
Short name T835
Test name
Test status
Simulation time 140062842330 ps
CPU time 1856.74 seconds
Started Jun 30 05:59:11 PM PDT 24
Finished Jun 30 06:30:08 PM PDT 24
Peak memory 397088 kb
Host smart-230b4be8-f7fc-4229-81fc-ea62abf3bc1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1883910993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1883910993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.3539062264
Short name T907
Test name
Test status
Simulation time 68563656305 ps
CPU time 1557.09 seconds
Started Jun 30 05:59:11 PM PDT 24
Finished Jun 30 06:25:09 PM PDT 24
Peak memory 375772 kb
Host smart-7112050b-c9df-41d6-b7b3-fd97c6c271ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3539062264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3539062264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3890608166
Short name T894
Test name
Test status
Simulation time 48311845029 ps
CPU time 1336.97 seconds
Started Jun 30 05:59:11 PM PDT 24
Finished Jun 30 06:21:28 PM PDT 24
Peak memory 336912 kb
Host smart-67d616dc-fbe4-4b75-a1dd-b5c78132e038
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3890608166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3890608166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.1882583222
Short name T712
Test name
Test status
Simulation time 67012215685 ps
CPU time 946.45 seconds
Started Jun 30 05:59:16 PM PDT 24
Finished Jun 30 06:15:03 PM PDT 24
Peak memory 296680 kb
Host smart-689789f1-d48f-43a3-8070-76eafda90a8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1882583222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.1882583222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.685908890
Short name T991
Test name
Test status
Simulation time 3625517288145 ps
CPU time 5599.77 seconds
Started Jun 30 05:59:16 PM PDT 24
Finished Jun 30 07:32:37 PM PDT 24
Peak memory 565648 kb
Host smart-5a40ef8e-af4e-4fb9-b824-7f4c85c2e695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=685908890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.685908890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.90320469
Short name T290
Test name
Test status
Simulation time 92896124 ps
CPU time 0.82 seconds
Started Jun 30 05:59:49 PM PDT 24
Finished Jun 30 05:59:50 PM PDT 24
Peak memory 205580 kb
Host smart-ad32f916-2d65-4910-9eaa-91618aa75639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90320469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.90320469 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.223837197
Short name T820
Test name
Test status
Simulation time 2639546780 ps
CPU time 42.01 seconds
Started Jun 30 05:59:35 PM PDT 24
Finished Jun 30 06:00:17 PM PDT 24
Peak memory 222320 kb
Host smart-3c3cf6d9-7df6-424c-9711-a0e2d01fa8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223837197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.223837197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3022356850
Short name T501
Test name
Test status
Simulation time 59311930696 ps
CPU time 577.99 seconds
Started Jun 30 05:59:32 PM PDT 24
Finished Jun 30 06:09:10 PM PDT 24
Peak memory 231520 kb
Host smart-af6e4842-0a18-4460-80f6-7b0e7e56ff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022356850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3022356850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.816445030
Short name T1042
Test name
Test status
Simulation time 16978935809 ps
CPU time 154.02 seconds
Started Jun 30 05:59:41 PM PDT 24
Finished Jun 30 06:02:16 PM PDT 24
Peak memory 237340 kb
Host smart-f6bd211e-0f47-4114-82fc-41cfcb940453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816445030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.816445030 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1207544825
Short name T164
Test name
Test status
Simulation time 114853042647 ps
CPU time 355.11 seconds
Started Jun 30 05:59:40 PM PDT 24
Finished Jun 30 06:05:36 PM PDT 24
Peak memory 256860 kb
Host smart-e0ab6dab-16f4-485a-a44c-2681eb6c77e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207544825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1207544825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.887624712
Short name T565
Test name
Test status
Simulation time 925536303 ps
CPU time 4.68 seconds
Started Jun 30 05:59:40 PM PDT 24
Finished Jun 30 05:59:45 PM PDT 24
Peak memory 207852 kb
Host smart-405eb8fd-51b4-4e8e-830e-224eddbc8671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887624712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.887624712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.1539584074
Short name T85
Test name
Test status
Simulation time 147653518 ps
CPU time 1.35 seconds
Started Jun 30 05:59:40 PM PDT 24
Finished Jun 30 05:59:42 PM PDT 24
Peak memory 216024 kb
Host smart-b2717d94-d0bc-419d-bbee-c4b7c67702e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539584074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1539584074 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.4266869121
Short name T319
Test name
Test status
Simulation time 543231790976 ps
CPU time 2182.97 seconds
Started Jun 30 05:59:31 PM PDT 24
Finished Jun 30 06:35:54 PM PDT 24
Peak memory 431812 kb
Host smart-ca82cbd1-4259-4634-b288-1d162e4f6cd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266869121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.4266869121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.3737023130
Short name T1040
Test name
Test status
Simulation time 18968589004 ps
CPU time 382.66 seconds
Started Jun 30 05:59:30 PM PDT 24
Finished Jun 30 06:05:53 PM PDT 24
Peak memory 248476 kb
Host smart-eb3fc027-069a-47ff-ab90-6e53f1072f94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737023130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3737023130 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.3726198055
Short name T284
Test name
Test status
Simulation time 16678230865 ps
CPU time 67.4 seconds
Started Jun 30 05:59:30 PM PDT 24
Finished Jun 30 06:00:37 PM PDT 24
Peak memory 219832 kb
Host smart-f504f1f4-5343-42ef-8992-ec999aa1d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726198055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3726198055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.895828664
Short name T22
Test name
Test status
Simulation time 95556406771 ps
CPU time 266.86 seconds
Started Jun 30 05:59:41 PM PDT 24
Finished Jun 30 06:04:08 PM PDT 24
Peak memory 257388 kb
Host smart-377a64aa-fb52-4e87-a5d1-25561dcb571f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=895828664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.895828664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.3683632471
Short name T378
Test name
Test status
Simulation time 254481982 ps
CPU time 5.22 seconds
Started Jun 30 05:59:34 PM PDT 24
Finished Jun 30 05:59:40 PM PDT 24
Peak memory 216176 kb
Host smart-58778155-1305-4c36-8582-1e4da37242f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683632471 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.3683632471 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1849384163
Short name T744
Test name
Test status
Simulation time 501870645 ps
CPU time 5.04 seconds
Started Jun 30 05:59:35 PM PDT 24
Finished Jun 30 05:59:40 PM PDT 24
Peak memory 216220 kb
Host smart-2c26460c-3b86-4720-af82-5d084d64bd8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849384163 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1849384163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.4087124382
Short name T480
Test name
Test status
Simulation time 100832364453 ps
CPU time 2002.52 seconds
Started Jun 30 05:59:30 PM PDT 24
Finished Jun 30 06:32:53 PM PDT 24
Peak memory 391288 kb
Host smart-0210e933-3cde-4d87-b370-cd6c4edee47f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4087124382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.4087124382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.4160981846
Short name T620
Test name
Test status
Simulation time 683926078340 ps
CPU time 1682.95 seconds
Started Jun 30 05:59:30 PM PDT 24
Finished Jun 30 06:27:33 PM PDT 24
Peak memory 377504 kb
Host smart-3e0a00e0-513a-4b19-97c2-4eba0d9789e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4160981846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.4160981846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.1051461947
Short name T738
Test name
Test status
Simulation time 245875063584 ps
CPU time 1252.01 seconds
Started Jun 30 05:59:31 PM PDT 24
Finished Jun 30 06:20:24 PM PDT 24
Peak memory 333820 kb
Host smart-b1a6f502-2beb-47df-94bf-1d56a38bb0da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1051461947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.1051461947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.211832992
Short name T904
Test name
Test status
Simulation time 143023993875 ps
CPU time 1022.51 seconds
Started Jun 30 05:59:35 PM PDT 24
Finished Jun 30 06:16:38 PM PDT 24
Peak memory 294820 kb
Host smart-47345542-6c16-4eb7-9981-59cdd116da79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=211832992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.211832992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.2957359019
Short name T1034
Test name
Test status
Simulation time 223248213905 ps
CPU time 4685.15 seconds
Started Jun 30 05:59:36 PM PDT 24
Finished Jun 30 07:17:42 PM PDT 24
Peak memory 641780 kb
Host smart-2fac313e-bcda-408b-aeac-102889ea6c4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2957359019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.2957359019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.2606316255
Short name T768
Test name
Test status
Simulation time 175825238659 ps
CPU time 3373.03 seconds
Started Jun 30 05:59:35 PM PDT 24
Finished Jun 30 06:55:49 PM PDT 24
Peak memory 574788 kb
Host smart-fab68981-2cc0-42b0-b5e7-88c6a8d702fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2606316255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2606316255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.1472135907
Short name T818
Test name
Test status
Simulation time 149239284 ps
CPU time 0.84 seconds
Started Jun 30 06:00:20 PM PDT 24
Finished Jun 30 06:00:21 PM PDT 24
Peak memory 205612 kb
Host smart-c97acccd-c042-4a1a-9dc4-0943b20898f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472135907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1472135907 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.2136747460
Short name T541
Test name
Test status
Simulation time 15932869503 ps
CPU time 60.06 seconds
Started Jun 30 06:00:13 PM PDT 24
Finished Jun 30 06:01:14 PM PDT 24
Peak memory 224572 kb
Host smart-004163e8-fb8a-40df-bdd2-81d9b89f3ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136747460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.2136747460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.332792321
Short name T1020
Test name
Test status
Simulation time 33063023660 ps
CPU time 98.29 seconds
Started Jun 30 05:59:54 PM PDT 24
Finished Jun 30 06:01:33 PM PDT 24
Peak memory 222748 kb
Host smart-6b6ef771-bd26-4536-b2a8-9eaad3d02998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332792321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.332792321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.3480960378
Short name T391
Test name
Test status
Simulation time 14102279513 ps
CPU time 255.94 seconds
Started Jun 30 06:00:13 PM PDT 24
Finished Jun 30 06:04:29 PM PDT 24
Peak memory 243032 kb
Host smart-2586c5c6-34d0-4dc0-8697-afb15ae8f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480960378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3480960378 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.854759317
Short name T28
Test name
Test status
Simulation time 47282659668 ps
CPU time 341.44 seconds
Started Jun 30 06:00:12 PM PDT 24
Finished Jun 30 06:05:54 PM PDT 24
Peak memory 257136 kb
Host smart-fbf3d697-5496-4e40-a7f4-a4a739c53dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854759317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.854759317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.3527651713
Short name T476
Test name
Test status
Simulation time 1557222578 ps
CPU time 7.4 seconds
Started Jun 30 06:00:13 PM PDT 24
Finished Jun 30 06:00:20 PM PDT 24
Peak memory 216132 kb
Host smart-cf83fa5f-e98d-4f5b-9f94-dc5be1a3c86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527651713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3527651713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.4071527607
Short name T872
Test name
Test status
Simulation time 52154098 ps
CPU time 1.44 seconds
Started Jun 30 06:00:20 PM PDT 24
Finished Jun 30 06:00:22 PM PDT 24
Peak memory 220892 kb
Host smart-43d683ea-55dd-44ab-bb0b-89b96f2eb931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071527607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4071527607 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.3651857599
Short name T128
Test name
Test status
Simulation time 15021642731 ps
CPU time 289.64 seconds
Started Jun 30 05:59:48 PM PDT 24
Finished Jun 30 06:04:38 PM PDT 24
Peak memory 243228 kb
Host smart-3a7cdcac-e268-401d-9051-62d1224cd520
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651857599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.3651857599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.583662392
Short name T821
Test name
Test status
Simulation time 17553847368 ps
CPU time 94.35 seconds
Started Jun 30 05:59:56 PM PDT 24
Finished Jun 30 06:01:30 PM PDT 24
Peak memory 227868 kb
Host smart-79a18d9a-6259-4247-ad91-f88c761d8b8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583662392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.583662392 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.1277640940
Short name T556
Test name
Test status
Simulation time 4789002851 ps
CPU time 22.83 seconds
Started Jun 30 05:59:48 PM PDT 24
Finished Jun 30 06:00:11 PM PDT 24
Peak memory 216196 kb
Host smart-8f09cddc-8686-49ac-a33b-cb20f0200cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277640940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1277640940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.2571165257
Short name T490
Test name
Test status
Simulation time 315453926377 ps
CPU time 1484.58 seconds
Started Jun 30 06:00:20 PM PDT 24
Finished Jun 30 06:25:06 PM PDT 24
Peak memory 388732 kb
Host smart-022772a6-ac0b-4e39-b183-b816b7ae9d46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2571165257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2571165257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.3873165311
Short name T842
Test name
Test status
Simulation time 241732530 ps
CPU time 4.83 seconds
Started Jun 30 06:00:12 PM PDT 24
Finished Jun 30 06:00:17 PM PDT 24
Peak memory 216128 kb
Host smart-44de4b82-e5d0-4d4e-b24e-66288dc503ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873165311 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.3873165311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.1281117581
Short name T805
Test name
Test status
Simulation time 924776858 ps
CPU time 4.81 seconds
Started Jun 30 06:00:12 PM PDT 24
Finished Jun 30 06:00:18 PM PDT 24
Peak memory 216132 kb
Host smart-91092972-3423-4ef4-a018-13e4c6556efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281117581 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.1281117581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.2978771037
Short name T362
Test name
Test status
Simulation time 135022402347 ps
CPU time 1858.11 seconds
Started Jun 30 05:59:56 PM PDT 24
Finished Jun 30 06:30:54 PM PDT 24
Peak memory 391300 kb
Host smart-96a7f769-f5f4-4ab2-9207-a65eabc6465c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2978771037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.2978771037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.4029165705
Short name T194
Test name
Test status
Simulation time 185274394691 ps
CPU time 1730 seconds
Started Jun 30 06:00:01 PM PDT 24
Finished Jun 30 06:28:51 PM PDT 24
Peak memory 374252 kb
Host smart-a0bcbe6d-5436-4610-bb31-b87cf4b6950c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4029165705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.4029165705 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.3347576670
Short name T876
Test name
Test status
Simulation time 25759346033 ps
CPU time 1115.53 seconds
Started Jun 30 06:00:00 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 331012 kb
Host smart-9f3fbe77-98e5-4a69-80f6-b23d0b5da52b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3347576670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3347576670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1922330503
Short name T296
Test name
Test status
Simulation time 19090846705 ps
CPU time 758.93 seconds
Started Jun 30 05:59:59 PM PDT 24
Finished Jun 30 06:12:38 PM PDT 24
Peak memory 296480 kb
Host smart-36d9c33b-2968-419b-bb2b-689fb276579f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1922330503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1922330503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.1866782020
Short name T288
Test name
Test status
Simulation time 254343178755 ps
CPU time 4569.41 seconds
Started Jun 30 05:59:59 PM PDT 24
Finished Jun 30 07:16:09 PM PDT 24
Peak memory 634764 kb
Host smart-7475c296-0008-4fac-a21a-f6adf498bfcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1866782020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.1866782020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.2401834192
Short name T160
Test name
Test status
Simulation time 43039203031 ps
CPU time 3222.88 seconds
Started Jun 30 06:00:06 PM PDT 24
Finished Jun 30 06:53:49 PM PDT 24
Peak memory 547848 kb
Host smart-ae71ddfd-f6b8-4f9d-a8f6-3ce3e63df1cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2401834192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2401834192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.1293116552
Short name T645
Test name
Test status
Simulation time 23056095 ps
CPU time 0.79 seconds
Started Jun 30 06:00:43 PM PDT 24
Finished Jun 30 06:00:44 PM PDT 24
Peak memory 205624 kb
Host smart-9a49bf51-cbf2-4648-a26e-393713feffae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293116552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1293116552 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.41193596
Short name T276
Test name
Test status
Simulation time 11637155634 ps
CPU time 224.3 seconds
Started Jun 30 06:00:34 PM PDT 24
Finished Jun 30 06:04:18 PM PDT 24
Peak memory 241132 kb
Host smart-b9dd3345-72e4-4626-b0a8-1412df451e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41193596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.41193596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3721116521
Short name T612
Test name
Test status
Simulation time 5366930547 ps
CPU time 43.76 seconds
Started Jun 30 06:00:20 PM PDT 24
Finished Jun 30 06:01:04 PM PDT 24
Peak memory 218528 kb
Host smart-18107c09-96d5-45d2-ae34-589a76c7a92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721116521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3721116521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.3508404339
Short name T21
Test name
Test status
Simulation time 14020659732 ps
CPU time 144.95 seconds
Started Jun 30 06:00:33 PM PDT 24
Finished Jun 30 06:02:59 PM PDT 24
Peak memory 238656 kb
Host smart-3be3c0de-f1cb-452c-be16-a086a4978831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508404339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3508404339 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.282800534
Short name T471
Test name
Test status
Simulation time 1357320632 ps
CPU time 98.54 seconds
Started Jun 30 06:00:33 PM PDT 24
Finished Jun 30 06:02:12 PM PDT 24
Peak memory 240824 kb
Host smart-10d16f94-efdb-4639-aabb-4f4cb9ed6890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282800534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.282800534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.192309335
Short name T1
Test name
Test status
Simulation time 2741531220 ps
CPU time 6.87 seconds
Started Jun 30 06:00:41 PM PDT 24
Finished Jun 30 06:00:48 PM PDT 24
Peak memory 207940 kb
Host smart-8279343a-ee9f-4412-b33b-0c0f473d5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192309335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.192309335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.75030246
Short name T812
Test name
Test status
Simulation time 48506546 ps
CPU time 1.39 seconds
Started Jun 30 06:00:41 PM PDT 24
Finished Jun 30 06:00:43 PM PDT 24
Peak memory 216128 kb
Host smart-01c3922c-ff2e-4a46-b12f-5e4fe998c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75030246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.75030246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3740773222
Short name T295
Test name
Test status
Simulation time 10442495419 ps
CPU time 228.2 seconds
Started Jun 30 06:00:20 PM PDT 24
Finished Jun 30 06:04:09 PM PDT 24
Peak memory 236268 kb
Host smart-9c7945d8-7d71-4b80-aae3-853ce827a39f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740773222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3740773222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.2145103743
Short name T325
Test name
Test status
Simulation time 6865748514 ps
CPU time 196.85 seconds
Started Jun 30 06:00:19 PM PDT 24
Finished Jun 30 06:03:36 PM PDT 24
Peak memory 234840 kb
Host smart-be168843-e2e5-4973-8611-7c980134aeed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145103743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2145103743 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.3436008842
Short name T294
Test name
Test status
Simulation time 174601768 ps
CPU time 4.74 seconds
Started Jun 30 06:00:19 PM PDT 24
Finished Jun 30 06:00:24 PM PDT 24
Peak memory 222288 kb
Host smart-9be843e9-aa1b-42b8-83b1-37a758e0a0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436008842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3436008842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.1989779095
Short name T627
Test name
Test status
Simulation time 237768439984 ps
CPU time 1752.45 seconds
Started Jun 30 06:00:40 PM PDT 24
Finished Jun 30 06:29:53 PM PDT 24
Peak memory 425416 kb
Host smart-18d8b81e-2b24-4f92-9091-0877985958dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1989779095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1989779095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1728771637
Short name T355
Test name
Test status
Simulation time 238476161 ps
CPU time 3.8 seconds
Started Jun 30 06:00:26 PM PDT 24
Finished Jun 30 06:00:30 PM PDT 24
Peak memory 216164 kb
Host smart-a738dd59-5a8d-44ea-a315-ea423a557137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728771637 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1728771637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.1967044852
Short name T243
Test name
Test status
Simulation time 2921929111 ps
CPU time 4.94 seconds
Started Jun 30 06:00:25 PM PDT 24
Finished Jun 30 06:00:31 PM PDT 24
Peak memory 216180 kb
Host smart-1249ff62-9231-4d74-9a05-661aeb7eb91d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967044852 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.1967044852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2771346595
Short name T1049
Test name
Test status
Simulation time 65252871447 ps
CPU time 1748.74 seconds
Started Jun 30 06:00:27 PM PDT 24
Finished Jun 30 06:29:36 PM PDT 24
Peak memory 387168 kb
Host smart-fa9f4bc0-7fed-4326-85a4-27c9c14f8471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2771346595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2771346595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.3193281920
Short name T973
Test name
Test status
Simulation time 62433861472 ps
CPU time 1778.57 seconds
Started Jun 30 06:00:27 PM PDT 24
Finished Jun 30 06:30:06 PM PDT 24
Peak memory 389936 kb
Host smart-fb596fb7-f58a-4c00-8b8e-5ced82e8ea4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3193281920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3193281920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2461250789
Short name T283
Test name
Test status
Simulation time 117197774454 ps
CPU time 1344.75 seconds
Started Jun 30 06:00:25 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 329804 kb
Host smart-1c500c98-916c-4423-82ef-f4e75b752765
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2461250789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2461250789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.1045971511
Short name T431
Test name
Test status
Simulation time 135918677044 ps
CPU time 920.97 seconds
Started Jun 30 06:00:26 PM PDT 24
Finished Jun 30 06:15:48 PM PDT 24
Peak memory 295460 kb
Host smart-2da05707-48c0-4e02-be8e-834ee197344f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1045971511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1045971511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.1844882892
Short name T93
Test name
Test status
Simulation time 262472349475 ps
CPU time 5321.32 seconds
Started Jun 30 06:00:26 PM PDT 24
Finished Jun 30 07:29:08 PM PDT 24
Peak memory 652452 kb
Host smart-cc9a3bfb-d4b2-40c6-acc6-917847c3b9e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1844882892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1844882892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.2679847841
Short name T209
Test name
Test status
Simulation time 45249392339 ps
CPU time 3450.45 seconds
Started Jun 30 06:00:26 PM PDT 24
Finished Jun 30 06:57:57 PM PDT 24
Peak memory 563676 kb
Host smart-8b862de9-e771-4d77-8e84-68237febbfa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2679847841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.2679847841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.508170208
Short name T1007
Test name
Test status
Simulation time 20778362 ps
CPU time 0.74 seconds
Started Jun 30 06:01:00 PM PDT 24
Finished Jun 30 06:01:01 PM PDT 24
Peak memory 205608 kb
Host smart-55e2879e-2e43-4a5e-bfd5-b3ca2ef2944e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508170208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.508170208 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.2820895161
Short name T395
Test name
Test status
Simulation time 902231823 ps
CPU time 20.86 seconds
Started Jun 30 06:00:56 PM PDT 24
Finished Jun 30 06:01:17 PM PDT 24
Peak memory 224372 kb
Host smart-2b2a47b0-d053-41a9-9149-1a32635b5923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820895161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2820895161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.2150139581
Short name T1050
Test name
Test status
Simulation time 7501708203 ps
CPU time 182.2 seconds
Started Jun 30 06:00:43 PM PDT 24
Finished Jun 30 06:03:46 PM PDT 24
Peak memory 225680 kb
Host smart-3c121f8f-25d6-4be1-9ecf-1415aa4bc4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150139581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.2150139581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.722860755
Short name T670
Test name
Test status
Simulation time 5621651405 ps
CPU time 118.86 seconds
Started Jun 30 06:00:55 PM PDT 24
Finished Jun 30 06:02:54 PM PDT 24
Peak memory 231636 kb
Host smart-95e9d880-835f-4c4f-b667-580f7841d86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722860755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.722860755 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.3684834172
Short name T682
Test name
Test status
Simulation time 2336926160 ps
CPU time 38.17 seconds
Started Jun 30 06:00:54 PM PDT 24
Finished Jun 30 06:01:33 PM PDT 24
Peak memory 232564 kb
Host smart-71fec029-9ef2-4267-b288-ffcc7de635e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684834172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3684834172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.3650859749
Short name T330
Test name
Test status
Simulation time 1683663136 ps
CPU time 4.49 seconds
Started Jun 30 06:01:00 PM PDT 24
Finished Jun 30 06:01:05 PM PDT 24
Peak memory 207732 kb
Host smart-0327725d-a05b-4205-ab1d-ef3621e3eedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650859749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3650859749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.3629374236
Short name T537
Test name
Test status
Simulation time 391684364292 ps
CPU time 2628.3 seconds
Started Jun 30 06:00:44 PM PDT 24
Finished Jun 30 06:44:32 PM PDT 24
Peak memory 493880 kb
Host smart-94a6ecc1-cf37-4315-bc54-2e1bea803ffb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629374236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.3629374236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.1262395832
Short name T344
Test name
Test status
Simulation time 2822850404 ps
CPU time 213.37 seconds
Started Jun 30 06:00:40 PM PDT 24
Finished Jun 30 06:04:14 PM PDT 24
Peak memory 240748 kb
Host smart-f91cb364-84fd-47ce-8ebb-e8f7815b8fd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262395832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1262395832 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2973560453
Short name T1021
Test name
Test status
Simulation time 30771359786 ps
CPU time 45.76 seconds
Started Jun 30 06:00:39 PM PDT 24
Finished Jun 30 06:01:25 PM PDT 24
Peak memory 219956 kb
Host smart-db9746ff-0efa-40f8-ac1e-3da0920c1a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973560453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2973560453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.2289550655
Short name T732
Test name
Test status
Simulation time 40223258606 ps
CPU time 182.55 seconds
Started Jun 30 06:01:02 PM PDT 24
Finished Jun 30 06:04:05 PM PDT 24
Peak memory 257180 kb
Host smart-004279e7-5093-418c-99be-31a8eb93d6c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2289550655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2289550655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.3338587037
Short name T838
Test name
Test status
Simulation time 123733742 ps
CPU time 3.83 seconds
Started Jun 30 06:00:54 PM PDT 24
Finished Jun 30 06:00:58 PM PDT 24
Peak memory 216224 kb
Host smart-bd277f5c-48ad-46ac-8edb-4cb26f53c381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338587037 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.3338587037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1828189084
Short name T245
Test name
Test status
Simulation time 116853627 ps
CPU time 4.04 seconds
Started Jun 30 06:00:55 PM PDT 24
Finished Jun 30 06:00:59 PM PDT 24
Peak memory 216156 kb
Host smart-3c7a1a59-6d13-4484-bb54-c545068ea283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828189084 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1828189084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.4246486671
Short name T830
Test name
Test status
Simulation time 366885479902 ps
CPU time 2142.98 seconds
Started Jun 30 06:00:42 PM PDT 24
Finished Jun 30 06:36:25 PM PDT 24
Peak memory 399460 kb
Host smart-1d08587e-b733-4b2c-93d8-e22831767057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4246486671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.4246486671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.1089057979
Short name T867
Test name
Test status
Simulation time 34604583157 ps
CPU time 1442.74 seconds
Started Jun 30 06:00:47 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 373088 kb
Host smart-8a0d05f1-1212-4a7c-9c96-6b2e9db55bc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1089057979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.1089057979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.326969281
Short name T834
Test name
Test status
Simulation time 13801802944 ps
CPU time 1094.21 seconds
Started Jun 30 06:00:46 PM PDT 24
Finished Jun 30 06:19:01 PM PDT 24
Peak memory 329832 kb
Host smart-7ba5071f-caf1-41db-b184-0b649ca6a137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=326969281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.326969281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2414667392
Short name T544
Test name
Test status
Simulation time 145347720401 ps
CPU time 1036.4 seconds
Started Jun 30 06:00:48 PM PDT 24
Finished Jun 30 06:18:04 PM PDT 24
Peak memory 297896 kb
Host smart-26dbb951-2e89-4d38-a535-755b5a0af6db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2414667392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2414667392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.2983577597
Short name T801
Test name
Test status
Simulation time 202898369772 ps
CPU time 4183.49 seconds
Started Jun 30 06:00:46 PM PDT 24
Finished Jun 30 07:10:30 PM PDT 24
Peak memory 648412 kb
Host smart-a4ed2450-17a6-497b-afc5-507da8400fab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2983577597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.2983577597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2425127435
Short name T628
Test name
Test status
Simulation time 697728034570 ps
CPU time 4189.85 seconds
Started Jun 30 06:00:47 PM PDT 24
Finished Jun 30 07:10:37 PM PDT 24
Peak memory 568420 kb
Host smart-0121b8c7-e642-42bc-80f6-dff379ec6177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2425127435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2425127435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.1524876912
Short name T810
Test name
Test status
Simulation time 42425126 ps
CPU time 0.8 seconds
Started Jun 30 06:01:35 PM PDT 24
Finished Jun 30 06:01:36 PM PDT 24
Peak memory 205648 kb
Host smart-abf5f8c3-9ae3-4b43-becb-d9836af5c981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524876912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1524876912 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.2622390220
Short name T403
Test name
Test status
Simulation time 26770010987 ps
CPU time 148.94 seconds
Started Jun 30 06:01:32 PM PDT 24
Finished Jun 30 06:04:01 PM PDT 24
Peak memory 233880 kb
Host smart-f2d91ac4-5f9c-4530-84d1-91a825fd9de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622390220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2622390220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.4088356144
Short name T655
Test name
Test status
Simulation time 32019956053 ps
CPU time 716.6 seconds
Started Jun 30 06:01:16 PM PDT 24
Finished Jun 30 06:13:13 PM PDT 24
Peak memory 232084 kb
Host smart-c3681ba4-3b4b-4624-8054-ac476b71bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088356144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.4088356144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.628615804
Short name T614
Test name
Test status
Simulation time 5353767110 ps
CPU time 151.29 seconds
Started Jun 30 06:01:21 PM PDT 24
Finished Jun 30 06:03:52 PM PDT 24
Peak memory 236380 kb
Host smart-f2377f3c-4422-4125-95c9-e0c6893f26ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628615804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.628615804 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.4241071399
Short name T916
Test name
Test status
Simulation time 43642985817 ps
CPU time 364.09 seconds
Started Jun 30 06:01:21 PM PDT 24
Finished Jun 30 06:07:26 PM PDT 24
Peak memory 257152 kb
Host smart-17a195b9-896a-4545-a5ff-8da205cf1c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241071399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.4241071399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1405333273
Short name T764
Test name
Test status
Simulation time 420143932 ps
CPU time 1.38 seconds
Started Jun 30 06:01:30 PM PDT 24
Finished Jun 30 06:01:31 PM PDT 24
Peak memory 206524 kb
Host smart-f4ff7823-9b7e-4034-af78-6764c6342e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405333273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1405333273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.2117246692
Short name T671
Test name
Test status
Simulation time 103203877 ps
CPU time 1.36 seconds
Started Jun 30 06:01:32 PM PDT 24
Finished Jun 30 06:01:34 PM PDT 24
Peak memory 216036 kb
Host smart-466f111a-36b5-490c-92bb-1d8ff83ef359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117246692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2117246692 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.1839842623
Short name T701
Test name
Test status
Simulation time 96894465985 ps
CPU time 2141.81 seconds
Started Jun 30 06:01:09 PM PDT 24
Finished Jun 30 06:36:52 PM PDT 24
Peak memory 449196 kb
Host smart-9b192889-8eff-4bb0-9a4e-9c44499ec27f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839842623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.1839842623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.1432331408
Short name T566
Test name
Test status
Simulation time 19554942343 ps
CPU time 128.52 seconds
Started Jun 30 06:01:09 PM PDT 24
Finished Jun 30 06:03:18 PM PDT 24
Peak memory 232736 kb
Host smart-76007d7e-a8e3-4ef0-bf9a-e060738ec022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432331408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1432331408 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3257913161
Short name T320
Test name
Test status
Simulation time 548312146 ps
CPU time 29.14 seconds
Started Jun 30 06:01:02 PM PDT 24
Finished Jun 30 06:01:31 PM PDT 24
Peak memory 217556 kb
Host smart-f809e2f1-1eaa-496c-9e87-578f1f848aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257913161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3257913161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.810333246
Short name T298
Test name
Test status
Simulation time 25548906490 ps
CPU time 790.34 seconds
Started Jun 30 06:01:35 PM PDT 24
Finished Jun 30 06:14:46 PM PDT 24
Peak memory 355368 kb
Host smart-f0be3d0d-b31c-42de-98f7-03731ca7b4f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=810333246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.810333246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.3302965861
Short name T14
Test name
Test status
Simulation time 180676885 ps
CPU time 4.71 seconds
Started Jun 30 06:01:32 PM PDT 24
Finished Jun 30 06:01:37 PM PDT 24
Peak memory 216100 kb
Host smart-79ea17d7-8d2e-44d9-bd33-e62918f8ed0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302965861 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.3302965861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.2488596455
Short name T633
Test name
Test status
Simulation time 236006589 ps
CPU time 4.12 seconds
Started Jun 30 06:01:21 PM PDT 24
Finished Jun 30 06:01:25 PM PDT 24
Peak memory 216168 kb
Host smart-f5417dee-6d7a-43bf-9b69-41a1134f5c07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488596455 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.2488596455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.2802925026
Short name T598
Test name
Test status
Simulation time 97729485898 ps
CPU time 2012.03 seconds
Started Jun 30 06:01:15 PM PDT 24
Finished Jun 30 06:34:48 PM PDT 24
Peak memory 394948 kb
Host smart-47b87dcf-61b1-4e55-8542-b54ad382e390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2802925026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.2802925026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.3338797976
Short name T596
Test name
Test status
Simulation time 139114751961 ps
CPU time 1710.17 seconds
Started Jun 30 06:01:16 PM PDT 24
Finished Jun 30 06:29:47 PM PDT 24
Peak memory 367276 kb
Host smart-58a2ef48-e31d-406a-89e8-49955193186e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3338797976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.3338797976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.3794161480
Short name T957
Test name
Test status
Simulation time 137480753711 ps
CPU time 1306.39 seconds
Started Jun 30 06:01:15 PM PDT 24
Finished Jun 30 06:23:02 PM PDT 24
Peak memory 332712 kb
Host smart-ae481235-bc31-4bd9-9baf-f79f9de286b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3794161480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.3794161480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.2604279387
Short name T896
Test name
Test status
Simulation time 242757853063 ps
CPU time 887.54 seconds
Started Jun 30 06:01:14 PM PDT 24
Finished Jun 30 06:16:02 PM PDT 24
Peak memory 290284 kb
Host smart-24f871dc-fb1c-476d-9130-66cf98632eb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2604279387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2604279387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.2090165158
Short name T698
Test name
Test status
Simulation time 215234163793 ps
CPU time 4116.67 seconds
Started Jun 30 06:01:14 PM PDT 24
Finished Jun 30 07:09:51 PM PDT 24
Peak memory 667564 kb
Host smart-00df2d2f-d77d-4649-980d-6765243bd65c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2090165158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.2090165158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.925663923
Short name T622
Test name
Test status
Simulation time 55275742539 ps
CPU time 3432.08 seconds
Started Jun 30 06:01:22 PM PDT 24
Finished Jun 30 06:58:35 PM PDT 24
Peak memory 571112 kb
Host smart-078e5fb8-7676-4eb8-962a-dbf64a6aa88c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=925663923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.925663923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.562398574
Short name T572
Test name
Test status
Simulation time 24056672 ps
CPU time 0.79 seconds
Started Jun 30 06:01:56 PM PDT 24
Finished Jun 30 06:01:57 PM PDT 24
Peak memory 205608 kb
Host smart-286429e1-24d8-4857-a8bd-80455c144670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562398574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.562398574 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.3767778484
Short name T484
Test name
Test status
Simulation time 11328866373 ps
CPU time 240.8 seconds
Started Jun 30 06:01:53 PM PDT 24
Finished Jun 30 06:05:54 PM PDT 24
Peak memory 242704 kb
Host smart-d86d29fd-d6a9-4528-a764-8efc39cd0061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767778484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3767778484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.2666361172
Short name T433
Test name
Test status
Simulation time 114022686 ps
CPU time 8.55 seconds
Started Jun 30 06:01:41 PM PDT 24
Finished Jun 30 06:01:50 PM PDT 24
Peak memory 218736 kb
Host smart-098e4f7b-e73d-43bb-8d07-d72ac40ef009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666361172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2666361172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.2648024947
Short name T338
Test name
Test status
Simulation time 3271700203 ps
CPU time 50.14 seconds
Started Jun 30 06:01:59 PM PDT 24
Finished Jun 30 06:02:49 PM PDT 24
Peak memory 223352 kb
Host smart-8d41b1a8-ad1b-4aeb-9d4d-35949143baa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648024947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2648024947 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.690233701
Short name T1078
Test name
Test status
Simulation time 6975162678 ps
CPU time 146.16 seconds
Started Jun 30 06:01:56 PM PDT 24
Finished Jun 30 06:04:22 PM PDT 24
Peak memory 248984 kb
Host smart-1a120b39-78f8-44d9-9635-26e445268f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690233701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.690233701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.193101393
Short name T754
Test name
Test status
Simulation time 6237156711 ps
CPU time 8.99 seconds
Started Jun 30 06:01:55 PM PDT 24
Finished Jun 30 06:02:05 PM PDT 24
Peak memory 207916 kb
Host smart-f01dc896-98a4-4d86-971c-76229d2a2f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193101393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.193101393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.617875525
Short name T412
Test name
Test status
Simulation time 87701223 ps
CPU time 1.35 seconds
Started Jun 30 06:01:56 PM PDT 24
Finished Jun 30 06:01:58 PM PDT 24
Peak memory 216024 kb
Host smart-f3cd6a22-8f02-42c7-8754-ca2c7821aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617875525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.617875525 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.3820853863
Short name T473
Test name
Test status
Simulation time 132917552930 ps
CPU time 1988.9 seconds
Started Jun 30 06:01:41 PM PDT 24
Finished Jun 30 06:34:51 PM PDT 24
Peak memory 418148 kb
Host smart-2d253b66-cb43-4b13-9b8d-db8f20fa0911
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820853863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.3820853863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.2590137137
Short name T267
Test name
Test status
Simulation time 16904482820 ps
CPU time 335.58 seconds
Started Jun 30 06:01:41 PM PDT 24
Finished Jun 30 06:07:17 PM PDT 24
Peak memory 248584 kb
Host smart-5acdb63b-65b2-4379-bbc3-1318c894d06e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590137137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2590137137 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.568392505
Short name T924
Test name
Test status
Simulation time 27527907 ps
CPU time 1.83 seconds
Started Jun 30 06:01:43 PM PDT 24
Finished Jun 30 06:01:45 PM PDT 24
Peak memory 217252 kb
Host smart-b50f90db-b1c0-4db6-8dbe-437e973d9d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568392505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.568392505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.906413223
Short name T215
Test name
Test status
Simulation time 68754361 ps
CPU time 4.16 seconds
Started Jun 30 06:01:50 PM PDT 24
Finished Jun 30 06:01:55 PM PDT 24
Peak memory 216116 kb
Host smart-67a4e11b-f7d8-47c5-8958-a6e4462d1291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906413223 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.kmac_test_vectors_kmac.906413223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.4240068960
Short name T843
Test name
Test status
Simulation time 343321643 ps
CPU time 4.02 seconds
Started Jun 30 06:01:50 PM PDT 24
Finished Jun 30 06:01:54 PM PDT 24
Peak memory 216200 kb
Host smart-2d3eb2a5-d80e-4b22-a287-e6961b6552a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240068960 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.4240068960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.15185767
Short name T757
Test name
Test status
Simulation time 66433238159 ps
CPU time 1848.45 seconds
Started Jun 30 06:01:41 PM PDT 24
Finished Jun 30 06:32:31 PM PDT 24
Peak memory 397320 kb
Host smart-23e0c9ea-70a8-4b8e-8424-1fb88d158427
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=15185767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.15185767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.75890564
Short name T225
Test name
Test status
Simulation time 37288974301 ps
CPU time 1486.55 seconds
Started Jun 30 06:01:48 PM PDT 24
Finished Jun 30 06:26:35 PM PDT 24
Peak memory 377052 kb
Host smart-1b27b8b8-651f-4870-85e1-414dc95e8704
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=75890564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.75890564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.3056018549
Short name T849
Test name
Test status
Simulation time 46743260337 ps
CPU time 1244.76 seconds
Started Jun 30 06:01:48 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 331428 kb
Host smart-8f6e6159-370a-4340-ba7a-6603d5bf2656
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3056018549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3056018549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1180949348
Short name T621
Test name
Test status
Simulation time 33352467441 ps
CPU time 953.6 seconds
Started Jun 30 06:01:53 PM PDT 24
Finished Jun 30 06:17:47 PM PDT 24
Peak memory 299660 kb
Host smart-50810895-bef2-486e-b49d-e07476410994
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1180949348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1180949348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.2108984404
Short name T219
Test name
Test status
Simulation time 269899048664 ps
CPU time 4481.52 seconds
Started Jun 30 06:01:49 PM PDT 24
Finished Jun 30 07:16:32 PM PDT 24
Peak memory 659424 kb
Host smart-dc2a568f-101a-4a95-8336-e76bc74e4105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2108984404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2108984404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.1195464910
Short name T880
Test name
Test status
Simulation time 218054429246 ps
CPU time 4227.34 seconds
Started Jun 30 06:01:53 PM PDT 24
Finished Jun 30 07:12:21 PM PDT 24
Peak memory 557232 kb
Host smart-7a42a51c-cf53-48a9-95ce-95a077186d3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1195464910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1195464910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.582971212
Short name T249
Test name
Test status
Simulation time 62797013 ps
CPU time 0.87 seconds
Started Jun 30 06:02:26 PM PDT 24
Finished Jun 30 06:02:27 PM PDT 24
Peak memory 205600 kb
Host smart-5892083c-2ffa-4abf-ab9d-f8d57e601fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582971212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.582971212 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.1938935166
Short name T305
Test name
Test status
Simulation time 10152986899 ps
CPU time 234.74 seconds
Started Jun 30 06:02:11 PM PDT 24
Finished Jun 30 06:06:06 PM PDT 24
Peak memory 243340 kb
Host smart-6b436afa-9c19-41d7-a43a-d6085e989487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938935166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1938935166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.3532980654
Short name T717
Test name
Test status
Simulation time 25650442374 ps
CPU time 199.5 seconds
Started Jun 30 06:02:03 PM PDT 24
Finished Jun 30 06:05:22 PM PDT 24
Peak memory 224884 kb
Host smart-77e60386-186c-4378-83ed-d3021bd687b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532980654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3532980654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_error.3974144762
Short name T756
Test name
Test status
Simulation time 19857891599 ps
CPU time 132.06 seconds
Started Jun 30 06:02:18 PM PDT 24
Finished Jun 30 06:04:30 PM PDT 24
Peak memory 240776 kb
Host smart-de7afc0e-c6cf-4b69-81ce-50e5b4047002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974144762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3974144762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.2576409219
Short name T59
Test name
Test status
Simulation time 923842310 ps
CPU time 4.73 seconds
Started Jun 30 06:02:17 PM PDT 24
Finished Jun 30 06:02:22 PM PDT 24
Peak memory 216072 kb
Host smart-29b1e1de-c57e-4769-8e21-25d9eb8154aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576409219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2576409219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.379910822
Short name T32
Test name
Test status
Simulation time 58338023 ps
CPU time 1.55 seconds
Started Jun 30 06:02:17 PM PDT 24
Finished Jun 30 06:02:19 PM PDT 24
Peak memory 216060 kb
Host smart-1447e165-00e3-4de5-a080-f9690d7f5f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379910822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.379910822 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.2275102383
Short name T270
Test name
Test status
Simulation time 38924258610 ps
CPU time 1089.88 seconds
Started Jun 30 06:02:03 PM PDT 24
Finished Jun 30 06:20:13 PM PDT 24
Peak memory 323640 kb
Host smart-fc683ff1-5ab7-4002-8e50-9c7814b64457
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275102383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.2275102383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.489605483
Short name T951
Test name
Test status
Simulation time 22841104451 ps
CPU time 465.2 seconds
Started Jun 30 06:02:02 PM PDT 24
Finished Jun 30 06:09:48 PM PDT 24
Peak memory 251680 kb
Host smart-320c3b93-9226-457e-83b8-6f90ecd54f94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489605483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.489605483 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.3033773250
Short name T811
Test name
Test status
Simulation time 2800350180 ps
CPU time 36.28 seconds
Started Jun 30 06:02:03 PM PDT 24
Finished Jun 30 06:02:40 PM PDT 24
Peak memory 219104 kb
Host smart-03299518-83ed-4530-9e49-193e3e647687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033773250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.3033773250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.432847526
Short name T814
Test name
Test status
Simulation time 107408372727 ps
CPU time 507.23 seconds
Started Jun 30 06:02:25 PM PDT 24
Finished Jun 30 06:10:52 PM PDT 24
Peak memory 293188 kb
Host smart-9a1691e2-da13-4f52-9b0d-ed590714d17a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=432847526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.432847526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.1455300702
Short name T204
Test name
Test status
Simulation time 162334897 ps
CPU time 4.13 seconds
Started Jun 30 06:02:12 PM PDT 24
Finished Jun 30 06:02:16 PM PDT 24
Peak memory 216132 kb
Host smart-a944a28c-8a75-4a17-9ba9-757fedaa5906
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455300702 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.1455300702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.225967625
Short name T786
Test name
Test status
Simulation time 129998649 ps
CPU time 3.9 seconds
Started Jun 30 06:02:11 PM PDT 24
Finished Jun 30 06:02:15 PM PDT 24
Peak memory 216124 kb
Host smart-44b79427-2a91-4d89-bbfe-43cbafc578c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225967625 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.kmac_test_vectors_kmac_xof.225967625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1326102831
Short name T636
Test name
Test status
Simulation time 192674337072 ps
CPU time 1948 seconds
Started Jun 30 06:02:12 PM PDT 24
Finished Jun 30 06:34:40 PM PDT 24
Peak memory 374568 kb
Host smart-7c9dde4f-093b-41a8-b6a0-9ec19e6089fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1326102831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1326102831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.3912776296
Short name T453
Test name
Test status
Simulation time 357715120660 ps
CPU time 1557.71 seconds
Started Jun 30 06:02:11 PM PDT 24
Finished Jun 30 06:28:09 PM PDT 24
Peak memory 377668 kb
Host smart-4778b332-d148-4241-9338-7a260aebcaa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3912776296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.3912776296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.659948695
Short name T220
Test name
Test status
Simulation time 57278035053 ps
CPU time 1109.21 seconds
Started Jun 30 06:02:11 PM PDT 24
Finished Jun 30 06:20:40 PM PDT 24
Peak memory 338100 kb
Host smart-761ed6b6-d44d-4b9a-b0ef-8d7c0f394704
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=659948695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.659948695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.1283035756
Short name T946
Test name
Test status
Simulation time 9447957735 ps
CPU time 780.09 seconds
Started Jun 30 06:02:12 PM PDT 24
Finished Jun 30 06:15:12 PM PDT 24
Peak memory 290436 kb
Host smart-6529d2e4-43bc-4121-bc1d-58408c222bb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1283035756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1283035756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.755949074
Short name T370
Test name
Test status
Simulation time 175828179575 ps
CPU time 5039.57 seconds
Started Jun 30 06:02:11 PM PDT 24
Finished Jun 30 07:26:11 PM PDT 24
Peak memory 671500 kb
Host smart-bf906c91-97ee-4579-a58e-39a938c3b3e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=755949074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.755949074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3503253379
Short name T1058
Test name
Test status
Simulation time 44514262005 ps
CPU time 3422.9 seconds
Started Jun 30 06:02:12 PM PDT 24
Finished Jun 30 06:59:16 PM PDT 24
Peak memory 561296 kb
Host smart-39e305d4-80b2-4afa-93f4-ec89b3db5108
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3503253379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3503253379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1427886694
Short name T237
Test name
Test status
Simulation time 22196415 ps
CPU time 0.86 seconds
Started Jun 30 05:52:04 PM PDT 24
Finished Jun 30 05:52:05 PM PDT 24
Peak memory 205620 kb
Host smart-7fe41938-d882-4b29-aa23-990792bbf70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427886694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1427886694 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.2296694704
Short name T1004
Test name
Test status
Simulation time 19946820350 ps
CPU time 152.35 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 05:54:35 PM PDT 24
Peak memory 234848 kb
Host smart-d963929b-335d-49a1-9c9a-8b61677b2667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296694704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2296694704 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.393311442
Short name T380
Test name
Test status
Simulation time 31765041167 ps
CPU time 358.95 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 05:58:00 PM PDT 24
Peak memory 229252 kb
Host smart-c3b7c50e-3f14-4be5-b83d-5ac6b653e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393311442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.393311442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2653128380
Short name T333
Test name
Test status
Simulation time 4675942251 ps
CPU time 30.32 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 05:52:32 PM PDT 24
Peak memory 224808 kb
Host smart-d0552ae7-59a4-44e8-9d86-2bd1ec9eb408
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2653128380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2653128380 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.4024628683
Short name T254
Test name
Test status
Simulation time 582465799 ps
CPU time 15.7 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 05:52:18 PM PDT 24
Peak memory 216112 kb
Host smart-f123d5c0-cbae-447a-9be9-ae83f687a354
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024628683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.4024628683 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3540228888
Short name T850
Test name
Test status
Simulation time 16957542454 ps
CPU time 82.27 seconds
Started Jun 30 05:52:04 PM PDT 24
Finished Jun 30 05:53:26 PM PDT 24
Peak memory 216200 kb
Host smart-00237f6b-d4bf-417f-8e59-d85610551c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540228888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3540228888 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2388758192
Short name T890
Test name
Test status
Simulation time 31742142520 ps
CPU time 264.7 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 05:56:27 PM PDT 24
Peak memory 242652 kb
Host smart-e552a10d-00de-4b26-89a2-89aae92ee336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388758192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2388758192 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.1286877863
Short name T678
Test name
Test status
Simulation time 3253224672 ps
CPU time 64.42 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 05:53:05 PM PDT 24
Peak memory 234268 kb
Host smart-9aaf354b-4707-48d6-bbe6-277075eb74c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286877863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1286877863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.1156332200
Short name T57
Test name
Test status
Simulation time 996427582 ps
CPU time 5.16 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 05:52:08 PM PDT 24
Peak memory 215952 kb
Host smart-eb5366dd-7434-46bf-a2aa-1d54ec350fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156332200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1156332200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.1537126247
Short name T515
Test name
Test status
Simulation time 662246879 ps
CPU time 1.53 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 05:52:04 PM PDT 24
Peak memory 216136 kb
Host smart-ca881d00-5339-4fb6-995f-551c6bf0bcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537126247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1537126247 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.877032351
Short name T443
Test name
Test status
Simulation time 359988167464 ps
CPU time 1910.96 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 400956 kb
Host smart-ed5eac06-fc21-4800-ba63-4986ed5a04ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877032351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and
_output.877032351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.653779881
Short name T918
Test name
Test status
Simulation time 4304931323 ps
CPU time 98.15 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 05:53:41 PM PDT 24
Peak memory 230612 kb
Host smart-f42221b6-2ce7-44a5-a714-acb0e651f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653779881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.653779881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.1589410268
Short name T466
Test name
Test status
Simulation time 1008965144 ps
CPU time 39.24 seconds
Started Jun 30 05:52:03 PM PDT 24
Finished Jun 30 05:52:43 PM PDT 24
Peak memory 224288 kb
Host smart-09dcfec8-c5cb-47e8-b5f7-da0688269320
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589410268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1589410268 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.333784177
Short name T769
Test name
Test status
Simulation time 3497118962 ps
CPU time 47.44 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 05:52:48 PM PDT 24
Peak memory 220700 kb
Host smart-5943bb89-82f4-4e6b-b86f-d7c34f96ff00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333784177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.333784177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.1005596952
Short name T839
Test name
Test status
Simulation time 7429492566 ps
CPU time 266.67 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 05:56:27 PM PDT 24
Peak memory 279888 kb
Host smart-8441e6d1-f8a7-4a6b-aab8-b8af330e4898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1005596952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1005596952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.1868848443
Short name T499
Test name
Test status
Simulation time 350647122 ps
CPU time 4.15 seconds
Started Jun 30 05:52:03 PM PDT 24
Finished Jun 30 05:52:08 PM PDT 24
Peak memory 216232 kb
Host smart-1891342b-dc06-48a7-a59c-29a951ac9652
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868848443 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.1868848443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.385790771
Short name T1059
Test name
Test status
Simulation time 251889133 ps
CPU time 5.2 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 05:52:07 PM PDT 24
Peak memory 216160 kb
Host smart-ff0642f6-d7de-44fe-984c-963e82abdce0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385790771 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.kmac_test_vectors_kmac_xof.385790771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.446972255
Short name T534
Test name
Test status
Simulation time 77439684200 ps
CPU time 1551.82 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 06:17:55 PM PDT 24
Peak memory 387592 kb
Host smart-938452ec-d004-4c30-89f8-d33760544758
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=446972255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.446972255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.687535224
Short name T479
Test name
Test status
Simulation time 60506201908 ps
CPU time 1606.57 seconds
Started Jun 30 05:52:04 PM PDT 24
Finished Jun 30 06:18:51 PM PDT 24
Peak memory 371340 kb
Host smart-c442cfb8-918c-40a5-9cc2-cc8790efe53d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=687535224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.687535224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.1220973108
Short name T605
Test name
Test status
Simulation time 90355259441 ps
CPU time 1431.63 seconds
Started Jun 30 05:52:02 PM PDT 24
Finished Jun 30 06:15:54 PM PDT 24
Peak memory 332928 kb
Host smart-f26d36a6-77f9-42ac-92ba-3b728eb46119
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1220973108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.1220973108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.487073469
Short name T903
Test name
Test status
Simulation time 37832843726 ps
CPU time 798.31 seconds
Started Jun 30 05:52:00 PM PDT 24
Finished Jun 30 06:05:19 PM PDT 24
Peak memory 294240 kb
Host smart-74d4c97d-7db0-4553-a3b9-ed5fc96f5b1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=487073469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.487073469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.895696058
Short name T256
Test name
Test status
Simulation time 210796709027 ps
CPU time 3981.5 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 06:58:23 PM PDT 24
Peak memory 645544 kb
Host smart-b2bd0f30-4267-4036-8371-e5a8cb0e8eaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=895696058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.895696058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.2764776369
Short name T279
Test name
Test status
Simulation time 903051387701 ps
CPU time 4402.02 seconds
Started Jun 30 05:52:01 PM PDT 24
Finished Jun 30 07:05:24 PM PDT 24
Peak memory 562476 kb
Host smart-4ebf6e8e-9025-4bb3-a2f8-39202b6b7695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2764776369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.2764776369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.1337378981
Short name T642
Test name
Test status
Simulation time 22954056 ps
CPU time 0.81 seconds
Started Jun 30 05:52:16 PM PDT 24
Finished Jun 30 05:52:17 PM PDT 24
Peak memory 205604 kb
Host smart-bb39ad86-ddf5-45bf-a9fb-45e3fe9927c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337378981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1337378981 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.848308221
Short name T1006
Test name
Test status
Simulation time 2919561497 ps
CPU time 14.84 seconds
Started Jun 30 05:52:08 PM PDT 24
Finished Jun 30 05:52:23 PM PDT 24
Peak memory 224388 kb
Host smart-f34f6ed2-5e2d-43d2-941a-96edad8ea53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848308221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.848308221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.377350886
Short name T34
Test name
Test status
Simulation time 16768335157 ps
CPU time 222.21 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 05:55:52 PM PDT 24
Peak memory 240576 kb
Host smart-3be4ef44-2d77-4e17-ae06-908e30eaf6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377350886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.377350886 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3638457850
Short name T1003
Test name
Test status
Simulation time 21313818800 ps
CPU time 641.44 seconds
Started Jun 30 05:52:08 PM PDT 24
Finished Jun 30 06:02:50 PM PDT 24
Peak memory 240728 kb
Host smart-d7698aaf-208e-42e1-8c2a-bf3dfbbcffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638457850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3638457850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2355762197
Short name T361
Test name
Test status
Simulation time 560223033 ps
CPU time 18.68 seconds
Started Jun 30 05:52:15 PM PDT 24
Finished Jun 30 05:52:35 PM PDT 24
Peak memory 229348 kb
Host smart-e57793ce-7514-4cfe-898a-5373a008c20f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2355762197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2355762197 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.3914664722
Short name T514
Test name
Test status
Simulation time 283475129 ps
CPU time 19.25 seconds
Started Jun 30 05:52:16 PM PDT 24
Finished Jun 30 05:52:36 PM PDT 24
Peak memory 224248 kb
Host smart-319a94c2-101a-4fd1-b228-8673b1c0880e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914664722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3914664722 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.922716144
Short name T825
Test name
Test status
Simulation time 14716157768 ps
CPU time 29.42 seconds
Started Jun 30 05:52:19 PM PDT 24
Finished Jun 30 05:52:48 PM PDT 24
Peak memory 217168 kb
Host smart-ed9ed3e6-06ca-4097-abbe-84bae76839c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922716144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.922716144 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.507782286
Short name T615
Test name
Test status
Simulation time 28968692186 ps
CPU time 119.58 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 05:54:09 PM PDT 24
Peak memory 231800 kb
Host smart-acad828b-e06f-41cd-891b-f17d9ce0f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507782286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.507782286 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.1257377641
Short name T1008
Test name
Test status
Simulation time 13187618039 ps
CPU time 135.38 seconds
Started Jun 30 05:52:17 PM PDT 24
Finished Jun 30 05:54:33 PM PDT 24
Peak memory 250632 kb
Host smart-f7f425b8-f64e-47c0-91ec-4bed2af9a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257377641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1257377641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.3783480684
Short name T968
Test name
Test status
Simulation time 3145763241 ps
CPU time 4.61 seconds
Started Jun 30 05:52:15 PM PDT 24
Finished Jun 30 05:52:21 PM PDT 24
Peak memory 207996 kb
Host smart-074d9726-ca0a-4bfe-81d2-652dbdb10cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783480684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3783480684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.4151049288
Short name T51
Test name
Test status
Simulation time 54510832 ps
CPU time 1.21 seconds
Started Jun 30 05:52:18 PM PDT 24
Finished Jun 30 05:52:20 PM PDT 24
Peak memory 216084 kb
Host smart-3166247e-0ad1-4ee7-8fac-7c7bcf35e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151049288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.4151049288 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2710459230
Short name T871
Test name
Test status
Simulation time 762482443706 ps
CPU time 2441.09 seconds
Started Jun 30 05:52:08 PM PDT 24
Finished Jun 30 06:32:50 PM PDT 24
Peak memory 417032 kb
Host smart-8709257d-4e8e-4311-b2ef-007f3e9bab3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710459230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2710459230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.926613964
Short name T78
Test name
Test status
Simulation time 47974915879 ps
CPU time 260.89 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 05:56:30 PM PDT 24
Peak memory 242384 kb
Host smart-002fa03c-fc8e-4803-8144-6b964120c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926613964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.926613964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.1422550336
Short name T448
Test name
Test status
Simulation time 11898828812 ps
CPU time 242.98 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 05:56:13 PM PDT 24
Peak memory 238612 kb
Host smart-25dac91d-a7ab-4a09-9cf7-778398772d9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422550336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1422550336 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.3138256225
Short name T316
Test name
Test status
Simulation time 10031128817 ps
CPU time 53.13 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 05:53:02 PM PDT 24
Peak memory 220336 kb
Host smart-8a21411e-ad92-4707-a652-352ad0d0a729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138256225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3138256225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.351227948
Short name T583
Test name
Test status
Simulation time 2004667797 ps
CPU time 168.31 seconds
Started Jun 30 05:52:17 PM PDT 24
Finished Jun 30 05:55:06 PM PDT 24
Peak memory 232496 kb
Host smart-116a8a21-a93f-47fa-8eef-0a238b396d44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=351227948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.351227948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3155430550
Short name T190
Test name
Test status
Simulation time 1049170055 ps
CPU time 5.42 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 05:52:15 PM PDT 24
Peak memory 216144 kb
Host smart-99388046-c5b7-497c-9f8e-0f0c4baa803d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155430550 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3155430550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3634071400
Short name T195
Test name
Test status
Simulation time 1332015486 ps
CPU time 4.61 seconds
Started Jun 30 05:52:08 PM PDT 24
Finished Jun 30 05:52:13 PM PDT 24
Peak memory 216156 kb
Host smart-ef297c85-478a-4e35-959b-23c5b380f00c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634071400 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3634071400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3848884099
Short name T1045
Test name
Test status
Simulation time 373708281410 ps
CPU time 1653.87 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 389132 kb
Host smart-7a33c8a8-6d79-4808-a1f1-76c7eec935a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3848884099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3848884099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.4013303420
Short name T1046
Test name
Test status
Simulation time 94530295322 ps
CPU time 1767.49 seconds
Started Jun 30 05:52:11 PM PDT 24
Finished Jun 30 06:21:39 PM PDT 24
Peak memory 371084 kb
Host smart-7bfbfe95-b65a-472d-a655-14fcb3deb5be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4013303420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.4013303420 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.3845943273
Short name T235
Test name
Test status
Simulation time 201757964017 ps
CPU time 1359.67 seconds
Started Jun 30 05:52:08 PM PDT 24
Finished Jun 30 06:14:48 PM PDT 24
Peak memory 332204 kb
Host smart-09871bec-115d-4848-abf3-f190470b59d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3845943273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3845943273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.1798055207
Short name T926
Test name
Test status
Simulation time 191539148693 ps
CPU time 987.97 seconds
Started Jun 30 05:52:09 PM PDT 24
Finished Jun 30 06:08:37 PM PDT 24
Peak memory 291892 kb
Host smart-dfc81a94-dd89-4b50-bc93-0de5f18840d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1798055207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.1798055207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.255018115
Short name T474
Test name
Test status
Simulation time 171493497426 ps
CPU time 4690.07 seconds
Started Jun 30 05:52:11 PM PDT 24
Finished Jun 30 07:10:22 PM PDT 24
Peak memory 648632 kb
Host smart-6c46c1a5-2e30-4823-aee8-e6f07127d7d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=255018115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.255018115 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.205354348
Short name T992
Test name
Test status
Simulation time 296331119201 ps
CPU time 4296.22 seconds
Started Jun 30 05:52:07 PM PDT 24
Finished Jun 30 07:03:44 PM PDT 24
Peak memory 559812 kb
Host smart-f18d7595-59e5-4173-aac5-c7427f7067c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=205354348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.205354348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.1535219419
Short name T304
Test name
Test status
Simulation time 14204402 ps
CPU time 0.81 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 05:52:24 PM PDT 24
Peak memory 205624 kb
Host smart-9b0e502b-7ef7-4dce-b5e1-713098c5df57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535219419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1535219419 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.3482525491
Short name T467
Test name
Test status
Simulation time 19370480772 ps
CPU time 242.82 seconds
Started Jun 30 05:52:21 PM PDT 24
Finished Jun 30 05:56:24 PM PDT 24
Peak memory 242668 kb
Host smart-4d1a0ced-0ec2-4ea9-828d-a44571a38d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482525491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3482525491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2532088826
Short name T736
Test name
Test status
Simulation time 8854946919 ps
CPU time 142.04 seconds
Started Jun 30 05:52:24 PM PDT 24
Finished Jun 30 05:54:46 PM PDT 24
Peak memory 232052 kb
Host smart-2aa3a5f7-e527-4db8-b464-2c42b293ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532088826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2532088826 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.3195959957
Short name T841
Test name
Test status
Simulation time 7195255827 ps
CPU time 22.87 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 05:52:46 PM PDT 24
Peak memory 220356 kb
Host smart-21940ae3-68ea-4e2a-bbf1-184620aba66e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3195959957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3195959957 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.2945945371
Short name T859
Test name
Test status
Simulation time 736492639 ps
CPU time 13.78 seconds
Started Jun 30 05:52:23 PM PDT 24
Finished Jun 30 05:52:37 PM PDT 24
Peak memory 224248 kb
Host smart-5622835d-cb4a-4fce-96b0-073ebe5820b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2945945371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2945945371 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.2285652077
Short name T652
Test name
Test status
Simulation time 25196031944 ps
CPU time 66.36 seconds
Started Jun 30 05:52:23 PM PDT 24
Finished Jun 30 05:53:30 PM PDT 24
Peak memory 216184 kb
Host smart-388104c2-1877-4503-8c60-38b8ec484aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285652077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2285652077 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.3982492182
Short name T776
Test name
Test status
Simulation time 2887595405 ps
CPU time 78.69 seconds
Started Jun 30 05:52:24 PM PDT 24
Finished Jun 30 05:53:44 PM PDT 24
Peak memory 228620 kb
Host smart-08fb7d11-6de8-4a44-861d-abad0b03f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982492182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3982492182 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.2157757697
Short name T691
Test name
Test status
Simulation time 15062757673 ps
CPU time 288.22 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 05:57:11 PM PDT 24
Peak memory 258140 kb
Host smart-f19b04a4-3cca-442c-8598-e8366025a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157757697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.2157757697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.2646941953
Short name T526
Test name
Test status
Simulation time 647086775 ps
CPU time 3.57 seconds
Started Jun 30 05:52:23 PM PDT 24
Finished Jun 30 05:52:27 PM PDT 24
Peak memory 216008 kb
Host smart-42c3fdc3-3ff3-4893-9600-090bbfd0c7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646941953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2646941953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1861652158
Short name T659
Test name
Test status
Simulation time 93811736 ps
CPU time 1.44 seconds
Started Jun 30 05:52:21 PM PDT 24
Finished Jun 30 05:52:23 PM PDT 24
Peak memory 216112 kb
Host smart-e6673aee-4de2-4b0c-a218-615daddaf67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861652158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1861652158 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.1799958998
Short name T550
Test name
Test status
Simulation time 3005790772 ps
CPU time 252.92 seconds
Started Jun 30 05:52:15 PM PDT 24
Finished Jun 30 05:56:28 PM PDT 24
Peak memory 245492 kb
Host smart-284b9bab-21fb-4d5d-902a-8ddbd841fc5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799958998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.1799958998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.1912031439
Short name T76
Test name
Test status
Simulation time 704776615 ps
CPU time 31.63 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 05:52:54 PM PDT 24
Peak memory 224520 kb
Host smart-fbafc143-4137-44f0-867a-d663cc8a1048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912031439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1912031439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.211749765
Short name T368
Test name
Test status
Simulation time 795362705 ps
CPU time 61.52 seconds
Started Jun 30 05:52:16 PM PDT 24
Finished Jun 30 05:53:18 PM PDT 24
Peak memory 223692 kb
Host smart-471b2004-7d62-4132-a937-39f9c20c3f4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211749765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.211749765 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.449667986
Short name T329
Test name
Test status
Simulation time 3440475124 ps
CPU time 42.72 seconds
Started Jun 30 05:52:18 PM PDT 24
Finished Jun 30 05:53:01 PM PDT 24
Peak memory 220244 kb
Host smart-f8f20439-9837-4028-a231-aba8b7a485a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449667986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.449667986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3686317687
Short name T373
Test name
Test status
Simulation time 10374831153 ps
CPU time 268.44 seconds
Started Jun 30 05:52:21 PM PDT 24
Finished Jun 30 05:56:50 PM PDT 24
Peak memory 273756 kb
Host smart-444677f9-96c0-4a37-9fec-968cd62b07b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3686317687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3686317687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.1561009995
Short name T118
Test name
Test status
Simulation time 53828339460 ps
CPU time 849.15 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 06:06:32 PM PDT 24
Peak memory 273160 kb
Host smart-93814ae1-801a-42c7-9a61-fb26dc9e8cd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561009995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.1561009995 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.94419845
Short name T674
Test name
Test status
Simulation time 175780335 ps
CPU time 4.55 seconds
Started Jun 30 05:52:16 PM PDT 24
Finished Jun 30 05:52:21 PM PDT 24
Peak memory 216180 kb
Host smart-d67ac191-64c5-4719-854a-d6be3ac7dab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94419845 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.kmac_test_vectors_kmac.94419845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2221287385
Short name T623
Test name
Test status
Simulation time 1857368331 ps
CPU time 5.13 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 05:52:28 PM PDT 24
Peak memory 216104 kb
Host smart-3e383d56-ce44-4acb-98e7-85b048fd05f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221287385 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2221287385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2826980713
Short name T798
Test name
Test status
Simulation time 57570830100 ps
CPU time 1632.37 seconds
Started Jun 30 05:52:17 PM PDT 24
Finished Jun 30 06:19:30 PM PDT 24
Peak memory 395736 kb
Host smart-bbf7fc1f-c53c-4b10-ab54-3d2c6839677c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2826980713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2826980713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.2149492947
Short name T619
Test name
Test status
Simulation time 33955989339 ps
CPU time 1518.51 seconds
Started Jun 30 05:52:18 PM PDT 24
Finished Jun 30 06:17:37 PM PDT 24
Peak memory 372200 kb
Host smart-426c5da6-6fb8-4a66-aac7-efdbd2fb39a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2149492947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2149492947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3051343371
Short name T1077
Test name
Test status
Simulation time 111329332514 ps
CPU time 1062.2 seconds
Started Jun 30 05:52:16 PM PDT 24
Finished Jun 30 06:09:58 PM PDT 24
Peak memory 330224 kb
Host smart-2a3377b3-68d5-4452-90e9-3201e6af73b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3051343371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3051343371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.574346205
Short name T925
Test name
Test status
Simulation time 201282308363 ps
CPU time 1006.83 seconds
Started Jun 30 05:52:15 PM PDT 24
Finished Jun 30 06:09:02 PM PDT 24
Peak memory 292468 kb
Host smart-e74b6d51-9156-44ed-9ef4-9977e4401b31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=574346205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.574346205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.1174220413
Short name T546
Test name
Test status
Simulation time 1423904509593 ps
CPU time 4993.3 seconds
Started Jun 30 05:52:16 PM PDT 24
Finished Jun 30 07:15:30 PM PDT 24
Peak memory 643672 kb
Host smart-5c77de1e-dbe7-4a9a-aa64-7151f013d421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1174220413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.1174220413 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.3289547432
Short name T188
Test name
Test status
Simulation time 146055173334 ps
CPU time 3850.29 seconds
Started Jun 30 05:52:15 PM PDT 24
Finished Jun 30 06:56:27 PM PDT 24
Peak memory 564956 kb
Host smart-1d3bfe96-a88c-4693-ad81-701cda2be2a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3289547432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.3289547432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.1211068320
Short name T43
Test name
Test status
Simulation time 37700852 ps
CPU time 0.79 seconds
Started Jun 30 05:52:36 PM PDT 24
Finished Jun 30 05:52:37 PM PDT 24
Peak memory 205556 kb
Host smart-4eae5133-88aa-477c-873d-7ff716dc0010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211068320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1211068320 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3723234869
Short name T763
Test name
Test status
Simulation time 30387706918 ps
CPU time 242.22 seconds
Started Jun 30 05:52:30 PM PDT 24
Finished Jun 30 05:56:33 PM PDT 24
Peak memory 244724 kb
Host smart-3c43845c-4eb8-4c59-ab1a-9649238346b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723234869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3723234869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.489771425
Short name T726
Test name
Test status
Simulation time 3313024041 ps
CPU time 71.87 seconds
Started Jun 30 05:52:28 PM PDT 24
Finished Jun 30 05:53:40 PM PDT 24
Peak memory 228152 kb
Host smart-b68e0d84-94fe-4c2b-bf8e-58dee2dcfa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489771425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.489771425 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.3390688029
Short name T1068
Test name
Test status
Simulation time 3661988922 ps
CPU time 210.4 seconds
Started Jun 30 05:52:25 PM PDT 24
Finished Jun 30 05:55:56 PM PDT 24
Peak memory 225220 kb
Host smart-edd19317-8a1b-4064-97d3-96619420e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390688029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3390688029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.785603989
Short name T941
Test name
Test status
Simulation time 1611429731 ps
CPU time 22.8 seconds
Started Jun 30 05:52:29 PM PDT 24
Finished Jun 30 05:52:52 PM PDT 24
Peak memory 234912 kb
Host smart-adc1e1ad-1e5a-4b29-ad3d-80b6b4eadd44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=785603989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.785603989 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.490258432
Short name T206
Test name
Test status
Simulation time 1336253709 ps
CPU time 24.66 seconds
Started Jun 30 05:52:27 PM PDT 24
Finished Jun 30 05:52:52 PM PDT 24
Peak memory 224200 kb
Host smart-82655784-bdcc-402a-ada8-60fb188c0ab9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=490258432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.490258432 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.2861409528
Short name T657
Test name
Test status
Simulation time 14913814562 ps
CPU time 66.98 seconds
Started Jun 30 05:52:30 PM PDT 24
Finished Jun 30 05:53:37 PM PDT 24
Peak memory 216164 kb
Host smart-bd9b640c-d231-434e-8fbb-d09b1a68c3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861409528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2861409528 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.3134075932
Short name T800
Test name
Test status
Simulation time 9867480307 ps
CPU time 196.49 seconds
Started Jun 30 05:52:29 PM PDT 24
Finished Jun 30 05:55:46 PM PDT 24
Peak memory 239320 kb
Host smart-354b69ad-93f1-4744-bac4-ee58b93f77bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134075932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3134075932 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.3395619767
Short name T341
Test name
Test status
Simulation time 1581002440 ps
CPU time 118.14 seconds
Started Jun 30 05:52:28 PM PDT 24
Finished Jun 30 05:54:27 PM PDT 24
Peak memory 248824 kb
Host smart-1bddb281-14cc-4e6d-8c89-7abd567152d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395619767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3395619767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3538864384
Short name T1005
Test name
Test status
Simulation time 300379545 ps
CPU time 1.13 seconds
Started Jun 30 05:52:29 PM PDT 24
Finished Jun 30 05:52:30 PM PDT 24
Peak memory 206540 kb
Host smart-6ea75fed-a7d9-470b-8f30-dcc543956242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538864384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3538864384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.2223602547
Short name T81
Test name
Test status
Simulation time 85502295 ps
CPU time 1.29 seconds
Started Jun 30 05:52:35 PM PDT 24
Finished Jun 30 05:52:37 PM PDT 24
Peak memory 216224 kb
Host smart-2fea8f03-372f-4079-a138-5043a3d16d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223602547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2223602547 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.4065034542
Short name T413
Test name
Test status
Simulation time 71453102028 ps
CPU time 810.23 seconds
Started Jun 30 05:52:20 PM PDT 24
Finished Jun 30 06:05:50 PM PDT 24
Peak memory 294492 kb
Host smart-fa7cbfc8-46a6-417f-b294-cd8f91c2a3ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065034542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.4065034542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.3444905301
Short name T318
Test name
Test status
Simulation time 306628513 ps
CPU time 3.9 seconds
Started Jun 30 05:52:28 PM PDT 24
Finished Jun 30 05:52:33 PM PDT 24
Peak memory 220648 kb
Host smart-01f7c5d5-bea9-4110-ab65-463cdd488847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444905301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3444905301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.4117488535
Short name T988
Test name
Test status
Simulation time 108528964436 ps
CPU time 318 seconds
Started Jun 30 05:52:23 PM PDT 24
Finished Jun 30 05:57:42 PM PDT 24
Peak memory 243784 kb
Host smart-9781cb3d-22b6-46dc-924d-abc659b1abf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117488535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.4117488535 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3668258841
Short name T715
Test name
Test status
Simulation time 211832029 ps
CPU time 11.78 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 05:52:34 PM PDT 24
Peak memory 222292 kb
Host smart-37ee83bd-452c-40f6-a4da-96d38a8617b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668258841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3668258841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.2702481149
Short name T832
Test name
Test status
Simulation time 16512886679 ps
CPU time 1285.28 seconds
Started Jun 30 05:52:36 PM PDT 24
Finished Jun 30 06:14:01 PM PDT 24
Peak memory 395244 kb
Host smart-ada74fe0-b976-4e90-b73b-a6fe7c5e6a57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2702481149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2702481149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.3959877774
Short name T263
Test name
Test status
Simulation time 126180243 ps
CPU time 3.86 seconds
Started Jun 30 05:52:29 PM PDT 24
Finished Jun 30 05:52:33 PM PDT 24
Peak memory 216148 kb
Host smart-0b0da6b9-721f-442c-9e8d-b4564e5142cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959877774 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.3959877774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2921948647
Short name T469
Test name
Test status
Simulation time 79379287 ps
CPU time 4.19 seconds
Started Jun 30 05:52:29 PM PDT 24
Finished Jun 30 05:52:34 PM PDT 24
Peak memory 216200 kb
Host smart-8ebfb800-05f4-4bd4-a170-18b8421265b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921948647 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2921948647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2275539529
Short name T741
Test name
Test status
Simulation time 312871687963 ps
CPU time 1671.46 seconds
Started Jun 30 05:52:22 PM PDT 24
Finished Jun 30 06:20:14 PM PDT 24
Peak memory 390844 kb
Host smart-7bcacd7d-a9b2-4153-9124-615573a81ce1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2275539529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2275539529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.3365387717
Short name T665
Test name
Test status
Simulation time 36700058704 ps
CPU time 1382.2 seconds
Started Jun 30 05:52:21 PM PDT 24
Finished Jun 30 06:15:24 PM PDT 24
Peak memory 371372 kb
Host smart-1ce1826f-9bab-4081-8a6f-0da8d1964fe8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3365387717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.3365387717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.569767584
Short name T126
Test name
Test status
Simulation time 285857053807 ps
CPU time 1449.16 seconds
Started Jun 30 05:52:30 PM PDT 24
Finished Jun 30 06:16:40 PM PDT 24
Peak memory 329396 kb
Host smart-571d4129-a7c6-497b-8caa-90c72a828b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=569767584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.569767584 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.3232565713
Short name T795
Test name
Test status
Simulation time 18848610906 ps
CPU time 792.18 seconds
Started Jun 30 05:52:30 PM PDT 24
Finished Jun 30 06:05:43 PM PDT 24
Peak memory 293740 kb
Host smart-17b074c5-c4dd-4ce8-a42f-337da914a6db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3232565713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3232565713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.112811579
Short name T599
Test name
Test status
Simulation time 339412966139 ps
CPU time 4717.84 seconds
Started Jun 30 05:52:29 PM PDT 24
Finished Jun 30 07:11:08 PM PDT 24
Peak memory 637760 kb
Host smart-efb72a41-1f5c-4052-8a21-2b3d33f1eb7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=112811579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.112811579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.3688663684
Short name T404
Test name
Test status
Simulation time 216681437865 ps
CPU time 4184.41 seconds
Started Jun 30 05:52:29 PM PDT 24
Finished Jun 30 07:02:14 PM PDT 24
Peak memory 552444 kb
Host smart-f40d75b4-60e8-486f-9fc0-bedb6065fd42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3688663684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3688663684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.1956134633
Short name T979
Test name
Test status
Simulation time 11761710 ps
CPU time 0.74 seconds
Started Jun 30 05:52:42 PM PDT 24
Finished Jun 30 05:52:43 PM PDT 24
Peak memory 205612 kb
Host smart-ee2f0522-5853-48ed-b865-55f6ed5cdec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956134633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1956134633 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.617480041
Short name T699
Test name
Test status
Simulation time 35436461948 ps
CPU time 235.24 seconds
Started Jun 30 05:52:36 PM PDT 24
Finished Jun 30 05:56:32 PM PDT 24
Peak memory 240968 kb
Host smart-b6f35702-0941-49e4-9e66-20e8fcaa9b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617480041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.617480041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3036472867
Short name T487
Test name
Test status
Simulation time 25786427818 ps
CPU time 82.16 seconds
Started Jun 30 05:52:44 PM PDT 24
Finished Jun 30 05:54:06 PM PDT 24
Peak memory 226552 kb
Host smart-8d473136-28fc-4b8a-860f-b659337ba170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036472867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3036472867 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.78865172
Short name T967
Test name
Test status
Simulation time 20358616244 ps
CPU time 172.54 seconds
Started Jun 30 05:52:36 PM PDT 24
Finished Jun 30 05:55:29 PM PDT 24
Peak memory 224744 kb
Host smart-48eadd21-5c2d-42e3-801f-1bf872253ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78865172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.78865172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.3037389690
Short name T351
Test name
Test status
Simulation time 918820464 ps
CPU time 5.81 seconds
Started Jun 30 05:52:42 PM PDT 24
Finished Jun 30 05:52:49 PM PDT 24
Peak memory 216072 kb
Host smart-7bba71a0-b6c2-424c-a213-961bf0e6d76a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3037389690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3037389690 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.4040413859
Short name T931
Test name
Test status
Simulation time 266887535 ps
CPU time 9.4 seconds
Started Jun 30 05:52:39 PM PDT 24
Finished Jun 30 05:52:48 PM PDT 24
Peak memory 224208 kb
Host smart-c252aa50-ca7b-49da-a17a-56ae6bcc50ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4040413859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.4040413859 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1640455665
Short name T39
Test name
Test status
Simulation time 4244170956 ps
CPU time 49.5 seconds
Started Jun 30 05:52:41 PM PDT 24
Finished Jun 30 05:53:31 PM PDT 24
Peak memory 216208 kb
Host smart-2b18e0f4-0258-4dfe-9cf0-f2fb13ced12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640455665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1640455665 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.869672966
Short name T888
Test name
Test status
Simulation time 11109780350 ps
CPU time 156.5 seconds
Started Jun 30 05:52:41 PM PDT 24
Finished Jun 30 05:55:18 PM PDT 24
Peak memory 239000 kb
Host smart-c75fc10d-7ebf-4633-8a52-78b98a210bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869672966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.869672966 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.2137278179
Short name T311
Test name
Test status
Simulation time 1450636971 ps
CPU time 36.19 seconds
Started Jun 30 05:52:42 PM PDT 24
Finished Jun 30 05:53:19 PM PDT 24
Peak memory 237864 kb
Host smart-ff7efe70-3b52-4588-a7c0-5a2c2883e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137278179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2137278179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2167828868
Short name T714
Test name
Test status
Simulation time 223351784 ps
CPU time 1.77 seconds
Started Jun 30 05:52:41 PM PDT 24
Finished Jun 30 05:52:43 PM PDT 24
Peak memory 207764 kb
Host smart-bc6713c4-83e0-4193-a57c-3822559390e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167828868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2167828868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.2832262327
Short name T49
Test name
Test status
Simulation time 2988385643 ps
CPU time 13.29 seconds
Started Jun 30 05:52:40 PM PDT 24
Finished Jun 30 05:52:54 PM PDT 24
Peak memory 226056 kb
Host smart-266e6c4c-7de9-4cb8-8141-82b32093c516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832262327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2832262327 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.92055467
Short name T727
Test name
Test status
Simulation time 47341590108 ps
CPU time 703.09 seconds
Started Jun 30 05:52:38 PM PDT 24
Finished Jun 30 06:04:22 PM PDT 24
Peak memory 285316 kb
Host smart-7134f417-04d4-4433-8233-c201b749a134
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92055467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_
output.92055467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.191312581
Short name T912
Test name
Test status
Simulation time 18498666768 ps
CPU time 117.55 seconds
Started Jun 30 05:52:41 PM PDT 24
Finished Jun 30 05:54:39 PM PDT 24
Peak memory 232340 kb
Host smart-7ecbd350-dc14-488f-b8be-9108d0860752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191312581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.191312581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.2829305814
Short name T802
Test name
Test status
Simulation time 16719581561 ps
CPU time 366.28 seconds
Started Jun 30 05:52:35 PM PDT 24
Finished Jun 30 05:58:42 PM PDT 24
Peak memory 247020 kb
Host smart-ff0c3933-60c6-44ba-bf88-1da5a8b8028f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829305814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2829305814 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.3689097345
Short name T685
Test name
Test status
Simulation time 3551012204 ps
CPU time 46.96 seconds
Started Jun 30 05:52:35 PM PDT 24
Finished Jun 30 05:53:23 PM PDT 24
Peak memory 219824 kb
Host smart-cda21e0a-dfc4-400a-bd84-40ad7a94ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689097345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3689097345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.381102056
Short name T23
Test name
Test status
Simulation time 26290312410 ps
CPU time 442.55 seconds
Started Jun 30 05:52:42 PM PDT 24
Finished Jun 30 06:00:05 PM PDT 24
Peak memory 287584 kb
Host smart-cb48b54c-f728-4628-9abc-09a81bbb781d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=381102056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.381102056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1090946995
Short name T46
Test name
Test status
Simulation time 73909870696 ps
CPU time 1214.88 seconds
Started Jun 30 05:52:41 PM PDT 24
Finished Jun 30 06:12:56 PM PDT 24
Peak memory 363732 kb
Host smart-b31c474c-4530-4022-a9cb-ef8a423d92ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090946995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1090946995 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.4069039385
Short name T994
Test name
Test status
Simulation time 248551959 ps
CPU time 3.84 seconds
Started Jun 30 05:52:36 PM PDT 24
Finished Jun 30 05:52:40 PM PDT 24
Peak memory 216144 kb
Host smart-649b1226-a012-437f-8da3-e673f5f4e537
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069039385 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.4069039385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3342204437
Short name T255
Test name
Test status
Simulation time 240346094 ps
CPU time 4.97 seconds
Started Jun 30 05:52:37 PM PDT 24
Finished Jun 30 05:52:43 PM PDT 24
Peak memory 216088 kb
Host smart-25256e21-7fa4-4560-838c-0bee9ef7926e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342204437 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3342204437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1558601650
Short name T933
Test name
Test status
Simulation time 40425436734 ps
CPU time 1550.01 seconds
Started Jun 30 05:52:37 PM PDT 24
Finished Jun 30 06:18:28 PM PDT 24
Peak memory 404032 kb
Host smart-ed964d83-e4d7-4bff-a24c-f7ee026b5649
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1558601650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1558601650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.364650094
Short name T1070
Test name
Test status
Simulation time 375788866659 ps
CPU time 1932.2 seconds
Started Jun 30 05:52:36 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 391036 kb
Host smart-96857ed8-762c-4424-89ec-9e4b6300512f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=364650094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.364650094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.1083053327
Short name T401
Test name
Test status
Simulation time 14519302332 ps
CPU time 1106.82 seconds
Started Jun 30 05:52:39 PM PDT 24
Finished Jun 30 06:11:07 PM PDT 24
Peak memory 341196 kb
Host smart-fb4121ca-1e7c-4dc1-a71e-4418d74a5d14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1083053327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.1083053327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.3292357225
Short name T654
Test name
Test status
Simulation time 42232805154 ps
CPU time 895.11 seconds
Started Jun 30 05:52:35 PM PDT 24
Finished Jun 30 06:07:31 PM PDT 24
Peak memory 293304 kb
Host smart-667c3ec0-f020-4a8d-acf6-949913bc04e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3292357225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3292357225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.3563356277
Short name T277
Test name
Test status
Simulation time 342291575398 ps
CPU time 4713.52 seconds
Started Jun 30 05:52:39 PM PDT 24
Finished Jun 30 07:11:14 PM PDT 24
Peak memory 645944 kb
Host smart-4a2a7692-ddc4-48fc-9b86-5e2fb141d5ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3563356277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.3563356277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.174380134
Short name T415
Test name
Test status
Simulation time 394725085264 ps
CPU time 3525.53 seconds
Started Jun 30 05:52:34 PM PDT 24
Finished Jun 30 06:51:20 PM PDT 24
Peak memory 564912 kb
Host smart-919fb058-7089-41df-bec7-44d256f291dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=174380134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.174380134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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