Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100089410	1			T1	3342		T2	159804		T3	112240
all_values[1]	100089410	1			T1	3342		T2	159804		T3	112240
all_values[2]	100089410	1			T1	3342		T2	159804		T3	112240

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

459146

1

T1

1130

T2

6

T13

7

auto[1]

299809084

1

T1

8896

T2

479406

T3

336720

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298740981

1

T1

9924

T2

478053

T3

335598

auto[1]

1527249

1

T1

102

T2

1359

T3

1122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	166959	1			T1	559		T14	89		T16	1
all_values[0]	auto[0]	auto[1]	2112	1			T1	6		T14	2		T16	2
all_values[0]	auto[1]	auto[0]	99413368	1			T1	2749		T2	159351		T3	111866
all_values[0]	auto[1]	auto[1]	506971	1			T1	28		T2	453		T3	374
all_values[1]	auto[0]	auto[0]	148311	1			T2	2		T13	5		T17	2742
all_values[1]	auto[0]	auto[1]	1623	1			T2	1		T13	2		T17	1
all_values[1]	auto[1]	auto[0]	99432016	1			T1	3308		T2	159349		T3	111866
all_values[1]	auto[1]	auto[1]	507460	1			T1	34		T2	452		T3	374
all_values[2]	auto[0]	auto[0]	138555	1			T1	559		T2	2		T14	104
all_values[2]	auto[0]	auto[1]	1586	1			T1	6		T2	1		T14	2
all_values[2]	auto[1]	auto[0]	99441772	1			T1	2749		T2	159349		T3	111866
all_values[2]	auto[1]	auto[1]	507497	1			T1	28		T2	452		T3	374