Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
360090 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
492 |
auto[1] |
330412 |
1 |
|
|
T1 |
72 |
|
T2 |
618 |
|
T14 |
92 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173537 |
1 |
|
|
T1 |
14 |
|
T2 |
145 |
|
T3 |
136 |
lower_val |
170816 |
1 |
|
|
T1 |
23 |
|
T2 |
154 |
|
T3 |
114 |
zero_val |
1836 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345380 |
1 |
|
|
T1 |
46 |
|
T2 |
330 |
|
T3 |
242 |
lower_val |
345118 |
1 |
|
|
T1 |
28 |
|
T2 |
290 |
|
T3 |
250 |
zero_val |
4 |
1 |
|
|
T162 |
2 |
|
T163 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[0]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45036 |
1 |
|
|
T3 |
73 |
|
T13 |
72 |
|
T14 |
26 |
higher_val |
higher_val |
auto[1] |
41807 |
1 |
|
|
T1 |
7 |
|
T2 |
74 |
|
T14 |
15 |
higher_val |
lower_val |
auto[0] |
45125 |
1 |
|
|
T3 |
63 |
|
T13 |
65 |
|
T14 |
15 |
higher_val |
lower_val |
auto[1] |
41568 |
1 |
|
|
T1 |
7 |
|
T2 |
71 |
|
T14 |
11 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T163 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
44895 |
1 |
|
|
T3 |
57 |
|
T13 |
61 |
|
T14 |
10 |
lower_val |
higher_val |
auto[1] |
40634 |
1 |
|
|
T1 |
16 |
|
T2 |
84 |
|
T14 |
12 |
lower_val |
lower_val |
auto[0] |
44372 |
1 |
|
|
T2 |
1 |
|
T3 |
57 |
|
T13 |
43 |
lower_val |
lower_val |
auto[1] |
40913 |
1 |
|
|
T1 |
7 |
|
T2 |
69 |
|
T14 |
11 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T162 |
1 |
|
T163 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
676 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
233 |
1 |
|
|
T2 |
2 |
|
T16 |
1 |
|
T164 |
6 |
zero_val |
lower_val |
auto[0] |
700 |
1 |
|
|
T2 |
1 |
|
T15 |
1 |
|
T4 |
1 |
zero_val |
lower_val |
auto[1] |
227 |
1 |
|
|
T16 |
1 |
|
T165 |
1 |
|
T69 |
2 |