Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10353	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8961	1			T2	24		T14	3		T16	17
len_5001_7500	14248	1			T2	24		T3	33		T13	33
len_2501_5000	9185	1			T2	24		T3	34		T13	34
len_1025_2500	5403	1			T2	14		T3	20		T13	20
len_769_1024	6053	1			T1	5		T2	2		T3	4
len_513_768	6478	1			T1	6		T2	3		T3	3
len_257_512	21008	1			T1	8		T2	2		T3	4
len_0_256	257118	1			T1	5		T2	211		T3	148
len_keccak_block_sizes[72]	724	1			T2	2		T3	2		T13	2
len_keccak_block_sizes[104]	620	1			T2	2		T16	2		T93	3
len_keccak_block_sizes[136]	519	1			T16	2		T93	3		T38	1
len_keccak_block_sizes[144]	427	1			T16	2		T93	3		T38	1
len_keccak_block_sizes[168]	315	1			T93	3		T38	1		T39	1
len_1	762	1			T2	2		T3	2		T13	2
len_0	1195	1			T2	2		T3	2		T13	2