Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100089410	1			T1	3342		T2	159804		T3	112240
all_pins[1]	100089410	1			T1	3342		T2	159804		T3	112240
all_pins[2]	100089410	1			T1	3342		T2	159804		T3	112240

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299483542	1			T1	9998		T2	478959		T3	336346
values[0x1]	784688	1			T1	28		T2	453		T3	374
transitions[0x0=>0x1]	783001	1			T1	28		T2	453		T3	374
transitions[0x1=>0x0]	783028	1			T1	28		T2	453		T3	374

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99582439	1			T1	3314		T2	159351		T3	111866
all_pins[0]	values[0x1]	506971	1			T1	28		T2	453		T3	374
all_pins[0]	transitions[0x0=>0x1]	506955	1			T1	28		T2	453		T3	374
all_pins[0]	transitions[0x1=>0x0]	45	1			T44	2		T180	6		T181	2
all_pins[1]	values[0x0]	100089349	1			T1	3342		T2	159804		T3	112240
all_pins[1]	values[0x1]	61	1			T44	2		T180	6		T181	2
all_pins[1]	transitions[0x0=>0x1]	53	1			T44	2		T180	6		T181	2
all_pins[1]	transitions[0x1=>0x0]	277648	1			T14	2887		T19	16683		T25	618
all_pins[2]	values[0x0]	99811754	1			T1	3342		T2	159804		T3	112240
all_pins[2]	values[0x1]	277656	1			T14	2887		T19	16683		T25	618
all_pins[2]	transitions[0x0=>0x1]	275993	1			T14	2865		T19	16572		T25	613
all_pins[2]	transitions[0x1=>0x0]	505335	1			T1	28		T2	453		T3	374