Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	643	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5216	1			T1	3		T14	17		T17	4
len_601_800	12176	1			T1	6		T14	30		T17	9
len_401_600	8185	1			T1	11		T14	21		T18	3
len_201_400	16303	1			T1	4		T14	11		T17	1
len_65_200	73664	1			T14	5		T17	2		T18	1
len_min_for_xof_require_squeeze	1005	1			T93	10		T164	10		T165	9
len_keccak_block_sizes[72]	751	1			T93	5		T95	2		T164	5
len_keccak_block_sizes[104]	754	1			T14	1		T93	5		T95	1
len_keccak_block_sizes[136]	759	1			T93	5		T95	1		T164	5
len_keccak_block_sizes[144]	286	1			T93	5		T164	5		T191	5
len_keccak_block_sizes[168]	278	1			T93	5		T95	1		T164	5
len_datapath_width	13999	1			T3	246		T13	246		T15	3
len_2_63	213942	1			T1	13		T2	310		T14	35
len_1	57	1			T95	2		T192	1		T193	2