Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100058101	1			T1	293		T2	108737		T3	4991
all_values[1]	100058101	1			T1	293		T2	108737		T3	4991
all_values[2]	100058101	1			T1	293		T2	108737		T3	4991

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

546738

1

T1

26

T2

1510

T3

753

auto[1]

299627565

1

T1

853

T2

324701

T3

14220

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298640031

1

T1

846

T2

325905

T3

14469

auto[1]

1534272

1

T1

33

T2

306

T3

504

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	153609	1			T1	7		T2	1506		T3	398
all_values[0]	auto[0]	auto[1]	1988	1			T1	2		T2	4		T3	6
all_values[0]	auto[1]	auto[0]	99393068	1			T1	275		T2	107129		T3	4425
all_values[0]	auto[1]	auto[1]	509436	1			T1	9		T2	98		T3	162
all_values[1]	auto[0]	auto[0]	159599	1			T3	258		T13	1		T14	37
all_values[1]	auto[0]	auto[1]	1598	1			T3	5		T13	2		T14	3
all_values[1]	auto[1]	auto[0]	99387078	1			T1	282		T2	108635		T3	4565
all_values[1]	auto[1]	auto[1]	509826	1			T1	11		T2	102		T3	163
all_values[2]	auto[0]	auto[0]	228370	1			T1	14		T3	81		T14	11
all_values[2]	auto[0]	auto[1]	1574	1			T1	3		T3	5		T14	1
all_values[2]	auto[1]	auto[0]	99318307	1			T1	268		T2	108635		T3	4742
all_values[2]	auto[1]	auto[1]	509850	1			T1	8		T2	102		T3	163