Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
295746 |
1 |
|
|
T1 |
18 |
|
T2 |
138 |
|
T3 |
124 |
auto[1] |
399982 |
1 |
|
|
T3 |
150 |
|
T13 |
490 |
|
T16 |
158 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175354 |
1 |
|
|
T1 |
3 |
|
T2 |
34 |
|
T3 |
70 |
lower_val |
171251 |
1 |
|
|
T1 |
4 |
|
T2 |
38 |
|
T3 |
67 |
zero_val |
1777 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347896 |
1 |
|
|
T1 |
4 |
|
T2 |
72 |
|
T3 |
118 |
lower_val |
347820 |
1 |
|
|
T1 |
14 |
|
T2 |
66 |
|
T3 |
156 |
zero_val |
12 |
1 |
|
|
T168 |
2 |
|
T169 |
2 |
|
T170 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
36894 |
1 |
|
|
T2 |
18 |
|
T3 |
11 |
|
T14 |
46 |
higher_val |
higher_val |
auto[1] |
50789 |
1 |
|
|
T3 |
20 |
|
T13 |
48 |
|
T16 |
27 |
higher_val |
lower_val |
auto[0] |
37391 |
1 |
|
|
T1 |
3 |
|
T2 |
16 |
|
T3 |
20 |
higher_val |
lower_val |
auto[1] |
50275 |
1 |
|
|
T3 |
19 |
|
T13 |
69 |
|
T16 |
25 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T171 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
4 |
1 |
|
|
T168 |
2 |
|
T172 |
1 |
|
T173 |
1 |
lower_val |
higher_val |
auto[0] |
36333 |
1 |
|
|
T1 |
2 |
|
T2 |
19 |
|
T3 |
16 |
lower_val |
higher_val |
auto[1] |
49450 |
1 |
|
|
T3 |
16 |
|
T13 |
47 |
|
T16 |
21 |
lower_val |
lower_val |
auto[0] |
36003 |
1 |
|
|
T1 |
2 |
|
T2 |
19 |
|
T3 |
12 |
lower_val |
lower_val |
auto[1] |
49463 |
1 |
|
|
T3 |
23 |
|
T13 |
73 |
|
T16 |
15 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T170 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T172 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
649 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
226 |
1 |
|
|
T16 |
1 |
|
T17 |
1 |
|
T18 |
1 |
zero_val |
lower_val |
auto[0] |
634 |
1 |
|
|
T3 |
2 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
268 |
1 |
|
|
T16 |
1 |
|
T17 |
1 |
|
T19 |
2 |