Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100058101	1			T1	293		T2	108737		T3	4991
all_pins[1]	100058101	1			T1	293		T2	108737		T3	4991
all_pins[2]	100058101	1			T1	293		T2	108737		T3	4991

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299320883	1			T1	870		T2	326113		T3	14811
values[0x1]	853420	1			T1	9		T2	98		T3	162
transitions[0x0=>0x1]	851343	1			T1	9		T2	98		T3	162
transitions[0x1=>0x0]	851362	1			T1	9		T2	98		T3	162

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99548665	1			T1	284		T2	108639		T3	4829
all_pins[0]	values[0x1]	509436	1			T1	9		T2	98		T3	162
all_pins[0]	transitions[0x0=>0x1]	509423	1			T1	9		T2	98		T3	162
all_pins[0]	transitions[0x1=>0x0]	55	1			T44	4		T178	7		T179	2
all_pins[1]	values[0x0]	100058033	1			T1	293		T2	108737		T3	4991
all_pins[1]	values[0x1]	68	1			T44	4		T178	7		T179	2
all_pins[1]	transitions[0x0=>0x1]	55	1			T44	4		T178	7		T179	2
all_pins[1]	transitions[0x1=>0x0]	343903	1			T19	3913		T23	5593		T24	282
all_pins[2]	values[0x0]	99714185	1			T1	293		T2	108737		T3	4991
all_pins[2]	values[0x1]	343916	1			T19	3913		T23	5593		T24	282
all_pins[2]	transitions[0x0=>0x1]	341865	1			T19	3885		T23	5559		T24	281
all_pins[2]	transitions[0x1=>0x0]	507404	1			T1	9		T2	98		T3	162