Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	633	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5655	1			T2	9		T3	5		T14	23
len_601_800	12441	1			T2	20		T3	29		T14	50
len_401_600	8284	1			T2	19		T3	9		T14	41
len_201_400	16517	1			T2	9		T3	6		T14	13
len_65_200	74176	1			T2	6		T3	25		T14	15
len_min_for_xof_require_squeeze	1001	1			T17	1		T19	1		T96	9
len_keccak_block_sizes[72]	746	1			T16	1		T18	1		T37	2
len_keccak_block_sizes[104]	757	1			T3	1		T16	2		T96	9
len_keccak_block_sizes[136]	756	1			T96	9		T23	1		T199	5
len_keccak_block_sizes[144]	289	1			T19	1		T199	5		T153	1
len_keccak_block_sizes[168]	279	1			T18	1		T37	1		T199	5
len_datapath_width	14043	1			T1	3		T2	1		T3	6
len_2_63	214937	1			T1	6		T2	5		T3	56
len_1	47	1			T201	1		T41	1		T44	1