Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341608 |
1 |
|
|
T1 |
9 |
|
T2 |
67 |
|
T3 |
147 |
auto[1] |
3324 |
1 |
|
|
T3 |
7 |
|
T17 |
20 |
|
T19 |
18 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
307228 |
1 |
|
|
T2 |
20 |
|
T3 |
50 |
|
T13 |
237 |
auto[1] |
37704 |
1 |
|
|
T1 |
9 |
|
T2 |
47 |
|
T3 |
104 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
331081 |
1 |
|
|
T1 |
9 |
|
T2 |
67 |
|
T3 |
138 |
auto[1] |
13851 |
1 |
|
|
T3 |
16 |
|
T17 |
42 |
|
T19 |
60 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13851 |
1 |
|
|
T3 |
16 |
|
T17 |
42 |
|
T19 |
60 |
sw_kmac_invalid_sideload |
331081 |
1 |
|
|
T1 |
9 |
|
T2 |
67 |
|
T3 |
138 |
app_valid_sideload |
13851 |
1 |
|
|
T3 |
16 |
|
T17 |
42 |
|
T19 |
60 |
app_invalid_sideload |
331081 |
1 |
|
|
T1 |
9 |
|
T2 |
67 |
|
T3 |
138 |