Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100191407	1			T1	163229		T2	6038		T4	110532
all_values[1]	100191407	1			T1	163229		T2	6038		T4	110532
all_values[2]	100191407	1			T1	163229		T2	6038		T4	110532

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

479646

1

T1

3

T4

3

T14

22

auto[1]

300094575

1

T1

489684

T2

18114

T4

331593

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299049093

1

T1

488283

T2

17931

T4

330465

auto[1]

1525128

1

T1

1404

T2

183

T4

1131

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	155232	1			T1	1		T14	1		T15	18
all_values[0]	auto[0]	auto[1]	2060	1			T1	2		T14	2		T15	4
all_values[0]	auto[1]	auto[0]	99527799	1			T1	162760		T2	5977		T4	110155
all_values[0]	auto[1]	auto[1]	506316	1			T1	466		T2	61		T4	377
all_values[1]	auto[0]	auto[0]	146746	1			T4	2		T14	1		T16	113
all_values[1]	auto[0]	auto[1]	1304	1			T4	1		T14	2		T16	2
all_values[1]	auto[1]	auto[0]	99536285	1			T1	162761		T2	5977		T4	110153
all_values[1]	auto[1]	auto[1]	507072	1			T1	468		T2	61		T4	376
all_values[2]	auto[0]	auto[0]	172695	1			T14	10		T16	263		T17	43
all_values[2]	auto[0]	auto[1]	1609	1			T14	6		T16	4		T17	5
all_values[2]	auto[1]	auto[0]	99510336	1			T1	162761		T2	5977		T4	110155
all_values[2]	auto[1]	auto[1]	506767	1			T1	468		T2	61		T4	377