Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
66212 |
1 |
|
|
T1 |
59 |
|
T2 |
7 |
|
T4 |
57 |
auto[Key192] |
66358 |
1 |
|
|
T1 |
68 |
|
T2 |
7 |
|
T4 |
50 |
auto[Key256] |
80196 |
1 |
|
|
T1 |
68 |
|
T2 |
28 |
|
T4 |
58 |
auto[Key384] |
66099 |
1 |
|
|
T1 |
55 |
|
T2 |
11 |
|
T4 |
44 |
auto[Key512] |
66542 |
1 |
|
|
T1 |
60 |
|
T2 |
12 |
|
T4 |
37 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
312707 |
1 |
|
|
T1 |
310 |
|
T2 |
36 |
|
T4 |
246 |
auto[1] |
32700 |
1 |
|
|
T2 |
29 |
|
T15 |
113 |
|
T16 |
81 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
67265 |
1 |
|
|
T1 |
310 |
|
T2 |
1 |
|
T4 |
246 |
auto[Shake] |
241872 |
1 |
|
|
T2 |
23 |
|
T15 |
26 |
|
T16 |
45 |
auto[CShake] |
36270 |
1 |
|
|
T2 |
41 |
|
T15 |
113 |
|
T16 |
108 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172463 |
1 |
|
|
T1 |
164 |
|
T2 |
33 |
|
T4 |
118 |
auto[1] |
172944 |
1 |
|
|
T1 |
146 |
|
T2 |
32 |
|
T4 |
128 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335654 |
1 |
|
|
T1 |
310 |
|
T2 |
59 |
|
T4 |
246 |
auto[1] |
9753 |
1 |
|
|
T2 |
6 |
|
T16 |
22 |
|
T17 |
29 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172776 |
1 |
|
|
T1 |
172 |
|
T2 |
32 |
|
T4 |
120 |
auto[1] |
172631 |
1 |
|
|
T1 |
138 |
|
T2 |
33 |
|
T4 |
126 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
138893 |
1 |
|
|
T2 |
30 |
|
T15 |
72 |
|
T16 |
51 |
auto[L224] |
19815 |
1 |
|
|
T15 |
7 |
|
T17 |
1 |
|
T28 |
2 |
auto[L256] |
158269 |
1 |
|
|
T2 |
34 |
|
T14 |
374 |
|
T15 |
72 |
auto[L384] |
15805 |
1 |
|
|
T1 |
310 |
|
T2 |
1 |
|
T15 |
3 |
auto[L512] |
12625 |
1 |
|
|
T4 |
246 |
|
T15 |
6 |
|
T93 |
246 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327298 |
1 |
|
|
T1 |
310 |
|
T2 |
53 |
|
T4 |
246 |
auto[1] |
18109 |
1 |
|
|
T2 |
12 |
|
T15 |
80 |
|
T16 |
30 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
32700 |
1 |
|
|
T2 |
29 |
|
T15 |
113 |
|
T16 |
81 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
36270 |
1 |
|
|
T2 |
41 |
|
T15 |
113 |
|
T16 |
108 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
241872 |
1 |
|
|
T2 |
23 |
|
T15 |
26 |
|
T16 |
45 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
67265 |
1 |
|
|
T1 |
310 |
|
T2 |
1 |
|
T4 |
246 |