Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359244 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
2 |
auto[1] |
333536 |
1 |
|
|
T1 |
618 |
|
T2 |
128 |
|
T4 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173355 |
1 |
|
|
T1 |
146 |
|
T2 |
30 |
|
T4 |
116 |
lower_val |
171300 |
1 |
|
|
T1 |
144 |
|
T2 |
26 |
|
T4 |
120 |
zero_val |
1750 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345556 |
1 |
|
|
T1 |
322 |
|
T2 |
74 |
|
T4 |
252 |
lower_val |
347220 |
1 |
|
|
T1 |
298 |
|
T2 |
56 |
|
T4 |
240 |
zero_val |
4 |
1 |
|
|
T162 |
2 |
|
T163 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44658 |
1 |
|
|
T4 |
1 |
|
T15 |
39 |
|
T16 |
36 |
higher_val |
higher_val |
auto[1] |
41385 |
1 |
|
|
T1 |
79 |
|
T2 |
17 |
|
T4 |
61 |
higher_val |
lower_val |
auto[0] |
45461 |
1 |
|
|
T15 |
45 |
|
T16 |
32 |
|
T17 |
15 |
higher_val |
lower_val |
auto[1] |
41851 |
1 |
|
|
T1 |
67 |
|
T2 |
13 |
|
T4 |
54 |
lower_val |
higher_val |
auto[0] |
44279 |
1 |
|
|
T15 |
32 |
|
T16 |
41 |
|
T17 |
6 |
lower_val |
higher_val |
auto[1] |
41448 |
1 |
|
|
T1 |
70 |
|
T2 |
16 |
|
T4 |
61 |
lower_val |
lower_val |
auto[0] |
44230 |
1 |
|
|
T15 |
29 |
|
T16 |
36 |
|
T17 |
9 |
lower_val |
lower_val |
auto[1] |
41343 |
1 |
|
|
T1 |
74 |
|
T2 |
10 |
|
T4 |
59 |
zero_val |
higher_val |
auto[0] |
646 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
210 |
1 |
|
|
T28 |
2 |
|
T64 |
4 |
|
T65 |
3 |
zero_val |
lower_val |
auto[0] |
697 |
1 |
|
|
T17 |
2 |
|
T47 |
1 |
|
T27 |
1 |
zero_val |
lower_val |
auto[1] |
197 |
1 |
|
|
T28 |
1 |
|
T64 |
2 |
|
T65 |
1 |