Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100191407	1			T1	163229		T2	6038		T4	110532
all_pins[1]	100191407	1			T1	163229		T2	6038		T4	110532
all_pins[2]	100191407	1			T1	163229		T2	6038		T4	110532

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299805709	1			T1	489221		T2	18053		T4	331219
values[0x1]	768512	1			T1	466		T2	61		T4	377
transitions[0x0=>0x1]	766891	1			T1	466		T2	61		T4	377
transitions[0x1=>0x0]	766908	1			T1	466		T2	61		T4	377

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99685091	1			T1	162763		T2	5977		T4	110155
all_pins[0]	values[0x1]	506316	1			T1	466		T2	61		T4	377
all_pins[0]	transitions[0x0=>0x1]	506300	1			T1	466		T2	61		T4	377
all_pins[0]	transitions[0x1=>0x0]	59	1			T175	5		T176	2		T177	4
all_pins[1]	values[0x0]	100191332	1			T1	163229		T2	6038		T4	110532
all_pins[1]	values[0x1]	75	1			T175	5		T176	2		T177	4
all_pins[1]	transitions[0x0=>0x1]	66	1			T175	5		T176	2		T177	4
all_pins[1]	transitions[0x1=>0x0]	262112	1			T17	1097		T31	101		T25	8630
all_pins[2]	values[0x0]	99929286	1			T1	163229		T2	6038		T4	110532
all_pins[2]	values[0x1]	262121	1			T17	1097		T31	101		T25	8630
all_pins[2]	transitions[0x0=>0x1]	260525	1			T17	1089		T31	101		T25	8568
all_pins[2]	transitions[0x1=>0x0]	504737	1			T1	466		T2	61		T4	377