Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10588118 |
1 |
|
|
T1 |
3720 |
|
T2 |
6885 |
|
T4 |
3936 |
auto[1] |
25527875 |
1 |
|
|
T1 |
15500 |
|
T2 |
10938 |
|
T4 |
12300 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
35997566 |
1 |
|
|
T1 |
19220 |
|
T2 |
17790 |
|
T4 |
16236 |
triple_byte_access |
39211 |
1 |
|
|
T2 |
16 |
|
T15 |
37 |
|
T16 |
26 |
halfword_access |
39708 |
1 |
|
|
T2 |
7 |
|
T15 |
38 |
|
T16 |
25 |
byte_access |
39508 |
1 |
|
|
T2 |
10 |
|
T15 |
35 |
|
T16 |
25 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10469691 |
1 |
|
|
T1 |
3720 |
|
T2 |
6852 |
|
T4 |
3936 |
auto[0] |
triple_byte_access |
39211 |
1 |
|
|
T2 |
16 |
|
T15 |
37 |
|
T16 |
26 |
auto[0] |
halfword_access |
39708 |
1 |
|
|
T2 |
7 |
|
T15 |
38 |
|
T16 |
25 |
auto[0] |
byte_access |
39508 |
1 |
|
|
T2 |
10 |
|
T15 |
35 |
|
T16 |
25 |
auto[1] |
word_access |
25527875 |
1 |
|
|
T1 |
15500 |
|
T2 |
10938 |
|
T4 |
12300 |