Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100429072	1			T1	464436		T2	7440		T3	1335
all_values[1]	100429072	1			T1	464436		T2	7440		T3	1335
all_values[2]	100429072	1			T1	464436		T2	7440		T3	1335

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

505993

1

T2

198

T3

44

T14

3

auto[1]

300781223

1

T1

139330

T2

22122

T3

3961

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299753952

1

T1

138310

T2

22107

T3

3633

auto[1]

1533264

1

T1

10203

T2

213

T3

372

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	186862	1			T18	879		T41	1		T23	20
all_values[0]	auto[0]	auto[1]	2102	1			T18	8		T41	2		T23	6
all_values[0]	auto[1]	auto[0]	99731122	1			T1	461035		T2	7369		T3	1211
all_values[0]	auto[1]	auto[1]	508986	1			T1	3401		T2	71		T3	124
all_values[1]	auto[0]	auto[0]	169780	1			T2	1		T3	13		T15	2
all_values[1]	auto[0]	auto[1]	1562	1			T3	1		T15	1		T18	2
all_values[1]	auto[1]	auto[0]	99748204	1			T1	461035		T2	7368		T3	1198
all_values[1]	auto[1]	auto[1]	509526	1			T1	3401		T2	71		T3	123
all_values[2]	auto[0]	auto[0]	144173	1			T2	194		T3	28		T14	2
all_values[2]	auto[0]	auto[1]	1514	1			T2	3		T3	2		T14	1
all_values[2]	auto[1]	auto[0]	99773811	1			T1	461035		T2	7175		T3	1183
all_values[2]	auto[1]	auto[1]	509574	1			T1	3401		T2	68		T3	122