Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350860 |
1 |
|
|
T1 |
4530 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
342938 |
1 |
|
|
T2 |
154 |
|
T3 |
162 |
|
T17 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173813 |
1 |
|
|
T1 |
1117 |
|
T2 |
36 |
|
T3 |
38 |
lower_val |
171669 |
1 |
|
|
T1 |
1176 |
|
T2 |
44 |
|
T3 |
37 |
zero_val |
1790 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346906 |
1 |
|
|
T1 |
2380 |
|
T2 |
60 |
|
T3 |
104 |
lower_val |
346880 |
1 |
|
|
T1 |
2150 |
|
T2 |
96 |
|
T3 |
60 |
zero_val |
12 |
1 |
|
|
T157 |
2 |
|
T158 |
2 |
|
T159 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43728 |
1 |
|
|
T1 |
580 |
|
T13 |
41 |
|
T14 |
109 |
higher_val |
higher_val |
auto[1] |
42896 |
1 |
|
|
T2 |
16 |
|
T3 |
22 |
|
T17 |
104 |
higher_val |
lower_val |
auto[0] |
44088 |
1 |
|
|
T1 |
537 |
|
T2 |
1 |
|
T13 |
40 |
higher_val |
lower_val |
auto[1] |
43098 |
1 |
|
|
T2 |
19 |
|
T3 |
16 |
|
T17 |
78 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T160 |
1 |
|
T161 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T72 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43318 |
1 |
|
|
T1 |
613 |
|
T13 |
42 |
|
T14 |
116 |
lower_val |
higher_val |
auto[1] |
42379 |
1 |
|
|
T2 |
14 |
|
T3 |
22 |
|
T17 |
96 |
lower_val |
lower_val |
auto[0] |
43286 |
1 |
|
|
T1 |
563 |
|
T13 |
48 |
|
T14 |
92 |
lower_val |
lower_val |
auto[1] |
42682 |
1 |
|
|
T2 |
30 |
|
T3 |
15 |
|
T17 |
84 |
lower_val |
zero_val |
auto[0] |
4 |
1 |
|
|
T157 |
1 |
|
T159 |
2 |
|
T161 |
1 |
zero_val |
higher_val |
auto[0] |
667 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T13 |
4 |
zero_val |
higher_val |
auto[1] |
226 |
1 |
|
|
T2 |
1 |
|
T19 |
1 |
|
T24 |
1 |
zero_val |
lower_val |
auto[0] |
670 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
227 |
1 |
|
|
T2 |
1 |
|
T19 |
1 |
|
T23 |
2 |