Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100429072	1			T1	464436		T2	7440		T3	1335
all_pins[1]	100429072	1			T1	464436		T2	7440		T3	1335
all_pins[2]	100429072	1			T1	464436		T2	7440		T3	1335

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300458863	1			T1	138990		T2	22249		T3	3881
values[0x1]	828353	1			T1	3401		T2	71		T3	124
transitions[0x0=>0x1]	826363	1			T1	3401		T2	71		T3	124
transitions[0x1=>0x0]	826383	1			T1	3401		T2	71		T3	124

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99920086	1			T1	461035		T2	7369		T3	1211
all_pins[0]	values[0x1]	508986	1			T1	3401		T2	71		T3	124
all_pins[0]	transitions[0x0=>0x1]	508972	1			T1	3401		T2	71		T3	124
all_pins[0]	transitions[0x1=>0x0]	60	1			T42	5		T164	2		T169	15
all_pins[1]	values[0x0]	100428998	1			T1	464436		T2	7440		T3	1335
all_pins[1]	values[0x1]	74	1			T42	5		T164	2		T169	15
all_pins[1]	transitions[0x0=>0x1]	66	1			T42	5		T164	2		T169	15
all_pins[1]	transitions[0x1=>0x0]	319285	1			T13	770		T27	368		T23	1202
all_pins[2]	values[0x0]	100109779	1			T1	464436		T2	7440		T3	1335
all_pins[2]	values[0x1]	319293	1			T13	770		T27	368		T23	1202
all_pins[2]	transitions[0x0=>0x1]	317325	1			T13	770		T27	368		T23	1192
all_pins[2]	transitions[0x1=>0x0]	507038	1			T1	3401		T2	71		T3	124