Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102376693	1			T1	2451		T2	567297		T3	218647
all_values[1]	102376693	1			T1	2451		T2	567297		T3	218647
all_values[2]	102376693	1			T1	2451		T2	567297		T3	218647

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620739

1

T1

66

T3

3

T14

2

auto[1]

306509340

1

T1

7287

T2

170189

T3

655938

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305593005

1

T1

6684

T2

169145

T3

654150

auto[1]

1537074

1

T1

669

T2

10440

T3

1791

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	195749	1			T14	1		T15	332		T17	1
all_values[0]	auto[0]	auto[1]	1979	1			T15	10		T17	2		T18	4
all_values[0]	auto[1]	auto[0]	101668586	1			T1	2228		T2	563817		T3	218050
all_values[0]	auto[1]	auto[1]	510379	1			T1	223		T2	3480		T3	597
all_values[1]	auto[0]	auto[0]	214591	1			T1	39		T3	2		T15	340
all_values[1]	auto[0]	auto[1]	1678	1			T1	2		T3	1		T15	10
all_values[1]	auto[1]	auto[0]	101649744	1			T1	2189		T2	563817		T3	218048
all_values[1]	auto[1]	auto[1]	510680	1			T1	221		T2	3480		T3	596
all_values[2]	auto[0]	auto[0]	205106	1			T1	24		T14	1		T15	85
all_values[2]	auto[0]	auto[1]	1636	1			T1	1		T15	7		T16	3
all_values[2]	auto[1]	auto[0]	101659229	1			T1	2204		T2	563817		T3	218050
all_values[2]	auto[1]	auto[1]	510722	1			T1	222		T2	3480		T3	597