Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
311146 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
386338 |
1 |
|
|
T1 |
296 |
|
T2 |
4672 |
|
T3 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174294 |
1 |
|
|
T1 |
63 |
|
T2 |
1168 |
|
T3 |
160 |
lower_val |
172926 |
1 |
|
|
T1 |
76 |
|
T2 |
1221 |
|
T3 |
186 |
zero_val |
1786 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
349322 |
1 |
|
|
T1 |
146 |
|
T2 |
2386 |
|
T3 |
382 |
lower_val |
348154 |
1 |
|
|
T1 |
152 |
|
T2 |
2288 |
|
T3 |
398 |
zero_val |
8 |
1 |
|
|
T104 |
2 |
|
T147 |
2 |
|
T148 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39241 |
1 |
|
|
T4 |
1 |
|
T14 |
19 |
|
T15 |
55 |
higher_val |
higher_val |
auto[1] |
48481 |
1 |
|
|
T1 |
29 |
|
T2 |
602 |
|
T3 |
77 |
higher_val |
lower_val |
auto[0] |
38524 |
1 |
|
|
T14 |
12 |
|
T15 |
49 |
|
T16 |
5 |
higher_val |
lower_val |
auto[1] |
48047 |
1 |
|
|
T1 |
34 |
|
T2 |
566 |
|
T3 |
83 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T104 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
38510 |
1 |
|
|
T2 |
1 |
|
T14 |
12 |
|
T15 |
50 |
lower_val |
higher_val |
auto[1] |
47941 |
1 |
|
|
T1 |
46 |
|
T2 |
617 |
|
T3 |
82 |
lower_val |
lower_val |
auto[0] |
38726 |
1 |
|
|
T14 |
10 |
|
T15 |
48 |
|
T17 |
93 |
lower_val |
lower_val |
auto[1] |
47749 |
1 |
|
|
T1 |
30 |
|
T2 |
603 |
|
T3 |
104 |
zero_val |
higher_val |
auto[0] |
665 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
219 |
1 |
|
|
T85 |
2 |
|
T86 |
5 |
|
T149 |
1 |
zero_val |
lower_val |
auto[0] |
648 |
1 |
|
|
T3 |
1 |
|
T14 |
1 |
|
T15 |
2 |
zero_val |
lower_val |
auto[1] |
254 |
1 |
|
|
T1 |
2 |
|
T15 |
1 |
|
T85 |
2 |