Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9388	1			T1	30		T2	30		T3	17
len_5001_7500	15236	1			T1	71		T2	30		T3	17
len_2501_5000	9365	1			T1	12		T2	30		T3	17
len_1025_2500	5517	1			T1	12		T2	16		T3	10
len_769_1024	6091	1			T1	3		T2	4		T3	2
len_513_768	6630	1			T2	2		T3	2		T14	4
len_257_512	21023	1			T1	3		T2	244		T3	2
len_0_256	258213	1			T1	18		T2	1897		T3	290
len_keccak_block_sizes[72]	720	1			T2	3		T3	2		T17	2
len_keccak_block_sizes[104]	614	1			T2	3		T3	2		T17	2
len_keccak_block_sizes[136]	524	1			T2	3		T3	2		T17	2
len_keccak_block_sizes[144]	425	1			T2	3		T3	2		T85	3
len_keccak_block_sizes[168]	321	1			T2	3		T15	1		T85	3
len_1	771	1			T2	3		T3	2		T17	2
len_0	1249	1			T1	9		T2	3		T3	2