Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102376693	1			T1	2451		T2	567297		T3	218647
all_pins[1]	102376693	1			T1	2451		T2	567297		T3	218647
all_pins[2]	102376693	1			T1	2451		T2	567297		T3	218647

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	306302315	1			T1	7130		T2	169841		T3	655344
values[0x1]	827764	1			T1	223		T2	3480		T3	597
transitions[0x0=>0x1]	825795	1			T1	223		T2	3480		T3	597
transitions[0x1=>0x0]	825816	1			T1	223		T2	3480		T3	597

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101866314	1			T1	2228		T2	563817		T3	218050
all_pins[0]	values[0x1]	510379	1			T1	223		T2	3480		T3	597
all_pins[0]	transitions[0x0=>0x1]	510369	1			T1	223		T2	3480		T3	597
all_pins[0]	transitions[0x1=>0x0]	75	1			T42	5		T163	2		T164	2
all_pins[1]	values[0x0]	102376608	1			T1	2451		T2	567297		T3	218647
all_pins[1]	values[0x1]	85	1			T42	5		T163	2		T164	2
all_pins[1]	transitions[0x0=>0x1]	62	1			T42	5		T163	2		T164	2
all_pins[1]	transitions[0x1=>0x0]	317277	1			T15	6445		T28	733		T24	2309
all_pins[2]	values[0x0]	102059393	1			T1	2451		T2	567297		T3	218647
all_pins[2]	values[0x1]	317300	1			T15	6445		T28	733		T24	2309
all_pins[2]	transitions[0x0=>0x1]	315364	1			T15	6405		T28	733		T24	2293
all_pins[2]	transitions[0x1=>0x0]	508464	1			T1	223		T2	3480		T3	597