Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99921073	1			T1	3		T2	96489		T3	17461
all_values[1]	99921073	1			T1	3		T2	96489		T3	17461
all_values[2]	99921073	1			T1	3		T2	96489		T3	17461

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620522

1

T1

6

T2

15720

T3

2

auto[1]

299142697

1

T1

3

T2

273747

T3

52381

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298240440

1

T1

9

T2

289167

T3

51843

auto[1]

1522779

1

T2

300

T3

540

T9

489

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	197496	1			T1	3		T2	5234		T14	136
all_values[0]	auto[0]	auto[1]	2208	1			T2	6		T14	4		T17	2
all_values[0]	auto[1]	auto[0]	99215984	1			T2	91155		T3	17281		T9	16398
all_values[0]	auto[1]	auto[1]	505385	1			T2	94		T3	180		T9	163
all_values[1]	auto[0]	auto[0]	220928	1			T2	5234		T9	1		T13	45
all_values[1]	auto[0]	auto[1]	1608	1			T2	6		T13	6		T16	1
all_values[1]	auto[1]	auto[0]	99192552	1			T1	3		T2	91155		T3	17281
all_values[1]	auto[1]	auto[1]	505985	1			T2	94		T3	180		T9	163
all_values[2]	auto[0]	auto[0]	196561	1			T1	3		T2	5234		T3	2
all_values[2]	auto[0]	auto[1]	1721	1			T2	6		T9	2		T15	1
all_values[2]	auto[1]	auto[0]	99216919	1			T2	91155		T3	17279		T9	16330
all_values[2]	auto[1]	auto[1]	505872	1			T2	94		T3	180		T9	161