Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
352044 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
338022 |
1 |
|
|
T2 |
130 |
|
T3 |
322 |
|
T9 |
292 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172147 |
1 |
|
|
T2 |
28 |
|
T3 |
82 |
|
T9 |
59 |
lower_val |
170177 |
1 |
|
|
T2 |
35 |
|
T3 |
74 |
|
T9 |
72 |
zero_val |
1846 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345238 |
1 |
|
|
T1 |
2 |
|
T2 |
74 |
|
T3 |
194 |
lower_val |
344816 |
1 |
|
|
T2 |
58 |
|
T3 |
130 |
|
T9 |
154 |
zero_val |
12 |
1 |
|
|
T153 |
2 |
|
T154 |
2 |
|
T155 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44074 |
1 |
|
|
T14 |
39 |
|
T15 |
57 |
|
T17 |
13 |
higher_val |
higher_val |
auto[1] |
42192 |
1 |
|
|
T2 |
14 |
|
T3 |
52 |
|
T9 |
27 |
higher_val |
lower_val |
auto[0] |
43916 |
1 |
|
|
T2 |
1 |
|
T14 |
31 |
|
T15 |
60 |
higher_val |
lower_val |
auto[1] |
41958 |
1 |
|
|
T2 |
13 |
|
T3 |
30 |
|
T9 |
32 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T153 |
1 |
|
T156 |
2 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
4 |
1 |
|
|
T154 |
1 |
|
T155 |
1 |
|
T157 |
2 |
lower_val |
higher_val |
auto[0] |
43464 |
1 |
|
|
T14 |
29 |
|
T15 |
57 |
|
T17 |
13 |
lower_val |
higher_val |
auto[1] |
41794 |
1 |
|
|
T2 |
22 |
|
T3 |
45 |
|
T9 |
32 |
lower_val |
lower_val |
auto[0] |
43162 |
1 |
|
|
T14 |
32 |
|
T15 |
63 |
|
T17 |
13 |
lower_val |
lower_val |
auto[1] |
41755 |
1 |
|
|
T2 |
13 |
|
T3 |
29 |
|
T9 |
40 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T153 |
1 |
|
T158 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
673 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
216 |
1 |
|
|
T16 |
1 |
|
T18 |
1 |
|
T19 |
2 |
zero_val |
lower_val |
auto[0] |
722 |
1 |
|
|
T2 |
1 |
|
T9 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
235 |
1 |
|
|
T16 |
1 |
|
T17 |
1 |
|
T18 |
3 |