Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99921073	1			T1	3		T2	96489		T3	17461
all_pins[1]	99921073	1			T1	3		T2	96489		T3	17461
all_pins[2]	99921073	1			T1	3		T2	96489		T3	17461

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298983794	1			T1	9		T2	289373		T3	52203
values[0x1]	779425	1			T2	94		T3	180		T9	163
transitions[0x0=>0x1]	777677	1			T2	94		T3	180		T9	163
transitions[0x1=>0x0]	777699	1			T2	94		T3	180		T9	163

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99415688	1			T1	3		T2	96395		T3	17281
all_pins[0]	values[0x1]	505385	1			T2	94		T3	180		T9	163
all_pins[0]	transitions[0x0=>0x1]	505370	1			T2	94		T3	180		T9	163
all_pins[0]	transitions[0x1=>0x0]	67	1			T13	3		T171	2		T172	4
all_pins[1]	values[0x0]	99920991	1			T1	3		T2	96489		T3	17461
all_pins[1]	values[0x1]	82	1			T13	3		T171	2		T172	4
all_pins[1]	transitions[0x0=>0x1]	74	1			T13	3		T171	2		T172	4
all_pins[1]	transitions[0x1=>0x0]	273950	1			T16	10772		T27	398		T46	205
all_pins[2]	values[0x0]	99647115	1			T1	3		T2	96489		T3	17461
all_pins[2]	values[0x1]	273958	1			T16	10772		T27	398		T46	205
all_pins[2]	transitions[0x0=>0x1]	272233	1			T16	10707		T27	398		T46	205
all_pins[2]	transitions[0x1=>0x0]	503682	1			T2	94		T3	180		T9	163