Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	600	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5158	1			T2	12		T3	28		T9	11
len_601_800	12112	1			T2	27		T3	49		T9	48
len_401_600	7875	1			T2	16		T3	25		T9	25
len_201_400	16309	1			T2	5		T3	12		T9	9
len_65_200	73539	1			T2	4		T3	3		T9	5
len_min_for_xof_require_squeeze	999	1			T18	10		T66	1		T67	9
len_keccak_block_sizes[72]	748	1			T18	5		T88	1		T67	9
len_keccak_block_sizes[104]	758	1			T18	5		T66	1		T67	9
len_keccak_block_sizes[136]	759	1			T14	1		T18	5		T66	2
len_keccak_block_sizes[144]	274	1			T18	5		T184	5		T185	2
len_keccak_block_sizes[168]	285	1			T18	5		T135	1		T184	5
len_datapath_width	14082	1			T2	1		T13	1		T14	1
len_2_63	214368	1			T2	1		T3	43		T9	48
len_1	54	1			T88	1		T135	2		T185	1