Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10430830 |
1 |
|
|
T2 |
11461 |
|
T3 |
23469 |
|
T9 |
18821 |
| auto[1] |
25289337 |
1 |
|
|
T2 |
16588 |
|
T3 |
34944 |
|
T9 |
28184 |
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| word_access |
35602397 |
1 |
|
|
T2 |
27997 |
|
T3 |
58322 |
|
T9 |
46921 |
| triple_byte_access |
39210 |
1 |
|
|
T2 |
25 |
|
T3 |
30 |
|
T9 |
29 |
| halfword_access |
39505 |
1 |
|
|
T2 |
12 |
|
T3 |
36 |
|
T9 |
29 |
| byte_access |
39055 |
1 |
|
|
T2 |
15 |
|
T3 |
25 |
|
T9 |
26 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
word_access |
10313060 |
1 |
|
|
T2 |
11409 |
|
T3 |
23378 |
|
T9 |
18737 |
| auto[0] |
triple_byte_access |
39210 |
1 |
|
|
T2 |
25 |
|
T3 |
30 |
|
T9 |
29 |
| auto[0] |
halfword_access |
39505 |
1 |
|
|
T2 |
12 |
|
T3 |
36 |
|
T9 |
29 |
| auto[0] |
byte_access |
39055 |
1 |
|
|
T2 |
15 |
|
T3 |
25 |
|
T9 |
26 |
| auto[1] |
word_access |
25289337 |
1 |
|
|
T2 |
16588 |
|
T3 |
34944 |
|
T9 |
28184 |