Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99581621	1			T3	302		T13	104		T16	16507
all_values[1]	99581621	1			T3	302		T13	104		T16	16507
all_values[2]	99581621	1			T3	302		T13	104		T16	16507

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

472008

1

T3

101

T13

7

T16

108

auto[1]

298272855

1

T3

805

T13

305

T16

49413

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297215643

1

T3

870

T13

273

T16

49056

auto[1]

1529220

1

T3

36

T13

39

T16

465

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	146475	1			T3	4		T17	1		T74	1
all_values[0]	auto[0]	auto[1]	1933	1			T3	2		T17	2		T74	2
all_values[0]	auto[1]	auto[0]	98925406	1			T3	286		T13	91		T16	16352
all_values[0]	auto[1]	auto[1]	507807	1			T3	10		T13	13		T16	155
all_values[1]	auto[0]	auto[0]	153496	1			T13	6		T16	53		T17	1
all_values[1]	auto[0]	auto[1]	1558	1			T13	1		T16	1		T17	2
all_values[1]	auto[1]	auto[0]	98918385	1			T3	290		T13	85		T16	16299
all_values[1]	auto[1]	auto[1]	508182	1			T3	12		T13	12		T16	154
all_values[2]	auto[0]	auto[0]	167025	1			T3	90		T16	53		T17	1
all_values[2]	auto[0]	auto[1]	1521	1			T3	5		T16	1		T17	2
all_values[2]	auto[1]	auto[0]	98904856	1			T3	200		T13	91		T16	16299
all_values[2]	auto[1]	auto[1]	508219	1			T3	7		T13	13		T16	154