Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345330 |
1 |
|
|
T3 |
18 |
|
T13 |
2 |
|
T16 |
214 |
auto[1] |
346956 |
1 |
|
|
T13 |
16 |
|
T17 |
778 |
|
T19 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172888 |
1 |
|
|
T3 |
4 |
|
T13 |
2 |
|
T16 |
42 |
lower_val |
171800 |
1 |
|
|
T3 |
10 |
|
T13 |
1 |
|
T16 |
61 |
zero_val |
1709 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T16 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347192 |
1 |
|
|
T3 |
6 |
|
T13 |
4 |
|
T16 |
104 |
lower_val |
345092 |
1 |
|
|
T3 |
12 |
|
T13 |
14 |
|
T16 |
110 |
zero_val |
2 |
1 |
|
|
T153 |
2 |
|
- |
- |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43203 |
1 |
|
|
T3 |
1 |
|
T16 |
21 |
|
T74 |
54 |
higher_val |
higher_val |
auto[1] |
43839 |
1 |
|
|
T17 |
106 |
|
T19 |
68 |
|
T23 |
24 |
higher_val |
lower_val |
auto[0] |
42832 |
1 |
|
|
T3 |
3 |
|
T16 |
21 |
|
T74 |
80 |
higher_val |
lower_val |
auto[1] |
43013 |
1 |
|
|
T13 |
2 |
|
T17 |
83 |
|
T19 |
90 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T153 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
42974 |
1 |
|
|
T3 |
4 |
|
T16 |
32 |
|
T74 |
62 |
lower_val |
higher_val |
auto[1] |
43330 |
1 |
|
|
T17 |
92 |
|
T19 |
93 |
|
T23 |
14 |
lower_val |
lower_val |
auto[0] |
42559 |
1 |
|
|
T3 |
6 |
|
T16 |
29 |
|
T17 |
1 |
lower_val |
lower_val |
auto[1] |
42936 |
1 |
|
|
T13 |
1 |
|
T17 |
103 |
|
T19 |
92 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T153 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
659 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
227 |
1 |
|
|
T17 |
2 |
|
T23 |
2 |
|
T24 |
4 |
zero_val |
lower_val |
auto[0] |
618 |
1 |
|
|
T17 |
1 |
|
T19 |
1 |
|
T22 |
1 |
zero_val |
lower_val |
auto[1] |
205 |
1 |
|
|
T23 |
1 |
|
T24 |
1 |
|
T87 |
2 |