Group : kmac_env_pkg::kmac_env_cov::error_cg
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Group : kmac_env_pkg::kmac_env_cov::error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
89.66 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 21 3 18 85.71
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cmd 4 0 4 100.00 100 1 1 0
kmac_err_code 9 3 6 66.67 100 1 1 0
mode 3 0 3 100.00 100 1 1 0
strength 5 0 5 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_invalid_cmd_in_app_active 1 0 1 100.00 100 1 1 0
all_invalid_mode_strength_cfgs 7 0 7 100.00 100 1 1 0


Summary for Variable cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[CmdNone] 0 Excluded
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CmdStart] 598 1 T22 11 T30 2 T31 12
auto[CmdProcess] 72 1 T31 3 T32 2 T33 1
auto[CmdManualRun] 232 1 T31 12 T32 4 T33 5
auto[CmdDone] 1201 1 T22 16 T30 4 T45 4



Summary for Variable kmac_err_code

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 9 3 6 66.67


Automatically Generated Bins for kmac_err_code

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[ErrFatalError] 0 1 1
auto[ErrPackerIntegrity] 0 1 1
auto[ErrMsgFifoIntegrity] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
auto[ErrNone] 0 Excluded
auto[ErrWaitTimerExpired] 0 Illegal
auto[ErrIncorrectEntropyMode] 0 Illegal
auto[ErrSwHashingWithoutEntropyReady] 0 Illegal
auto[ErrShadowRegUpdate] 0 Illegal
il 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ErrKeyNotValid] 50 1 T1 1 T18 1 T21 1
auto[ErrSwPushedMsgFifo] 45 1 T22 2 T31 1 T32 1
auto[ErrSwIssuedCmdInAppActive] 35 1 T22 1 T31 1 T32 2
auto[ErrUnexpectedModeStrength] 534 1 T22 7 T30 1 T45 2
auto[ErrIncorrectFunctionName] 518 1 T22 8 T30 2 T31 12
auto[ErrSwCmdSequence] 985 1 T22 9 T30 3 T45 2



Summary for Variable mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[Sha3] 351 1 T22 4 T45 1 T31 14
auto[Shake] 341 1 T22 1 T45 3 T31 9
auto[CShake] 1425 1 T22 22 T30 6 T31 48



Summary for Variable strength

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for strength

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[L128] 757 1 T22 13 T30 1 T45 1
auto[L224] 223 1 T22 1 T31 7 T32 8
auto[L256] 661 1 T1 1 T18 1 T22 7
auto[L384] 267 1 T22 1 T30 3 T45 3
auto[L512] 259 1 T22 5 T31 11 T32 7



Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
invalid_cmds 35 1 T22 1 T31 1 T32 2



Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 7 0 7 100.00


User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha3_128_cfgs 153 1 T22 2 T45 1 T31 7
shake_224_invalid_cfg 20 1 T32 1 T159 1 T160 2
shake_384_invalid_cfg 36 1 T45 1 T31 1 T73 2
shake_512_invalid_cfg 43 1 T31 1 T32 2 T73 1
cshake_224_invalid_cfg 86 1 T22 1 T31 3 T32 3
cshake_384_invalid_cfg 104 1 T22 1 T30 1 T31 5
cshake_512_invalid_cfg 92 1 T22 3 T31 4 T32 3

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