Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99581621	1			T3	302		T13	104		T16	16507
all_pins[1]	99581621	1			T3	302		T13	104		T16	16507
all_pins[2]	99581621	1			T3	302		T13	104		T16	16507

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297929525	1			T3	896		T13	299		T16	49366
values[0x1]	815338	1			T3	10		T13	13		T16	155
transitions[0x0=>0x1]	813475	1			T3	10		T13	13		T16	155
transitions[0x1=>0x0]	813494	1			T3	10		T13	13		T16	155

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99073814	1			T3	292		T13	91		T16	16352
all_pins[0]	values[0x1]	507807	1			T3	10		T13	13		T16	155
all_pins[0]	transitions[0x0=>0x1]	507792	1			T3	10		T13	13		T16	155
all_pins[0]	transitions[0x1=>0x0]	68	1			T39	2		T167	7		T168	4
all_pins[1]	values[0x0]	99581538	1			T3	302		T13	104		T16	16507
all_pins[1]	values[0x1]	83	1			T39	2		T167	7		T168	4
all_pins[1]	transitions[0x0=>0x1]	67	1			T39	2		T167	7		T168	4
all_pins[1]	transitions[0x1=>0x0]	307432	1			T22	57		T24	2828		T30	108
all_pins[2]	values[0x0]	99274173	1			T3	302		T13	104		T16	16507
all_pins[2]	values[0x1]	307448	1			T22	57		T24	2828		T30	108
all_pins[2]	transitions[0x0=>0x1]	305616	1			T22	57		T24	2804		T30	108
all_pins[2]	transitions[0x1=>0x0]	505994	1			T3	10		T13	13		T16	155