Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100417328	1			T1	14984		T2	563059		T3	4421
all_values[1]	100417328	1			T1	14984		T2	563059		T3	4421
all_values[2]	100417328	1			T1	14984		T2	563059		T3	4421

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

510850

1

T1

138

T2

10

T3

550

auto[1]

300741134

1

T1

44814

T2

168916

T3

12713

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299722866

1

T1

44538

T2

167865

T3

13116

auto[1]

1529118

1

T1

414

T2

10524

T3

147

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	159511	1			T1	136		T2	3		T3	402
all_values[0]	auto[0]	auto[1]	2001	1			T1	2		T2	4		T3	6
all_values[0]	auto[1]	auto[0]	99748111	1			T1	14710		T2	559548		T3	3970
all_values[0]	auto[1]	auto[1]	507705	1			T1	136		T2	3504		T3	43
all_values[1]	auto[0]	auto[0]	165110	1			T3	140		T12	1		T15	6424
all_values[1]	auto[0]	auto[1]	1466	1			T3	2		T12	2		T15	5
all_values[1]	auto[1]	auto[0]	99742512	1			T1	14846		T2	559551		T3	4232
all_values[1]	auto[1]	auto[1]	508240	1			T1	138		T2	3508		T3	47
all_values[2]	auto[0]	auto[0]	181117	1			T2	1		T12	1		T15	1925
all_values[2]	auto[0]	auto[1]	1645	1			T2	2		T12	2		T15	2
all_values[2]	auto[1]	auto[0]	99726505	1			T1	14846		T2	559550		T3	4372
all_values[2]	auto[1]	auto[1]	508061	1			T1	138		T2	3506		T3	49