Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
324744 |
1 |
|
|
T1 |
242 |
|
T2 |
2 |
|
T3 |
98 |
auto[1] |
368502 |
1 |
|
|
T2 |
4672 |
|
T12 |
4672 |
|
T13 |
292 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173681 |
1 |
|
|
T1 |
67 |
|
T2 |
1147 |
|
T3 |
34 |
lower_val |
172190 |
1 |
|
|
T1 |
76 |
|
T2 |
1116 |
|
T3 |
22 |
zero_val |
1736 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346186 |
1 |
|
|
T1 |
126 |
|
T2 |
2382 |
|
T3 |
46 |
lower_val |
347046 |
1 |
|
|
T1 |
116 |
|
T2 |
2292 |
|
T3 |
52 |
zero_val |
14 |
1 |
|
|
T141 |
2 |
|
T142 |
2 |
|
T143 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40316 |
1 |
|
|
T1 |
42 |
|
T2 |
1 |
|
T3 |
15 |
higher_val |
higher_val |
auto[1] |
46495 |
1 |
|
|
T2 |
583 |
|
T12 |
600 |
|
T13 |
46 |
higher_val |
lower_val |
auto[0] |
40326 |
1 |
|
|
T1 |
25 |
|
T3 |
19 |
|
T17 |
54 |
higher_val |
lower_val |
auto[1] |
46538 |
1 |
|
|
T2 |
563 |
|
T12 |
570 |
|
T13 |
44 |
higher_val |
zero_val |
auto[0] |
4 |
1 |
|
|
T141 |
1 |
|
T143 |
1 |
|
T144 |
2 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T142 |
2 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
40703 |
1 |
|
|
T1 |
40 |
|
T3 |
10 |
|
T14 |
1 |
lower_val |
higher_val |
auto[1] |
45580 |
1 |
|
|
T2 |
548 |
|
T12 |
585 |
|
T13 |
23 |
lower_val |
lower_val |
auto[0] |
40540 |
1 |
|
|
T1 |
36 |
|
T3 |
12 |
|
T17 |
44 |
lower_val |
lower_val |
auto[1] |
45365 |
1 |
|
|
T2 |
568 |
|
T12 |
529 |
|
T13 |
29 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T143 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T145 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
640 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
223 |
1 |
|
|
T2 |
3 |
|
T65 |
1 |
|
T67 |
1 |
zero_val |
lower_val |
auto[0] |
627 |
1 |
|
|
T13 |
1 |
|
T17 |
1 |
|
T94 |
2 |
zero_val |
lower_val |
auto[1] |
246 |
1 |
|
|
T2 |
3 |
|
T65 |
1 |
|
T67 |
1 |