Summary for Variable cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cmd
Excluded/Illegal bins
NAME | COUNT | STATUS |
auto[CmdNone] |
0 |
Excluded |
ignore |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[CmdStart] |
628 |
1 |
|
|
T14 |
12 |
|
T28 |
15 |
|
T29 |
18 |
auto[CmdProcess] |
87 |
1 |
|
|
T14 |
1 |
|
T28 |
9 |
|
T29 |
4 |
auto[CmdManualRun] |
285 |
1 |
|
|
T14 |
5 |
|
T28 |
26 |
|
T29 |
13 |
auto[CmdDone] |
1320 |
1 |
|
|
T14 |
28 |
|
T28 |
47 |
|
T29 |
37 |
Summary for Variable kmac_err_code
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
9 |
3 |
6 |
66.67 |
Automatically Generated Bins for kmac_err_code
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[ErrFatalError] |
0 |
1 |
1 |
|
auto[ErrPackerIntegrity] |
0 |
1 |
1 |
|
auto[ErrMsgFifoIntegrity] |
0 |
1 |
1 |
|
Excluded/Illegal bins
NAME | COUNT | STATUS |
auto[ErrNone] |
0 |
Excluded |
auto[ErrWaitTimerExpired] |
0 |
Illegal |
auto[ErrIncorrectEntropyMode] |
0 |
Illegal |
auto[ErrSwHashingWithoutEntropyReady] |
0 |
Illegal |
auto[ErrShadowRegUpdate] |
0 |
Illegal |
il |
0 |
Illegal |
ignore |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[ErrKeyNotValid] |
50 |
1 |
|
|
T19 |
1 |
|
T20 |
1 |
|
T21 |
1 |
auto[ErrSwPushedMsgFifo] |
55 |
1 |
|
|
T14 |
1 |
|
T29 |
4 |
|
T137 |
1 |
auto[ErrSwIssuedCmdInAppActive] |
59 |
1 |
|
|
T14 |
1 |
|
T28 |
2 |
|
T29 |
2 |
auto[ErrUnexpectedModeStrength] |
578 |
1 |
|
|
T14 |
15 |
|
T28 |
20 |
|
T29 |
17 |
auto[ErrIncorrectFunctionName] |
535 |
1 |
|
|
T14 |
10 |
|
T28 |
13 |
|
T29 |
15 |
auto[ErrSwCmdSequence] |
1105 |
1 |
|
|
T14 |
19 |
|
T28 |
62 |
|
T29 |
34 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
384 |
1 |
|
|
T14 |
8 |
|
T28 |
19 |
|
T29 |
6 |
auto[Shake] |
346 |
1 |
|
|
T14 |
11 |
|
T28 |
13 |
|
T29 |
12 |
auto[CShake] |
1602 |
1 |
|
|
T14 |
27 |
|
T28 |
65 |
|
T29 |
54 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
844 |
1 |
|
|
T14 |
18 |
|
T28 |
48 |
|
T29 |
22 |
auto[L224] |
292 |
1 |
|
|
T14 |
4 |
|
T28 |
10 |
|
T29 |
11 |
auto[L256] |
746 |
1 |
|
|
T14 |
10 |
|
T19 |
1 |
|
T20 |
1 |
auto[L384] |
235 |
1 |
|
|
T14 |
9 |
|
T28 |
7 |
|
T29 |
2 |
auto[L512] |
265 |
1 |
|
|
T14 |
5 |
|
T28 |
6 |
|
T29 |
11 |
Summary for Cross all_invalid_cmd_in_app_active
Samples crossed: kmac_err_code cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for all_invalid_cmd_in_app_active
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
invalid_cmds |
59 |
1 |
|
|
T14 |
1 |
|
T28 |
2 |
|
T29 |
2 |
Summary for Cross all_invalid_mode_strength_cfgs
Samples crossed: kmac_err_code mode strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
7 |
0 |
7 |
100.00 |
|
User Defined Cross Bins for all_invalid_mode_strength_cfgs
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sha3_128_cfgs |
177 |
1 |
|
|
T14 |
5 |
|
T28 |
9 |
|
T29 |
3 |
shake_224_invalid_cfg |
36 |
1 |
|
|
T28 |
3 |
|
T29 |
2 |
|
T138 |
1 |
shake_384_invalid_cfg |
24 |
1 |
|
|
T14 |
3 |
|
T28 |
1 |
|
T137 |
1 |
shake_512_invalid_cfg |
34 |
1 |
|
|
T139 |
1 |
|
T138 |
1 |
|
T140 |
1 |
cshake_224_invalid_cfg |
107 |
1 |
|
|
T14 |
2 |
|
T28 |
1 |
|
T29 |
5 |
cshake_384_invalid_cfg |
99 |
1 |
|
|
T14 |
2 |
|
T28 |
2 |
|
T29 |
2 |
cshake_512_invalid_cfg |
101 |
1 |
|
|
T14 |
3 |
|
T28 |
4 |
|
T29 |
5 |