Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10353	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8973	1			T2	30		T12	30		T13	30
len_5001_7500	14304	1			T2	30		T12	30		T13	81
len_2501_5000	9196	1			T2	30		T12	30		T13	9
len_1025_2500	5393	1			T2	16		T12	16		T13	10
len_769_1024	6361	1			T1	30		T2	4		T3	7
len_513_768	6710	1			T1	17		T2	2		T3	8
len_257_512	21173	1			T1	27		T2	244		T3	6
len_0_256	257208	1			T1	21		T2	1897		T3	11
len_keccak_block_sizes[72]	718	1			T2	3		T12	3		T94	2
len_keccak_block_sizes[104]	624	1			T2	3		T12	3		T94	2
len_keccak_block_sizes[136]	517	1			T2	3		T12	3		T14	1
len_keccak_block_sizes[144]	437	1			T2	3		T12	3		T50	2
len_keccak_block_sizes[168]	316	1			T2	3		T12	3		T67	3
len_1	757	1			T2	3		T12	3		T17	1
len_0	1198	1			T2	3		T12	3		T13	3