Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100417328	1			T1	14984		T2	563059		T3	4421
all_pins[1]	100417328	1			T1	14984		T2	563059		T3	4421
all_pins[2]	100417328	1			T1	14984		T2	563059		T3	4421

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300419877	1			T1	29928		T2	168567		T3	13220
values[0x1]	832107	1			T1	15024		T2	3504		T3	43
transitions[0x0=>0x1]	830063	1			T1	14929		T2	3504		T3	43
transitions[0x1=>0x0]	830087	1			T1	14930		T2	3504		T3	43

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99909623	1			T1	14848		T2	559555		T3	4378
all_pins[0]	values[0x1]	507705	1			T1	136		T2	3504		T3	43
all_pins[0]	transitions[0x0=>0x1]	507688	1			T1	136		T2	3504		T3	43
all_pins[0]	transitions[0x1=>0x0]	47	1			T37	3		T153	3		T154	2
all_pins[1]	values[0x0]	100417264	1			T1	14984		T2	563059		T3	4421
all_pins[1]	values[0x1]	64	1			T37	3		T153	3		T154	2
all_pins[1]	transitions[0x0=>0x1]	49	1			T37	3		T153	3		T154	2
all_pins[1]	transitions[0x1=>0x0]	324323	1			T1	14888		T14	546		T22	1161
all_pins[2]	values[0x0]	100092990	1			T1	96		T2	563059		T3	4421
all_pins[2]	values[0x1]	324338	1			T1	14888		T14	546		T22	1161
all_pins[2]	transitions[0x0=>0x1]	322326	1			T1	14793		T14	545		T22	1154
all_pins[2]	transitions[0x1=>0x0]	505717	1			T1	42		T2	3504		T3	43