Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99894079	1			T2	1348		T3	317		T13	21326
all_values[1]	99894079	1			T2	1348		T3	317		T13	21326
all_values[2]	99894079	1			T2	1348		T3	317		T13	21326

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

517231

1

T2

96

T3

24

T13

154

auto[1]

299165006

1

T2

3948

T3

927

T13

63824

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298155942

1

T2

3669

T3

909

T13

63339

auto[1]

1526295

1

T2

375

T3

42

T13

639

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	186963	1			T2	35		T14	1		T16	1
all_values[0]	auto[0]	auto[1]	2116	1			T2	4		T14	2		T16	2
all_values[0]	auto[1]	auto[0]	99198351	1			T2	1188		T3	303		T13	21113
all_values[0]	auto[1]	auto[1]	506649	1			T2	121		T3	14		T13	213
all_values[1]	auto[0]	auto[0]	174675	1			T2	35		T3	14		T15	10
all_values[1]	auto[0]	auto[1]	1554	1			T2	4		T3	3		T15	1
all_values[1]	auto[1]	auto[0]	99210639	1			T2	1188		T3	289		T13	21113
all_values[1]	auto[1]	auto[1]	507211	1			T2	121		T3	11		T13	213
all_values[2]	auto[0]	auto[0]	150465	1			T2	16		T3	6		T13	153
all_values[2]	auto[0]	auto[1]	1458	1			T2	2		T3	1		T13	1
all_values[2]	auto[1]	auto[0]	99234849	1			T2	1207		T3	297		T13	20960
all_values[2]	auto[1]	auto[1]	507307	1			T2	123		T3	13		T13	212