Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
66393 |
1 |
|
|
T2 |
12 |
|
T13 |
22 |
|
T14 |
444 |
auto[Key192] |
65766 |
1 |
|
|
T2 |
18 |
|
T13 |
18 |
|
T14 |
476 |
auto[Key256] |
80054 |
1 |
|
|
T2 |
14 |
|
T3 |
9 |
|
T13 |
39 |
auto[Key384] |
66247 |
1 |
|
|
T2 |
18 |
|
T13 |
26 |
|
T14 |
433 |
auto[Key512] |
66502 |
1 |
|
|
T2 |
21 |
|
T13 |
20 |
|
T14 |
461 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
312437 |
1 |
|
|
T2 |
28 |
|
T13 |
36 |
|
T14 |
2265 |
auto[1] |
32525 |
1 |
|
|
T2 |
55 |
|
T3 |
9 |
|
T13 |
89 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
67297 |
1 |
|
|
T2 |
2 |
|
T13 |
3 |
|
T15 |
4 |
auto[Shake] |
241798 |
1 |
|
|
T2 |
26 |
|
T13 |
27 |
|
T14 |
2265 |
auto[CShake] |
35867 |
1 |
|
|
T2 |
55 |
|
T3 |
9 |
|
T13 |
95 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172507 |
1 |
|
|
T2 |
40 |
|
T3 |
7 |
|
T13 |
58 |
auto[1] |
172455 |
1 |
|
|
T2 |
43 |
|
T3 |
2 |
|
T13 |
67 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335441 |
1 |
|
|
T2 |
83 |
|
T3 |
9 |
|
T13 |
105 |
auto[1] |
9521 |
1 |
|
|
T13 |
20 |
|
T18 |
61 |
|
T24 |
9 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172597 |
1 |
|
|
T2 |
40 |
|
T3 |
3 |
|
T13 |
69 |
auto[1] |
172365 |
1 |
|
|
T2 |
43 |
|
T3 |
6 |
|
T13 |
56 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
138717 |
1 |
|
|
T2 |
38 |
|
T3 |
6 |
|
T13 |
47 |
auto[L224] |
19814 |
1 |
|
|
T13 |
1 |
|
T18 |
3 |
|
T41 |
1 |
auto[L256] |
157964 |
1 |
|
|
T2 |
43 |
|
T3 |
3 |
|
T13 |
76 |
auto[L384] |
15845 |
1 |
|
|
T30 |
1 |
|
T25 |
4 |
|
T39 |
2 |
auto[L512] |
12622 |
1 |
|
|
T2 |
2 |
|
T13 |
1 |
|
T15 |
1 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326879 |
1 |
|
|
T2 |
48 |
|
T3 |
9 |
|
T13 |
69 |
auto[1] |
18083 |
1 |
|
|
T2 |
35 |
|
T13 |
56 |
|
T15 |
18 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
32525 |
1 |
|
|
T2 |
55 |
|
T3 |
9 |
|
T13 |
89 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
35867 |
1 |
|
|
T2 |
55 |
|
T3 |
9 |
|
T13 |
95 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
241798 |
1 |
|
|
T2 |
26 |
|
T13 |
27 |
|
T14 |
2265 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
67297 |
1 |
|
|
T2 |
2 |
|
T13 |
3 |
|
T15 |
4 |