Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
366088 |
1 |
|
|
T2 |
166 |
|
T3 |
2 |
|
T13 |
2 |
auto[1] |
326022 |
1 |
|
|
T3 |
16 |
|
T13 |
306 |
|
T17 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173117 |
1 |
|
|
T2 |
33 |
|
T3 |
4 |
|
T13 |
75 |
lower_val |
171163 |
1 |
|
|
T2 |
30 |
|
T3 |
6 |
|
T13 |
90 |
zero_val |
1803 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345948 |
1 |
|
|
T2 |
74 |
|
T3 |
4 |
|
T13 |
140 |
lower_val |
346154 |
1 |
|
|
T2 |
92 |
|
T3 |
14 |
|
T13 |
168 |
zero_val |
8 |
1 |
|
|
T148 |
2 |
|
T149 |
2 |
|
T150 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45603 |
1 |
|
|
T2 |
19 |
|
T14 |
569 |
|
T15 |
14 |
higher_val |
higher_val |
auto[1] |
41032 |
1 |
|
|
T13 |
39 |
|
T17 |
3 |
|
T18 |
32 |
higher_val |
lower_val |
auto[0] |
45544 |
1 |
|
|
T2 |
14 |
|
T14 |
545 |
|
T15 |
14 |
higher_val |
lower_val |
auto[1] |
40936 |
1 |
|
|
T3 |
4 |
|
T13 |
36 |
|
T18 |
46 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T149 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
45369 |
1 |
|
|
T2 |
13 |
|
T13 |
1 |
|
T14 |
559 |
lower_val |
higher_val |
auto[1] |
39879 |
1 |
|
|
T3 |
1 |
|
T13 |
42 |
|
T17 |
3 |
lower_val |
lower_val |
auto[0] |
45547 |
1 |
|
|
T2 |
17 |
|
T14 |
570 |
|
T15 |
17 |
lower_val |
lower_val |
auto[1] |
40366 |
1 |
|
|
T3 |
5 |
|
T13 |
47 |
|
T17 |
4 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T151 |
2 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
674 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
232 |
1 |
|
|
T18 |
3 |
|
T30 |
2 |
|
T25 |
1 |
zero_val |
lower_val |
auto[0] |
702 |
1 |
|
|
T14 |
2 |
|
T15 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
195 |
1 |
|
|
T25 |
1 |
|
T70 |
1 |
|
T152 |
1 |