Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::error_cg

Group : kmac_env_pkg::kmac_env_cov::error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.66	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	3	18	85.71
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cmd	4	0	4	100.00	100	1	1	0
kmac_err_code	9	3	6	66.67	100	1	1	0
mode	3	0	3	100.00	100	1	1	0
strength	5	0	5	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_invalid_cmd_in_app_active	1	0	1	100.00	100	1	1	0
all_invalid_mode_strength_cfgs	7	0	7	100.00	100	1	1	0

Summary for Variable cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CmdNone]	0	Excluded
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CmdStart]	569	1			T13	16		T24	8		T30	17
auto[CmdProcess]	89	1			T13	1		T24	2		T30	3
auto[CmdManualRun]	297	1			T13	4		T24	11		T30	9
auto[CmdDone]	1271	1			T13	41		T24	8		T30	28

---

Summary for Variable kmac_err_code

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	9	3	6	66.67

Automatically Generated Bins for kmac_err_code

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ErrFatalError]	0	1	1
auto[ErrPackerIntegrity]	0	1	1
auto[ErrMsgFifoIntegrity]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[ErrNone]	0	Excluded
auto[ErrWaitTimerExpired]	0	Illegal
auto[ErrIncorrectEntropyMode]	0	Illegal
auto[ErrSwHashingWithoutEntropyReady]	0	Illegal
auto[ErrShadowRegUpdate]	0	Illegal
il	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ErrKeyNotValid]	50	1			T21	1		T22	1		T23	1
auto[ErrSwPushedMsgFifo]	47	1			T13	1		T24	1		T30	1
auto[ErrSwIssuedCmdInAppActive]	47	1			T13	4		T28	1		T31	2
auto[ErrUnexpectedModeStrength]	551	1			T13	16		T24	4		T30	14
auto[ErrIncorrectFunctionName]	484	1			T13	13		T24	6		T30	13
auto[ErrSwCmdSequence]	1113	1			T13	28		T24	18		T30	29

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	390	1			T13	17		T24	1		T30	10
auto[Shake]	370	1			T13	14		T30	10		T48	6
auto[CShake]	1482	1			T13	31		T24	28		T30	37

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	777	1			T13	22		T24	4		T30	26
auto[L224]	237	1			T13	9		T24	4		T30	11
auto[L256]	738	1			T13	22		T24	19		T30	15
auto[L384]	270	1			T13	6		T24	1		T30	3
auto[L512]	270	1			T13	3		T24	1		T30	2

---

Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

invalid_cmds

46

1

T13

4

T28

1

T31

2

---

Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	7	0	7	100.00

User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha3_128_cfgs	168	1			T13	6		T30	4		T48	1
shake_224_invalid_cfg	36	1			T13	2		T30	1		T71	1
shake_384_invalid_cfg	27	1			T13	1		T30	1		T28	1
shake_512_invalid_cfg	32	1			T13	1		T71	1		T156	3
cshake_224_invalid_cfg	86	1			T13	3		T24	2		T30	4
cshake_384_invalid_cfg	102	1			T13	1		T24	1		T30	2
cshake_512_invalid_cfg	100	1			T13	2		T24	1		T30	2