Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	10821819	1			T2	4980		T3	298		T13	16911
shake	55164179	1			T2	2008		T13	5018		T14	450937
sha3	35308867	1			T2	68		T13	1304		T15	25

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90471830

1

T2

2076

T13

6322

T14

450937

auto[1]

10823035

1

T2

4980

T3

298

T13

16911

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	100049368	1			T2	6997		T3	298		T13	23194
depth[0x01]	807780	1			T2	58		T13	39		T18	6120
depth[0x02]	142451	1			T2	1		T18	3992		T24	159
depth[0x03]	116879	1			T18	3273		T24	130		T41	1883
depth[0x04]	73859	1			T18	2175		T24	61		T41	1297
depth[0x05]	43630	1			T18	1265		T24	10		T41	836
depth[0x06]	18118	1			T18	631		T41	255		T42	613
depth[0x07]	280	1			T41	17		T26	16		T27	9
depth[0x08]	1439	1			T18	50		T41	20		T42	52
depth[0x09]	1142	1			T18	25		T41	40		T42	28
depth[0x0a]	39919	1			T18	1175		T41	831		T42	1232

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1245497

1

T2

59

T13

39

T18

18706

auto[1]

100049368

1

T2

6997

T3

298

T13

23194

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101254946

1

T2

7056

T3

298

T13

23233

auto[1]

39919

1

T18

1175

T41

831

T42

1232