Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99894079	1			T2	1348		T3	317		T13	21326
all_pins[1]	99894079	1			T2	1348		T3	317		T13	21326
all_pins[2]	99894079	1			T2	1348		T3	317		T13	21326

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298847900	1			T2	3923		T3	937		T13	63006
values[0x1]	834337	1			T2	121		T3	14		T13	972
transitions[0x0=>0x1]	832364	1			T2	121		T3	14		T13	972
transitions[0x1=>0x0]	832394	1			T2	121		T3	14		T13	972

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99387430	1			T2	1227		T3	303		T13	21113
all_pins[0]	values[0x1]	506649	1			T2	121		T3	14		T13	213
all_pins[0]	transitions[0x0=>0x1]	506637	1			T2	121		T3	14		T13	213
all_pins[0]	transitions[0x1=>0x0]	62	1			T26	2		T169	2		T170	3
all_pins[1]	values[0x0]	99894005	1			T2	1348		T3	317		T13	21326
all_pins[1]	values[0x1]	74	1			T26	2		T169	2		T170	3
all_pins[1]	transitions[0x0=>0x1]	62	1			T26	2		T169	2		T170	3
all_pins[1]	transitions[0x1=>0x0]	327602	1			T13	759		T24	75		T30	798
all_pins[2]	values[0x0]	99566465	1			T2	1348		T3	317		T13	20567
all_pins[2]	values[0x1]	327614	1			T13	759		T24	75		T30	798
all_pins[2]	transitions[0x0=>0x1]	325665	1			T13	759		T24	75		T30	798
all_pins[2]	transitions[0x1=>0x0]	504730	1			T2	121		T3	14		T13	213