Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	643	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5299	1			T2	13		T13	20		T18	41
len_601_800	12352	1			T2	30		T13	49		T18	92
len_401_600	8078	1			T2	18		T13	25		T18	77
len_201_400	16377	1			T2	8		T13	15		T14	251
len_65_200	73697	1			T2	6		T13	5		T14	680
len_min_for_xof_require_squeeze	1004	1			T14	10		T16	10		T30	1
len_keccak_block_sizes[72]	741	1			T2	1		T14	5		T15	1
len_keccak_block_sizes[104]	750	1			T14	5		T16	5		T89	9
len_keccak_block_sizes[136]	749	1			T14	5		T15	1		T16	5
len_keccak_block_sizes[144]	285	1			T14	5		T16	5		T25	1
len_keccak_block_sizes[168]	290	1			T14	5		T15	1		T16	5
len_datapath_width	14005	1			T2	2		T3	3		T13	1
len_2_63	214467	1			T2	2		T3	6		T13	10
len_1	44	1			T25	1		T173	1		T105	1