Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339672 |
1 |
|
|
T2 |
83 |
|
T3 |
8 |
|
T13 |
159 |
auto[1] |
3407 |
1 |
|
|
T13 |
2 |
|
T18 |
19 |
|
T30 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306643 |
1 |
|
|
T2 |
28 |
|
T13 |
52 |
|
T14 |
2208 |
auto[1] |
36436 |
1 |
|
|
T2 |
55 |
|
T3 |
8 |
|
T13 |
109 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330029 |
1 |
|
|
T2 |
83 |
|
T3 |
8 |
|
T13 |
135 |
auto[1] |
13050 |
1 |
|
|
T13 |
26 |
|
T18 |
80 |
|
T24 |
10 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13050 |
1 |
|
|
T13 |
26 |
|
T18 |
80 |
|
T24 |
10 |
sw_kmac_invalid_sideload |
330029 |
1 |
|
|
T2 |
83 |
|
T3 |
8 |
|
T13 |
135 |
app_valid_sideload |
13050 |
1 |
|
|
T13 |
26 |
|
T18 |
80 |
|
T24 |
10 |
app_invalid_sideload |
330029 |
1 |
|
|
T2 |
83 |
|
T3 |
8 |
|
T13 |
135 |