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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.30 95.89 92.27 100.00 68.60 94.11 98.84 96.43


Total test records in report: 1240
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T1058 /workspace/coverage/default/23.kmac_sideload.1986761867 Jul 09 05:50:40 PM PDT 24 Jul 09 05:54:08 PM PDT 24 3852445632 ps
T1059 /workspace/coverage/default/34.kmac_key_error.1362638604 Jul 09 05:51:54 PM PDT 24 Jul 09 05:52:02 PM PDT 24 5883528048 ps
T1060 /workspace/coverage/default/35.kmac_sideload.1350079122 Jul 09 05:51:54 PM PDT 24 Jul 09 05:57:33 PM PDT 24 17543021048 ps
T1061 /workspace/coverage/default/45.kmac_error.399093463 Jul 09 05:54:29 PM PDT 24 Jul 09 05:56:41 PM PDT 24 4724100905 ps
T1062 /workspace/coverage/default/35.kmac_smoke.3361118169 Jul 09 05:51:56 PM PDT 24 Jul 09 05:53:10 PM PDT 24 35136953270 ps
T1063 /workspace/coverage/default/2.kmac_alert_test.462655772 Jul 09 05:49:32 PM PDT 24 Jul 09 05:49:34 PM PDT 24 43498158 ps
T1064 /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3799303265 Jul 09 05:49:21 PM PDT 24 Jul 09 06:21:39 PM PDT 24 101004948143 ps
T1065 /workspace/coverage/default/0.kmac_edn_timeout_error.2584134323 Jul 09 05:49:28 PM PDT 24 Jul 09 05:49:35 PM PDT 24 191836517 ps
T1066 /workspace/coverage/default/13.kmac_test_vectors_sha3_256.3957806760 Jul 09 05:50:05 PM PDT 24 Jul 09 06:20:11 PM PDT 24 61762504421 ps
T1067 /workspace/coverage/default/44.kmac_sideload.4082613677 Jul 09 05:54:05 PM PDT 24 Jul 09 05:54:35 PM PDT 24 2527774391 ps
T1068 /workspace/coverage/default/26.kmac_test_vectors_shake_128.3144016233 Jul 09 05:50:57 PM PDT 24 Jul 09 07:18:36 PM PDT 24 2404095713908 ps
T1069 /workspace/coverage/default/0.kmac_test_vectors_kmac.1814628457 Jul 09 05:49:29 PM PDT 24 Jul 09 05:49:34 PM PDT 24 67259153 ps
T1070 /workspace/coverage/default/24.kmac_test_vectors_shake_256.2884169900 Jul 09 05:50:46 PM PDT 24 Jul 09 06:53:55 PM PDT 24 577933734631 ps
T1071 /workspace/coverage/default/2.kmac_edn_timeout_error.1388922333 Jul 09 05:49:41 PM PDT 24 Jul 09 05:49:53 PM PDT 24 1205559293 ps
T1072 /workspace/coverage/default/9.kmac_long_msg_and_output.3549506380 Jul 09 05:49:46 PM PDT 24 Jul 09 06:03:32 PM PDT 24 36396219220 ps
T1073 /workspace/coverage/default/30.kmac_error.1338093476 Jul 09 05:51:21 PM PDT 24 Jul 09 05:56:16 PM PDT 24 30458295119 ps
T1074 /workspace/coverage/default/30.kmac_key_error.3785125084 Jul 09 05:51:19 PM PDT 24 Jul 09 05:51:27 PM PDT 24 7426212480 ps
T1075 /workspace/coverage/default/9.kmac_sideload.1942958690 Jul 09 05:49:45 PM PDT 24 Jul 09 05:56:10 PM PDT 24 137107131359 ps
T1076 /workspace/coverage/default/9.kmac_test_vectors_sha3_224.2819478221 Jul 09 05:49:44 PM PDT 24 Jul 09 06:16:31 PM PDT 24 37962137667 ps
T1077 /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3152452093 Jul 09 05:51:13 PM PDT 24 Jul 09 06:05:22 PM PDT 24 34071133111 ps
T1078 /workspace/coverage/default/36.kmac_app.1683873020 Jul 09 05:52:10 PM PDT 24 Jul 09 05:52:36 PM PDT 24 1656266244 ps
T1079 /workspace/coverage/default/26.kmac_lc_escalation.2882483028 Jul 09 05:50:56 PM PDT 24 Jul 09 05:50:58 PM PDT 24 163244424 ps
T1080 /workspace/coverage/default/4.kmac_key_error.373218933 Jul 09 05:49:46 PM PDT 24 Jul 09 05:49:53 PM PDT 24 2333402227 ps
T1081 /workspace/coverage/default/4.kmac_alert_test.4046633213 Jul 09 05:49:47 PM PDT 24 Jul 09 05:49:53 PM PDT 24 28740724 ps
T1082 /workspace/coverage/default/43.kmac_error.1760376922 Jul 09 05:53:58 PM PDT 24 Jul 09 05:57:35 PM PDT 24 9593934418 ps
T115 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2114970121 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:58 PM PDT 24 375917847 ps
T93 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.289457291 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:00 PM PDT 24 89087135 ps
T112 /workspace/coverage/cover_reg_top/11.kmac_intr_test.2121449527 Jul 09 05:46:57 PM PDT 24 Jul 09 05:47:00 PM PDT 24 49651145 ps
T172 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.4267361626 Jul 09 05:47:07 PM PDT 24 Jul 09 05:47:12 PM PDT 24 414986869 ps
T127 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1474818434 Jul 09 05:46:48 PM PDT 24 Jul 09 05:46:50 PM PDT 24 43806860 ps
T113 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1437732400 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:54 PM PDT 24 15555184 ps
T1083 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3617769987 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:49 PM PDT 24 79995744 ps
T94 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.578001294 Jul 09 05:48:51 PM PDT 24 Jul 09 05:48:55 PM PDT 24 47409091 ps
T134 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.4182808034 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:08 PM PDT 24 96917942 ps
T116 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3512772382 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:55 PM PDT 24 172678085 ps
T117 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2215058832 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:10 PM PDT 24 268796133 ps
T1084 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1153191189 Jul 09 05:46:49 PM PDT 24 Jul 09 05:46:51 PM PDT 24 173052535 ps
T1085 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3968930969 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:03 PM PDT 24 94854670 ps
T109 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1019452750 Jul 09 05:47:03 PM PDT 24 Jul 09 05:47:10 PM PDT 24 264035037 ps
T114 /workspace/coverage/cover_reg_top/48.kmac_intr_test.267649480 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:02 PM PDT 24 13782008 ps
T118 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.886767909 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:02 PM PDT 24 60524771 ps
T110 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1548232126 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:05 PM PDT 24 337787465 ps
T119 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2274776763 Jul 09 05:46:37 PM PDT 24 Jul 09 05:46:39 PM PDT 24 72061417 ps
T120 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.416670208 Jul 09 05:47:02 PM PDT 24 Jul 09 05:47:07 PM PDT 24 37721349 ps
T135 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3836739563 Jul 09 05:47:02 PM PDT 24 Jul 09 05:47:05 PM PDT 24 71748360 ps
T136 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3749609753 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:01 PM PDT 24 72763897 ps
T111 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1817719378 Jul 09 05:46:44 PM PDT 24 Jul 09 05:46:47 PM PDT 24 127978867 ps
T95 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3727794939 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:59 PM PDT 24 388874035 ps
T157 /workspace/coverage/cover_reg_top/0.kmac_intr_test.375586956 Jul 09 05:46:44 PM PDT 24 Jul 09 05:46:46 PM PDT 24 152122279 ps
T1086 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2231920218 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:02 PM PDT 24 103412427 ps
T1087 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.617162706 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:56 PM PDT 24 135411403 ps
T137 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2718148523 Jul 09 05:46:56 PM PDT 24 Jul 09 05:46:58 PM PDT 24 123488150 ps
T96 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1590511344 Jul 09 05:46:57 PM PDT 24 Jul 09 05:46:59 PM PDT 24 33581400 ps
T1088 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2427312763 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:57 PM PDT 24 26101070 ps
T1089 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.732368581 Jul 09 05:46:44 PM PDT 24 Jul 09 05:46:46 PM PDT 24 44061414 ps
T102 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3082151962 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:54 PM PDT 24 28544669 ps
T1090 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.580057827 Jul 09 05:46:43 PM PDT 24 Jul 09 05:46:53 PM PDT 24 396890284 ps
T162 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3172433426 Jul 09 05:47:03 PM PDT 24 Jul 09 05:47:09 PM PDT 24 382663091 ps
T158 /workspace/coverage/cover_reg_top/10.kmac_intr_test.4087730361 Jul 09 05:46:50 PM PDT 24 Jul 09 05:46:52 PM PDT 24 21399441 ps
T1091 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1719575767 Jul 09 05:47:09 PM PDT 24 Jul 09 05:47:13 PM PDT 24 63467123 ps
T1092 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2599517942 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:56 PM PDT 24 116249818 ps
T138 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1327462163 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:50 PM PDT 24 121629524 ps
T142 /workspace/coverage/cover_reg_top/25.kmac_intr_test.570212425 Jul 09 05:47:09 PM PDT 24 Jul 09 05:47:13 PM PDT 24 14822738 ps
T128 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2645006608 Jul 09 05:46:39 PM PDT 24 Jul 09 05:46:41 PM PDT 24 111641942 ps
T143 /workspace/coverage/cover_reg_top/22.kmac_intr_test.4268307052 Jul 09 05:47:09 PM PDT 24 Jul 09 05:47:13 PM PDT 24 32875796 ps
T97 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.751220662 Jul 09 05:47:03 PM PDT 24 Jul 09 05:47:06 PM PDT 24 29644502 ps
T139 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.640456807 Jul 09 05:46:46 PM PDT 24 Jul 09 05:47:06 PM PDT 24 5007794610 ps
T145 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1915791982 Jul 09 05:46:49 PM PDT 24 Jul 09 05:46:51 PM PDT 24 122487565 ps
T100 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2935733684 Jul 09 05:47:09 PM PDT 24 Jul 09 05:47:15 PM PDT 24 374638413 ps
T108 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1077062121 Jul 09 05:46:57 PM PDT 24 Jul 09 05:46:59 PM PDT 24 39479689 ps
T1093 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.593954563 Jul 09 05:46:46 PM PDT 24 Jul 09 05:46:48 PM PDT 24 414799144 ps
T1094 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3138387463 Jul 09 05:46:44 PM PDT 24 Jul 09 05:46:50 PM PDT 24 428161344 ps
T1095 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2002968432 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:05 PM PDT 24 46867046 ps
T1096 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2237652633 Jul 09 05:46:54 PM PDT 24 Jul 09 05:46:56 PM PDT 24 26411132 ps
T140 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.29079665 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:03 PM PDT 24 227546103 ps
T1097 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3998037572 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:11 PM PDT 24 80792503 ps
T1098 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3487690813 Jul 09 05:46:53 PM PDT 24 Jul 09 05:46:58 PM PDT 24 887459244 ps
T129 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3443235719 Jul 09 05:46:45 PM PDT 24 Jul 09 05:46:47 PM PDT 24 20781336 ps
T1099 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1531914864 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:55 PM PDT 24 108060020 ps
T98 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1045418020 Jul 09 05:46:57 PM PDT 24 Jul 09 05:46:59 PM PDT 24 65808460 ps
T101 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3037460129 Jul 09 05:46:53 PM PDT 24 Jul 09 05:46:55 PM PDT 24 62361303 ps
T159 /workspace/coverage/cover_reg_top/14.kmac_intr_test.3232302063 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:02 PM PDT 24 42125614 ps
T141 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4275590409 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:48 PM PDT 24 102459922 ps
T1100 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1938815317 Jul 09 05:46:54 PM PDT 24 Jul 09 05:46:56 PM PDT 24 15403136 ps
T1101 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.99074991 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:03 PM PDT 24 96922656 ps
T161 /workspace/coverage/cover_reg_top/33.kmac_intr_test.4217854740 Jul 09 05:47:02 PM PDT 24 Jul 09 05:47:05 PM PDT 24 16510287 ps
T1102 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2249662817 Jul 09 05:47:07 PM PDT 24 Jul 09 05:47:12 PM PDT 24 35241956 ps
T1103 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1359622741 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:07 PM PDT 24 14842077 ps
T144 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3743143024 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:54 PM PDT 24 111359137 ps
T1104 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.456706299 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:58 PM PDT 24 723115740 ps
T146 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3418823383 Jul 09 05:46:56 PM PDT 24 Jul 09 05:47:00 PM PDT 24 459623181 ps
T1105 /workspace/coverage/cover_reg_top/35.kmac_intr_test.64793460 Jul 09 05:46:57 PM PDT 24 Jul 09 05:46:59 PM PDT 24 14727121 ps
T99 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.668628880 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:04 PM PDT 24 73300409 ps
T1106 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2668793015 Jul 09 05:46:56 PM PDT 24 Jul 09 05:47:09 PM PDT 24 1296236994 ps
T147 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2972478840 Jul 09 05:46:40 PM PDT 24 Jul 09 05:47:01 PM PDT 24 2955157659 ps
T164 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4010370943 Jul 09 05:46:54 PM PDT 24 Jul 09 05:47:00 PM PDT 24 317229496 ps
T163 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.952930837 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:52 PM PDT 24 636687330 ps
T1107 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3236050280 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:06 PM PDT 24 753198873 ps
T160 /workspace/coverage/cover_reg_top/43.kmac_intr_test.3715416108 Jul 09 05:47:03 PM PDT 24 Jul 09 05:47:06 PM PDT 24 15064870 ps
T1108 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.131312643 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:53 PM PDT 24 36646212 ps
T1109 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2130861298 Jul 09 05:46:48 PM PDT 24 Jul 09 05:46:51 PM PDT 24 262550153 ps
T1110 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1442928284 Jul 09 05:47:15 PM PDT 24 Jul 09 05:47:18 PM PDT 24 187271844 ps
T1111 /workspace/coverage/cover_reg_top/37.kmac_intr_test.2334101646 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:57 PM PDT 24 41854265 ps
T1112 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1099273110 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:11 PM PDT 24 40347040 ps
T1113 /workspace/coverage/cover_reg_top/6.kmac_intr_test.1291514933 Jul 09 05:46:48 PM PDT 24 Jul 09 05:46:50 PM PDT 24 22681022 ps
T1114 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3356121244 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:02 PM PDT 24 63982317 ps
T1115 /workspace/coverage/cover_reg_top/13.kmac_intr_test.3247188155 Jul 09 05:47:03 PM PDT 24 Jul 09 05:47:05 PM PDT 24 38736187 ps
T1116 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3681995184 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:03 PM PDT 24 347305649 ps
T1117 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.659510702 Jul 09 05:46:54 PM PDT 24 Jul 09 05:46:56 PM PDT 24 20066369 ps
T1118 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2561207140 Jul 09 05:46:49 PM PDT 24 Jul 09 05:46:52 PM PDT 24 22681645 ps
T1119 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.402888799 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:54 PM PDT 24 129200025 ps
T1120 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3979073124 Jul 09 05:46:40 PM PDT 24 Jul 09 05:46:42 PM PDT 24 81803344 ps
T103 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4088963567 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:10 PM PDT 24 248114626 ps
T1121 /workspace/coverage/cover_reg_top/31.kmac_intr_test.1139763927 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:09 PM PDT 24 20543286 ps
T1122 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2940344665 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:55 PM PDT 24 35934773 ps
T1123 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3310001658 Jul 09 05:46:38 PM PDT 24 Jul 09 05:46:39 PM PDT 24 132358084 ps
T1124 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3568993553 Jul 09 05:46:43 PM PDT 24 Jul 09 05:46:45 PM PDT 24 74263990 ps
T1125 /workspace/coverage/cover_reg_top/18.kmac_intr_test.564268213 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:00 PM PDT 24 30234568 ps
T1126 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1917669121 Jul 09 05:46:43 PM PDT 24 Jul 09 05:46:45 PM PDT 24 188527235 ps
T1127 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2200487687 Jul 09 05:46:57 PM PDT 24 Jul 09 05:46:59 PM PDT 24 29422326 ps
T1128 /workspace/coverage/cover_reg_top/3.kmac_intr_test.3308538893 Jul 09 05:46:39 PM PDT 24 Jul 09 05:46:41 PM PDT 24 39233384 ps
T171 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3070283650 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:04 PM PDT 24 427027164 ps
T1129 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.276215551 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:09 PM PDT 24 163112476 ps
T1130 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2323738837 Jul 09 05:46:42 PM PDT 24 Jul 09 05:46:46 PM PDT 24 135765145 ps
T1131 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1563437479 Jul 09 05:46:48 PM PDT 24 Jul 09 05:46:51 PM PDT 24 147685615 ps
T1132 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1756727073 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:50 PM PDT 24 374776984 ps
T1133 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1636972017 Jul 09 05:47:13 PM PDT 24 Jul 09 05:47:17 PM PDT 24 47760058 ps
T1134 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2571941864 Jul 09 05:46:45 PM PDT 24 Jul 09 05:46:48 PM PDT 24 380077822 ps
T1135 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2472325429 Jul 09 05:46:56 PM PDT 24 Jul 09 05:47:07 PM PDT 24 760402603 ps
T1136 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2890013864 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:54 PM PDT 24 51763191 ps
T1137 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.101704616 Jul 09 05:46:45 PM PDT 24 Jul 09 05:46:48 PM PDT 24 195089770 ps
T1138 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1891010934 Jul 09 05:46:44 PM PDT 24 Jul 09 05:47:04 PM PDT 24 1976993265 ps
T1139 /workspace/coverage/cover_reg_top/30.kmac_intr_test.3538061930 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:03 PM PDT 24 13412640 ps
T1140 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2095512387 Jul 09 05:47:03 PM PDT 24 Jul 09 05:47:06 PM PDT 24 40958423 ps
T1141 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.700383397 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:01 PM PDT 24 42418688 ps
T1142 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2582821132 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:49 PM PDT 24 116486773 ps
T1143 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.570747868 Jul 09 05:46:42 PM PDT 24 Jul 09 05:46:44 PM PDT 24 45370617 ps
T1144 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3072813946 Jul 09 05:46:41 PM PDT 24 Jul 09 05:46:43 PM PDT 24 44052645 ps
T1145 /workspace/coverage/cover_reg_top/41.kmac_intr_test.4093440124 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:02 PM PDT 24 146236028 ps
T165 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2330821493 Jul 09 05:46:49 PM PDT 24 Jul 09 05:46:55 PM PDT 24 197975169 ps
T1146 /workspace/coverage/cover_reg_top/20.kmac_intr_test.433210081 Jul 09 05:47:17 PM PDT 24 Jul 09 05:47:19 PM PDT 24 102987740 ps
T1147 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3254783140 Jul 09 05:47:06 PM PDT 24 Jul 09 05:47:11 PM PDT 24 58668529 ps
T1148 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1990168055 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:02 PM PDT 24 106163849 ps
T1149 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3037806742 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:08 PM PDT 24 155041048 ps
T1150 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2936551455 Jul 09 05:47:02 PM PDT 24 Jul 09 05:47:05 PM PDT 24 73955601 ps
T1151 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.882087267 Jul 09 05:47:07 PM PDT 24 Jul 09 05:47:13 PM PDT 24 23532695 ps
T1152 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.481727704 Jul 09 05:49:25 PM PDT 24 Jul 09 05:49:27 PM PDT 24 43882450 ps
T1153 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3198675306 Jul 09 05:46:53 PM PDT 24 Jul 09 05:46:55 PM PDT 24 16435586 ps
T1154 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2881375831 Jul 09 05:47:02 PM PDT 24 Jul 09 05:47:06 PM PDT 24 95643422 ps
T1155 /workspace/coverage/cover_reg_top/36.kmac_intr_test.3685240214 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:00 PM PDT 24 41796697 ps
T1156 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.568821555 Jul 09 05:46:42 PM PDT 24 Jul 09 05:46:44 PM PDT 24 15583525 ps
T1157 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1815066741 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:01 PM PDT 24 41587490 ps
T1158 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2377132707 Jul 09 05:46:42 PM PDT 24 Jul 09 05:46:44 PM PDT 24 36895218 ps
T1159 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.543578814 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:58 PM PDT 24 48454582 ps
T1160 /workspace/coverage/cover_reg_top/1.kmac_intr_test.4249137335 Jul 09 05:46:50 PM PDT 24 Jul 09 05:46:52 PM PDT 24 23682054 ps
T1161 /workspace/coverage/cover_reg_top/9.kmac_intr_test.1294754573 Jul 09 05:46:49 PM PDT 24 Jul 09 05:46:50 PM PDT 24 45726199 ps
T1162 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3679593729 Jul 09 05:46:46 PM PDT 24 Jul 09 05:46:51 PM PDT 24 816298636 ps
T1163 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4085066054 Jul 09 05:46:53 PM PDT 24 Jul 09 05:46:55 PM PDT 24 45123480 ps
T1164 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2759378466 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:10 PM PDT 24 659452568 ps
T1165 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3829807474 Jul 09 05:46:54 PM PDT 24 Jul 09 05:46:56 PM PDT 24 21564818 ps
T1166 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1500014663 Jul 09 05:46:39 PM PDT 24 Jul 09 05:46:41 PM PDT 24 116720666 ps
T1167 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3262267494 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:49 PM PDT 24 19123458 ps
T1168 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2323276590 Jul 09 05:46:41 PM PDT 24 Jul 09 05:46:45 PM PDT 24 205251146 ps
T1169 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3143265299 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:10 PM PDT 24 169868205 ps
T1170 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2122757897 Jul 09 05:47:21 PM PDT 24 Jul 09 05:47:22 PM PDT 24 47593832 ps
T1171 /workspace/coverage/cover_reg_top/40.kmac_intr_test.550673986 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:02 PM PDT 24 40613807 ps
T1172 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.422128447 Jul 09 05:46:45 PM PDT 24 Jul 09 05:46:47 PM PDT 24 77358178 ps
T1173 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1676829879 Jul 09 05:46:48 PM PDT 24 Jul 09 05:46:52 PM PDT 24 761876548 ps
T1174 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3557967821 Jul 09 05:46:45 PM PDT 24 Jul 09 05:46:46 PM PDT 24 51288802 ps
T1175 /workspace/coverage/cover_reg_top/21.kmac_intr_test.500323875 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:02 PM PDT 24 28335628 ps
T1176 /workspace/coverage/cover_reg_top/16.kmac_intr_test.1201708710 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:09 PM PDT 24 17628230 ps
T1177 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2398251292 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:55 PM PDT 24 28764694 ps
T1178 /workspace/coverage/cover_reg_top/5.kmac_intr_test.1848196354 Jul 09 05:47:02 PM PDT 24 Jul 09 05:47:04 PM PDT 24 42147073 ps
T166 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.961542314 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:12 PM PDT 24 98787248 ps
T1179 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3519336425 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:57 PM PDT 24 27475028 ps
T1180 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1927822850 Jul 09 05:46:44 PM PDT 24 Jul 09 05:46:47 PM PDT 24 93785644 ps
T1181 /workspace/coverage/cover_reg_top/19.kmac_intr_test.3014077469 Jul 09 05:47:08 PM PDT 24 Jul 09 05:47:12 PM PDT 24 181465529 ps
T1182 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4037815709 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:10 PM PDT 24 65414528 ps
T1183 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1373116654 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:10 PM PDT 24 238260065 ps
T1184 /workspace/coverage/cover_reg_top/46.kmac_intr_test.2284103552 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:57 PM PDT 24 177304294 ps
T130 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2757274642 Jul 09 05:46:42 PM PDT 24 Jul 09 05:46:44 PM PDT 24 60654479 ps
T1185 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2922195898 Jul 09 05:46:56 PM PDT 24 Jul 09 05:47:00 PM PDT 24 103132800 ps
T1186 /workspace/coverage/cover_reg_top/12.kmac_intr_test.624611591 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:54 PM PDT 24 25237489 ps
T1187 /workspace/coverage/cover_reg_top/49.kmac_intr_test.1275544132 Jul 09 05:47:06 PM PDT 24 Jul 09 05:47:10 PM PDT 24 23210927 ps
T1188 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3614956240 Jul 09 05:47:07 PM PDT 24 Jul 09 05:47:12 PM PDT 24 90478830 ps
T1189 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1297319693 Jul 09 05:46:50 PM PDT 24 Jul 09 05:46:52 PM PDT 24 53701748 ps
T1190 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2959546412 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:56 PM PDT 24 96926902 ps
T167 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2025823743 Jul 09 05:47:03 PM PDT 24 Jul 09 05:47:09 PM PDT 24 760049870 ps
T1191 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2310197272 Jul 09 05:46:38 PM PDT 24 Jul 09 05:46:41 PM PDT 24 39405110 ps
T1192 /workspace/coverage/cover_reg_top/45.kmac_intr_test.774989405 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:03 PM PDT 24 86740900 ps
T1193 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3477061032 Jul 09 05:46:46 PM PDT 24 Jul 09 05:46:49 PM PDT 24 109918854 ps
T1194 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3456597786 Jul 09 05:46:57 PM PDT 24 Jul 09 05:46:59 PM PDT 24 67119975 ps
T1195 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1149982234 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:03 PM PDT 24 32118049 ps
T1196 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.4148435586 Jul 09 05:46:53 PM PDT 24 Jul 09 05:46:58 PM PDT 24 2403483982 ps
T1197 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3875740749 Jul 09 05:46:47 PM PDT 24 Jul 09 05:46:50 PM PDT 24 166243557 ps
T1198 /workspace/coverage/cover_reg_top/27.kmac_intr_test.695052487 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:03 PM PDT 24 24391525 ps
T1199 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2827635031 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:55 PM PDT 24 92324709 ps
T1200 /workspace/coverage/cover_reg_top/38.kmac_intr_test.3022020756 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:04 PM PDT 24 16472576 ps
T1201 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.749083060 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:54 PM PDT 24 25021936 ps
T1202 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1057922887 Jul 09 05:47:11 PM PDT 24 Jul 09 05:47:15 PM PDT 24 49959844 ps
T1203 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.183829972 Jul 09 05:46:43 PM PDT 24 Jul 09 05:46:44 PM PDT 24 37485453 ps
T1204 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.932051740 Jul 09 05:46:50 PM PDT 24 Jul 09 05:46:59 PM PDT 24 661227342 ps
T1205 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2817559659 Jul 09 05:46:54 PM PDT 24 Jul 09 05:46:56 PM PDT 24 16163896 ps
T1206 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.278390257 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:04 PM PDT 24 517896883 ps
T1207 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.958905521 Jul 09 05:46:50 PM PDT 24 Jul 09 05:46:52 PM PDT 24 14051678 ps
T1208 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.142384578 Jul 09 05:46:52 PM PDT 24 Jul 09 05:46:55 PM PDT 24 53050914 ps
T1209 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.132562254 Jul 09 05:46:50 PM PDT 24 Jul 09 05:46:53 PM PDT 24 566474597 ps
T1210 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1493510363 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:57 PM PDT 24 1163289002 ps
T1211 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.870370666 Jul 09 05:46:56 PM PDT 24 Jul 09 05:47:00 PM PDT 24 107207881 ps
T1212 /workspace/coverage/cover_reg_top/29.kmac_intr_test.3629876188 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:08 PM PDT 24 37767315 ps
T1213 /workspace/coverage/cover_reg_top/7.kmac_intr_test.2061006880 Jul 09 05:46:43 PM PDT 24 Jul 09 05:46:45 PM PDT 24 14467384 ps
T131 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.460794101 Jul 09 05:46:53 PM PDT 24 Jul 09 05:46:55 PM PDT 24 54909045 ps
T1214 /workspace/coverage/cover_reg_top/47.kmac_intr_test.2251140862 Jul 09 05:47:04 PM PDT 24 Jul 09 05:47:08 PM PDT 24 45386535 ps
T1215 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2280543452 Jul 09 05:46:59 PM PDT 24 Jul 09 05:47:02 PM PDT 24 77495604 ps
T1216 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.100273163 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:03 PM PDT 24 164062170 ps
T1217 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1334574156 Jul 09 05:46:48 PM PDT 24 Jul 09 05:46:50 PM PDT 24 58837934 ps
T1218 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1515242822 Jul 09 05:46:46 PM PDT 24 Jul 09 05:46:48 PM PDT 24 382654607 ps
T1219 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3452410859 Jul 09 05:46:55 PM PDT 24 Jul 09 05:47:01 PM PDT 24 494191591 ps
T1220 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1039671195 Jul 09 05:47:05 PM PDT 24 Jul 09 05:47:09 PM PDT 24 40709849 ps
T1221 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4074032528 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:03 PM PDT 24 30054541 ps
T1222 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1524763284 Jul 09 05:46:45 PM PDT 24 Jul 09 05:46:47 PM PDT 24 25144666 ps
T1223 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2366388363 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:03 PM PDT 24 71038119 ps
T1224 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1149252307 Jul 09 05:47:07 PM PDT 24 Jul 09 05:47:12 PM PDT 24 14589187 ps
T1225 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2772578943 Jul 09 05:46:56 PM PDT 24 Jul 09 05:46:58 PM PDT 24 314547570 ps
T168 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1280367757 Jul 09 05:46:42 PM PDT 24 Jul 09 05:46:47 PM PDT 24 281023428 ps
T1226 /workspace/coverage/cover_reg_top/42.kmac_intr_test.2073246923 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:53 PM PDT 24 23659108 ps
T1227 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3146414019 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:04 PM PDT 24 21988477 ps
T1228 /workspace/coverage/cover_reg_top/32.kmac_intr_test.2995280655 Jul 09 05:47:09 PM PDT 24 Jul 09 05:47:13 PM PDT 24 21718043 ps
T1229 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2045638458 Jul 09 05:46:57 PM PDT 24 Jul 09 05:47:03 PM PDT 24 124563268 ps
T1230 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3957758724 Jul 09 05:47:15 PM PDT 24 Jul 09 05:47:19 PM PDT 24 239713114 ps
T1231 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.212225070 Jul 09 05:46:58 PM PDT 24 Jul 09 05:47:07 PM PDT 24 53472723 ps
T1232 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1837405269 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:54 PM PDT 24 259459658 ps
T1233 /workspace/coverage/cover_reg_top/23.kmac_intr_test.3870910184 Jul 09 05:47:00 PM PDT 24 Jul 09 05:47:03 PM PDT 24 41281718 ps
T1234 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1818927428 Jul 09 05:46:45 PM PDT 24 Jul 09 05:46:50 PM PDT 24 259220877 ps
T1235 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.981564240 Jul 09 05:46:41 PM PDT 24 Jul 09 05:46:43 PM PDT 24 70265948 ps
T1236 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3375634054 Jul 09 05:46:49 PM PDT 24 Jul 09 05:46:51 PM PDT 24 12929449 ps
T1237 /workspace/coverage/cover_reg_top/34.kmac_intr_test.3826120103 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:04 PM PDT 24 38589387 ps
T1238 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3903845542 Jul 09 05:47:01 PM PDT 24 Jul 09 05:47:04 PM PDT 24 85081085 ps
T1239 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3586486663 Jul 09 05:46:51 PM PDT 24 Jul 09 05:46:54 PM PDT 24 37154355 ps
T1240 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3216759011 Jul 09 05:46:55 PM PDT 24 Jul 09 05:46:59 PM PDT 24 423171269 ps

Test location /workspace/coverage/default/45.kmac_stress_all.1305456198
Short name T18
Test name
Test status
Simulation time 18705325210 ps
CPU time 1346 seconds
Started Jul 09 05:54:31 PM PDT 24
Finished Jul 09 06:16:58 PM PDT 24
Peak memory 386764 kb
Host smart-0ccc211a-f005-44e5-95be-3f8ba5abd61f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1305456198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1305456198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1019452750
Short name T109
Test name
Test status
Simulation time 264035037 ps
CPU time 4.94 seconds
Started Jul 09 05:47:03 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 219356 kb
Host smart-7650dbf4-7c11-406d-96dd-8638600a898c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019452750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1019
452750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.141517526
Short name T4
Test name
Test status
Simulation time 188129065 ps
CPU time 1.26 seconds
Started Jul 09 05:54:54 PM PDT 24
Finished Jul 09 05:54:56 PM PDT 24
Peak memory 215620 kb
Host smart-f8029b8c-543a-4e23-a9a8-cc781336485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141517526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.141517526 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.1416810854
Short name T27
Test name
Test status
Simulation time 30971505424 ps
CPU time 636.65 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 06:00:05 PM PDT 24
Peak memory 272956 kb
Host smart-90023a52-b87e-441a-8599-242ea1fcd669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416810854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.1416810854 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.1364602612
Short name T10
Test name
Test status
Simulation time 18869099871 ps
CPU time 69.72 seconds
Started Jul 09 05:49:51 PM PDT 24
Finished Jul 09 05:51:04 PM PDT 24
Peak memory 269728 kb
Host smart-47e55cd3-eff7-415a-af08-15fd51233eb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364602612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1364602612 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/23.kmac_error.3229951532
Short name T31
Test name
Test status
Simulation time 11607638259 ps
CPU time 264.83 seconds
Started Jul 09 05:50:42 PM PDT 24
Finished Jul 09 05:55:07 PM PDT 24
Peak memory 249512 kb
Host smart-f1550dee-4d4d-439d-9537-a46b1ff99b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229951532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3229951532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.726906679
Short name T22
Test name
Test status
Simulation time 182569225 ps
CPU time 1.63 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 05:50:18 PM PDT 24
Peak memory 215584 kb
Host smart-0e6c0f64-6e24-4029-b0cc-9282ab71ea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726906679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.726906679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3727794939
Short name T95
Test name
Test status
Simulation time 388874035 ps
CPU time 2.65 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 215996 kb
Host smart-d4350827-1699-451b-918d-ef92859b586f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727794939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.3727794939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.1770461719
Short name T416
Test name
Test status
Simulation time 516264364 ps
CPU time 1.27 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:49:51 PM PDT 24
Peak memory 215480 kb
Host smart-6867d7db-28e5-4104-9009-d694d9aa951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770461719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1770461719 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.3699994386
Short name T55
Test name
Test status
Simulation time 5399433190 ps
CPU time 14.36 seconds
Started Jul 09 05:52:02 PM PDT 24
Finished Jul 09 05:52:17 PM PDT 24
Peak memory 223912 kb
Host smart-717acf5d-4aa8-4ac5-b973-893a4afe0770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699994386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3699994386 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.375586956
Short name T157
Test name
Test status
Simulation time 152122279 ps
CPU time 0.75 seconds
Started Jul 09 05:46:44 PM PDT 24
Finished Jul 09 05:46:46 PM PDT 24
Peak memory 206992 kb
Host smart-2c1bccd2-b58c-47b8-b82a-bd314b36810d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375586956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.375586956 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.779977411
Short name T5
Test name
Test status
Simulation time 41881905 ps
CPU time 1.15 seconds
Started Jul 09 05:51:16 PM PDT 24
Finished Jul 09 05:51:18 PM PDT 24
Peak memory 215600 kb
Host smart-d5df481b-67d1-40d4-8485-0106c2c84639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779977411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.779977411 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.3018607687
Short name T14
Test name
Test status
Simulation time 1304198231860 ps
CPU time 3898.59 seconds
Started Jul 09 05:52:20 PM PDT 24
Finished Jul 09 06:57:20 PM PDT 24
Peak memory 549212 kb
Host smart-700a3c4d-62b2-4e5f-9471-fb03c867da41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3018607687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.3018607687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2649116950
Short name T49
Test name
Test status
Simulation time 31130317 ps
CPU time 0.91 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:50:08 PM PDT 24
Peak memory 205348 kb
Host smart-8909facb-37a9-4171-b7d5-ce8498ab64e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649116950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2649116950 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3443235719
Short name T129
Test name
Test status
Simulation time 20781336 ps
CPU time 1.32 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 215544 kb
Host smart-d685c222-2ee1-4a23-ac85-6e982329b4a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443235719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.3443235719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.2957929055
Short name T51
Test name
Test status
Simulation time 114728848653 ps
CPU time 1399.41 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 06:13:11 PM PDT 24
Peak memory 338968 kb
Host smart-2a2b34bc-9a17-4475-825e-0279110e5ab5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957929055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.2957929055 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.1461667378
Short name T37
Test name
Test status
Simulation time 228212628 ps
CPU time 1.33 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:49:52 PM PDT 24
Peak memory 215596 kb
Host smart-536740a6-092b-4a95-8dc3-824f5e25bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461667378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1461667378 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.4087730361
Short name T158
Test name
Test status
Simulation time 21399441 ps
CPU time 0.77 seconds
Started Jul 09 05:46:50 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 207072 kb
Host smart-d9f647e2-4e6a-48b0-99a4-51e4fe182193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087730361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.4087730361 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2935733684
Short name T100
Test name
Test status
Simulation time 374638413 ps
CPU time 2.81 seconds
Started Jul 09 05:47:09 PM PDT 24
Finished Jul 09 05:47:15 PM PDT 24
Peak memory 215940 kb
Host smart-18bec84a-df63-41af-a068-747b282ab77c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935733684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2935733684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.kmac_stress_all.221036722
Short name T25
Test name
Test status
Simulation time 140004298820 ps
CPU time 884.97 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 06:06:16 PM PDT 24
Peak memory 334404 kb
Host smart-5f9dcada-fa60-4150-84d3-2e04e3ca226c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=221036722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.221036722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2025823743
Short name T167
Test name
Test status
Simulation time 760049870 ps
CPU time 4.68 seconds
Started Jul 09 05:47:03 PM PDT 24
Finished Jul 09 05:47:09 PM PDT 24
Peak memory 215672 kb
Host smart-bc75713a-d051-43d8-a5b7-7b27ffd1a43d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025823743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2025
823743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.751220662
Short name T97
Test name
Test status
Simulation time 29644502 ps
CPU time 1.5 seconds
Started Jul 09 05:47:03 PM PDT 24
Finished Jul 09 05:47:06 PM PDT 24
Peak memory 215684 kb
Host smart-80b9dbb6-9816-4822-96ae-db1e60056489
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751220662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac
_shadow_reg_errors_with_csr_rw.751220662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.952930837
Short name T163
Test name
Test status
Simulation time 636687330 ps
CPU time 4.21 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 215648 kb
Host smart-4ee39ca9-58bd-4af0-83e2-9d2a3e87279c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952930837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.95293
0837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.2651318295
Short name T149
Test name
Test status
Simulation time 51462308935 ps
CPU time 4011.01 seconds
Started Jul 09 05:49:26 PM PDT 24
Finished Jul 09 06:56:18 PM PDT 24
Peak memory 662728 kb
Host smart-9c7239c4-5731-467b-be0c-e9854a5d55b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2651318295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2651318295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_stress_all.4183815752
Short name T53
Test name
Test status
Simulation time 37176806163 ps
CPU time 992.87 seconds
Started Jul 09 05:54:54 PM PDT 24
Finished Jul 09 06:11:28 PM PDT 24
Peak memory 367052 kb
Host smart-44f449ad-b510-44c7-b566-5e0deae6f834
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4183815752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.4183815752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_error.1636890779
Short name T306
Test name
Test status
Simulation time 2306750113 ps
CPU time 176.96 seconds
Started Jul 09 05:55:10 PM PDT 24
Finished Jul 09 05:58:07 PM PDT 24
Peak memory 248680 kb
Host smart-2dcb5bde-e7d1-4111-9e72-48ff1d794a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636890779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1636890779 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3574566306
Short name T150
Test name
Test status
Simulation time 65382468131 ps
CPU time 1760.92 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 06:20:08 PM PDT 24
Peak memory 393904 kb
Host smart-abc645c0-2331-4cba-b1a9-e167aa015b31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3574566306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3574566306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.161157720
Short name T151
Test name
Test status
Simulation time 179214723997 ps
CPU time 4609.99 seconds
Started Jul 09 05:51:10 PM PDT 24
Finished Jul 09 07:08:01 PM PDT 24
Peak memory 652632 kb
Host smart-9ce085ea-0a50-479c-9291-88c1dece110c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=161157720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.161157720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.1523763703
Short name T646
Test name
Test status
Simulation time 3683908217 ps
CPU time 32.01 seconds
Started Jul 09 05:49:17 PM PDT 24
Finished Jul 09 05:49:49 PM PDT 24
Peak memory 216780 kb
Host smart-97077919-b90f-4e5d-aa12-2a74858fb480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523763703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1523763703 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/12.kmac_burst_write.4028750239
Short name T41
Test name
Test status
Simulation time 6156384149 ps
CPU time 177.39 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 05:52:54 PM PDT 24
Peak memory 225212 kb
Host smart-16fda3d4-556c-4a87-a68c-ab8a277fb242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028750239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.4028750239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2668793015
Short name T1106
Test name
Test status
Simulation time 1296236994 ps
CPU time 9.27 seconds
Started Jul 09 05:46:56 PM PDT 24
Finished Jul 09 05:47:09 PM PDT 24
Peak memory 215592 kb
Host smart-b63965c8-5b83-4caa-989c-dc4f981500cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668793015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2668793
015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2472325429
Short name T1135
Test name
Test status
Simulation time 760402603 ps
CPU time 10.76 seconds
Started Jul 09 05:46:56 PM PDT 24
Finished Jul 09 05:47:07 PM PDT 24
Peak memory 207440 kb
Host smart-de3de34f-d8ac-4d16-a9dd-c047dc8a902a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472325429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2472325
429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1915791982
Short name T145
Test name
Test status
Simulation time 122487565 ps
CPU time 1.01 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 207168 kb
Host smart-84648a5c-5e25-4c26-aed6-fd6ff36526de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915791982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1915791
982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.981564240
Short name T1235
Test name
Test status
Simulation time 70265948 ps
CPU time 2.4 seconds
Started Jul 09 05:46:41 PM PDT 24
Finished Jul 09 05:46:43 PM PDT 24
Peak memory 223784 kb
Host smart-df3a9f65-54ce-46fb-9d2d-e85582a032e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981564240 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.981564240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.570747868
Short name T1143
Test name
Test status
Simulation time 45370617 ps
CPU time 0.91 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 207156 kb
Host smart-acedf680-42c5-4985-8d0a-cc006a25b32b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570747868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.570747868 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.460794101
Short name T131
Test name
Test status
Simulation time 54909045 ps
CPU time 1.1 seconds
Started Jul 09 05:46:53 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 215472 kb
Host smart-81099117-4253-459a-aed1-6c4f2bb465a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460794101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial
_access.460794101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.131312643
Short name T1108
Test name
Test status
Simulation time 36646212 ps
CPU time 0.74 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:53 PM PDT 24
Peak memory 207180 kb
Host smart-f4d2691f-f851-47b6-8d3a-21036b06dec1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131312643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.131312643 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3072813946
Short name T1144
Test name
Test status
Simulation time 44052645 ps
CPU time 1.44 seconds
Started Jul 09 05:46:41 PM PDT 24
Finished Jul 09 05:46:43 PM PDT 24
Peak memory 215604 kb
Host smart-1a1e8886-7d0d-4d7f-a75d-1d42cfd6d779
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072813946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3072813946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1917669121
Short name T1126
Test name
Test status
Simulation time 188527235 ps
CPU time 1.09 seconds
Started Jul 09 05:46:43 PM PDT 24
Finished Jul 09 05:46:45 PM PDT 24
Peak memory 215972 kb
Host smart-50d459ff-7021-46fa-bfcc-00034cedd790
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917669121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.1917669121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2323276590
Short name T1168
Test name
Test status
Simulation time 205251146 ps
CPU time 2.89 seconds
Started Jul 09 05:46:41 PM PDT 24
Finished Jul 09 05:46:45 PM PDT 24
Peak memory 216048 kb
Host smart-46179b37-d23c-4356-b01b-174348ab6da1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323276590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2323276590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2561207140
Short name T1118
Test name
Test status
Simulation time 22681645 ps
CPU time 1.44 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 215876 kb
Host smart-b4f79b33-5ee6-4edc-907e-e43a13becf1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561207140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2561207140 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1817719378
Short name T111
Test name
Test status
Simulation time 127978867 ps
CPU time 2.73 seconds
Started Jul 09 05:46:44 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 215536 kb
Host smart-f67a9d43-d1fe-4512-9f6e-c0bffd9f8388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817719378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.18177
19378 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1493510363
Short name T1210
Test name
Test status
Simulation time 1163289002 ps
CPU time 5.31 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:57 PM PDT 24
Peak memory 207388 kb
Host smart-9d804da4-4d6f-4e73-9e19-00c4b873af5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493510363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1493510
363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.640456807
Short name T139
Test name
Test status
Simulation time 5007794610 ps
CPU time 18.8 seconds
Started Jul 09 05:46:46 PM PDT 24
Finished Jul 09 05:47:06 PM PDT 24
Peak memory 207440 kb
Host smart-06dec751-3823-48a5-80ae-500cc4d557d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640456807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.64045680
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2398251292
Short name T1177
Test name
Test status
Simulation time 28764694 ps
CPU time 1.04 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 207440 kb
Host smart-21377f9f-718a-4958-b029-ef250d213301
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398251292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2398251
292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.132562254
Short name T1209
Test name
Test status
Simulation time 566474597 ps
CPU time 1.57 seconds
Started Jul 09 05:46:50 PM PDT 24
Finished Jul 09 05:46:53 PM PDT 24
Peak memory 215612 kb
Host smart-ce8084a9-b366-4fbe-ad57-f5c430bf40c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132562254 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.132562254 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4275590409
Short name T141
Test name
Test status
Simulation time 102459922 ps
CPU time 1.06 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:48 PM PDT 24
Peak memory 207328 kb
Host smart-bf55d6a6-c842-4bcf-98e7-a6d92c9367e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275590409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4275590409 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.4249137335
Short name T1160
Test name
Test status
Simulation time 23682054 ps
CPU time 0.74 seconds
Started Jul 09 05:46:50 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 207056 kb
Host smart-99183b8f-ac22-4931-9483-6ba436258eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249137335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.4249137335 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2757274642
Short name T130
Test name
Test status
Simulation time 60654479 ps
CPU time 1.35 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 215484 kb
Host smart-2e299365-4d56-4c28-a61e-e3c4ddb86ce4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757274642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.2757274642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3310001658
Short name T1123
Test name
Test status
Simulation time 132358084 ps
CPU time 0.76 seconds
Started Jul 09 05:46:38 PM PDT 24
Finished Jul 09 05:46:39 PM PDT 24
Peak memory 207208 kb
Host smart-2643a5ae-688b-4c52-a5c9-6c6631632cb2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310001658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3310001658
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3456597786
Short name T1194
Test name
Test status
Simulation time 67119975 ps
CPU time 1.53 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 215776 kb
Host smart-3b2f7e99-2f7a-4b5d-9145-eb036aacd247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456597786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.3456597786 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1500014663
Short name T1166
Test name
Test status
Simulation time 116720666 ps
CPU time 1.31 seconds
Started Jul 09 05:46:39 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 215916 kb
Host smart-ffd7f17e-8fd2-4b59-8e8f-2245d06fbec2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500014663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.1500014663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.578001294
Short name T94
Test name
Test status
Simulation time 47409091 ps
CPU time 2.31 seconds
Started Jul 09 05:48:51 PM PDT 24
Finished Jul 09 05:48:55 PM PDT 24
Peak memory 224100 kb
Host smart-c1758aff-965b-4162-b6a4-f52a59230f56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578001294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_
shadow_reg_errors_with_csr_rw.578001294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1524763284
Short name T1222
Test name
Test status
Simulation time 25144666 ps
CPU time 1.5 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 215544 kb
Host smart-bc389224-bd4e-4888-9646-f23965e5eb55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524763284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1524763284 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2323738837
Short name T1130
Test name
Test status
Simulation time 135765145 ps
CPU time 3.89 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:46 PM PDT 24
Peak memory 215624 kb
Host smart-07425a0f-526d-441e-aacc-bc391d1f1a32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323738837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.23237
38837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2280543452
Short name T1215
Test name
Test status
Simulation time 77495604 ps
CPU time 1.61 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 215596 kb
Host smart-6483206e-4e1e-451c-bfcf-92099cc99791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280543452 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2280543452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1149982234
Short name T1195
Test name
Test status
Simulation time 32118049 ps
CPU time 1.05 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 207464 kb
Host smart-25e0b766-76ac-46fd-8ac8-13340987b60b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149982234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1149982234 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.142384578
Short name T1208
Test name
Test status
Simulation time 53050914 ps
CPU time 1.42 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 215768 kb
Host smart-1c885925-5566-4d38-9b0a-f69070c11b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142384578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr
_outstanding.142384578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3082151962
Short name T102
Test name
Test status
Simulation time 28544669 ps
CPU time 1.07 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 215904 kb
Host smart-84c7ddfe-7606-4078-96a3-b78491ebcf16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082151962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3082151962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2599517942
Short name T1092
Test name
Test status
Simulation time 116249818 ps
CPU time 1.97 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 215516 kb
Host smart-25582961-c2de-4c0a-9865-92d8de856cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599517942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2599517942 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1373116654
Short name T1183
Test name
Test status
Simulation time 238260065 ps
CPU time 2.28 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 215596 kb
Host smart-7e33952b-8f69-4b6d-9fb6-fb20d84c8e85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373116654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1373
116654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1636972017
Short name T1133
Test name
Test status
Simulation time 47760058 ps
CPU time 1.41 seconds
Started Jul 09 05:47:13 PM PDT 24
Finished Jul 09 05:47:17 PM PDT 24
Peak memory 215584 kb
Host smart-581855e9-a29a-4b09-9422-07e992064375
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636972017 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1636972017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.870370666
Short name T1211
Test name
Test status
Simulation time 107207881 ps
CPU time 1.16 seconds
Started Jul 09 05:46:56 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 207388 kb
Host smart-c58e78d5-8ad6-405d-83e3-8dd228d8ffba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870370666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.870370666 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.2121449527
Short name T112
Test name
Test status
Simulation time 49651145 ps
CPU time 0.72 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 207004 kb
Host smart-584d056d-f4ac-42f4-b039-58d01b00d520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121449527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2121449527 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3143265299
Short name T1169
Test name
Test status
Simulation time 169868205 ps
CPU time 2.29 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 215812 kb
Host smart-f9f21538-e909-4395-a22a-97316cd73e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143265299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3143265299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4074032528
Short name T1221
Test name
Test status
Simulation time 30054541 ps
CPU time 1.02 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 215672 kb
Host smart-84adef85-aeb2-4cac-978e-9b43aeaa6c48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074032528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.4074032528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.100273163
Short name T1216
Test name
Test status
Simulation time 164062170 ps
CPU time 2.09 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 215944 kb
Host smart-6b631ac2-eebd-4778-b633-bd3f5fc8a021
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100273163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.100273163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.882087267
Short name T1151
Test name
Test status
Simulation time 23532695 ps
CPU time 1.59 seconds
Started Jul 09 05:47:07 PM PDT 24
Finished Jul 09 05:47:13 PM PDT 24
Peak memory 215820 kb
Host smart-9ec567c5-42fd-4091-ad24-8f4383c5c497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882087267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.882087267 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2231920218
Short name T1086
Test name
Test status
Simulation time 103412427 ps
CPU time 1.42 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 222932 kb
Host smart-d1c10bc2-f41b-4f65-b774-d6f94069e9b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231920218 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2231920218 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.4267361626
Short name T172
Test name
Test status
Simulation time 414986869 ps
CPU time 1.09 seconds
Started Jul 09 05:47:07 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 215512 kb
Host smart-f1428119-bbe4-491e-8f46-299dadb499bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267361626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.4267361626 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.624611591
Short name T1186
Test name
Test status
Simulation time 25237489 ps
CPU time 0.8 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 207084 kb
Host smart-f8bd992f-c64c-4414-b981-2fd34bd80512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624611591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.624611591 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.456706299
Short name T1104
Test name
Test status
Simulation time 723115740 ps
CPU time 2.35 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 215660 kb
Host smart-9c8a9499-ab20-4d5d-8ca2-a93ef7c1b5ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456706299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr
_outstanding.456706299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2249662817
Short name T1102
Test name
Test status
Simulation time 35241956 ps
CPU time 1.08 seconds
Started Jul 09 05:47:07 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 215896 kb
Host smart-e25b6bdb-04de-46f7-8652-fbd0529c3751
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249662817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2249662817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.278390257
Short name T1206
Test name
Test status
Simulation time 517896883 ps
CPU time 2.94 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 215904 kb
Host smart-9aa8a3b0-1cdc-417f-9939-c5d2f4b266f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278390257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac
_shadow_reg_errors_with_csr_rw.278390257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2759378466
Short name T1164
Test name
Test status
Simulation time 659452568 ps
CPU time 2.68 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 215592 kb
Host smart-83f42280-fce4-478f-97c9-f8fb22e72551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759378466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2759378466 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3418823383
Short name T146
Test name
Test status
Simulation time 459623181 ps
CPU time 2.98 seconds
Started Jul 09 05:46:56 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 215724 kb
Host smart-7b90e07d-d406-4e93-9465-1ee0ec187df5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418823383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3418
823383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2959546412
Short name T1190
Test name
Test status
Simulation time 96926902 ps
CPU time 2.39 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 223788 kb
Host smart-8c8aec1f-900c-4304-af47-255d98e29009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959546412 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2959546412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1719575767
Short name T1091
Test name
Test status
Simulation time 63467123 ps
CPU time 0.87 seconds
Started Jul 09 05:47:09 PM PDT 24
Finished Jul 09 05:47:13 PM PDT 24
Peak memory 207244 kb
Host smart-d856208a-77a3-4b62-bcf1-4b89fd3c810b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719575767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1719575767 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.3247188155
Short name T1115
Test name
Test status
Simulation time 38736187 ps
CPU time 0.78 seconds
Started Jul 09 05:47:03 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 207060 kb
Host smart-aa9aed63-e564-4b62-8478-e4bf4460a712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247188155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3247188155 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3968930969
Short name T1085
Test name
Test status
Simulation time 94854670 ps
CPU time 2.57 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 215864 kb
Host smart-ef4c35b7-57f4-4063-aee9-c03e206799b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968930969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3968930969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1442928284
Short name T1110
Test name
Test status
Simulation time 187271844 ps
CPU time 0.93 seconds
Started Jul 09 05:47:15 PM PDT 24
Finished Jul 09 05:47:18 PM PDT 24
Peak memory 215748 kb
Host smart-75863500-c2d5-4e5a-b935-17ea5b8274be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442928284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1442928284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.212225070
Short name T1231
Test name
Test status
Simulation time 53472723 ps
CPU time 1.64 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:07 PM PDT 24
Peak memory 207384 kb
Host smart-d6371448-d2a5-49aa-ad3a-61c582776465
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212225070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac
_shadow_reg_errors_with_csr_rw.212225070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1837405269
Short name T1232
Test name
Test status
Simulation time 259459658 ps
CPU time 2.11 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 215596 kb
Host smart-e6a5e8c7-3ece-43cc-8049-c1a1ee9cc913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837405269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1837405269 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2330821493
Short name T165
Test name
Test status
Simulation time 197975169 ps
CPU time 4.35 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 207416 kb
Host smart-8383c396-ccc3-4940-a9a7-7c2523ed33ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330821493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2330
821493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3957758724
Short name T1230
Test name
Test status
Simulation time 239713114 ps
CPU time 2.35 seconds
Started Jul 09 05:47:15 PM PDT 24
Finished Jul 09 05:47:19 PM PDT 24
Peak memory 223792 kb
Host smart-1c9c0f8c-65af-4728-b604-ebd47adad608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957758724 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3957758724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3146414019
Short name T1227
Test name
Test status
Simulation time 21988477 ps
CPU time 0.92 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 207224 kb
Host smart-e6b5b490-b9a9-4bf3-9865-c5c691ed7ce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146414019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3146414019 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3232302063
Short name T159
Test name
Test status
Simulation time 42125614 ps
CPU time 0.76 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 207000 kb
Host smart-9eeabdd0-914d-4838-9240-3c61f3f37e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232302063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3232302063 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3681995184
Short name T1116
Test name
Test status
Simulation time 347305649 ps
CPU time 2.48 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 215904 kb
Host smart-5d68d02d-f21e-46f4-8c59-add074febd76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681995184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.3681995184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1077062121
Short name T108
Test name
Test status
Simulation time 39479689 ps
CPU time 0.79 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 207244 kb
Host smart-20375018-0d0e-4d54-8f7c-d402fe256e86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077062121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.1077062121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3998037572
Short name T1097
Test name
Test status
Simulation time 80792503 ps
CPU time 1.84 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:11 PM PDT 24
Peak memory 215972 kb
Host smart-b13e24ad-ffa8-4b4a-a2b5-1c2d630c7cd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998037572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.3998037572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.617162706
Short name T1087
Test name
Test status
Simulation time 135411403 ps
CPU time 2.82 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 215616 kb
Host smart-baa68ec5-e450-4966-9838-2adf57efc0f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617162706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.617162706 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2366388363
Short name T1223
Test name
Test status
Simulation time 71038119 ps
CPU time 1.58 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 215604 kb
Host smart-cb74c1c1-748f-4a96-91f4-b331892af4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366388363 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2366388363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1990168055
Short name T1148
Test name
Test status
Simulation time 106163849 ps
CPU time 1.1 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 207344 kb
Host smart-c6490ae1-6439-4d51-803a-85813d710bc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990168055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1990168055 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1437732400
Short name T113
Test name
Test status
Simulation time 15555184 ps
CPU time 0.72 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 207032 kb
Host smart-efbcaa08-8fa0-4a6c-aa77-d0004bf75784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437732400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1437732400 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.99074991
Short name T1101
Test name
Test status
Simulation time 96922656 ps
CPU time 2.37 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 215412 kb
Host smart-a8a49932-0e3e-4ca4-8c09-2cdd1d1d8874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99074991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_
outstanding.99074991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.289457291
Short name T93
Test name
Test status
Simulation time 89087135 ps
CPU time 1.06 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 207776 kb
Host smart-7252682f-7699-42ad-a05a-e0c6e029defe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289457291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_
errors.289457291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.668628880
Short name T99
Test name
Test status
Simulation time 73300409 ps
CPU time 2.48 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 215964 kb
Host smart-1761a141-17bf-4ccd-90be-2f8744c57bc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668628880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac
_shadow_reg_errors_with_csr_rw.668628880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2095512387
Short name T1140
Test name
Test status
Simulation time 40958423 ps
CPU time 1.54 seconds
Started Jul 09 05:47:03 PM PDT 24
Finished Jul 09 05:47:06 PM PDT 24
Peak memory 218928 kb
Host smart-c8c64b5d-66a8-4cd2-84bb-cacee513fb82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095512387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2095512387 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3172433426
Short name T162
Test name
Test status
Simulation time 382663091 ps
CPU time 4.32 seconds
Started Jul 09 05:47:03 PM PDT 24
Finished Jul 09 05:47:09 PM PDT 24
Peak memory 215420 kb
Host smart-8cf14a23-5fc1-4b95-b0d0-0744e8598094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172433426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3172
433426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.416670208
Short name T120
Test name
Test status
Simulation time 37721349 ps
CPU time 2.42 seconds
Started Jul 09 05:47:02 PM PDT 24
Finished Jul 09 05:47:07 PM PDT 24
Peak memory 217140 kb
Host smart-4628d011-a511-45aa-b9cc-0832a27a9c92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416670208 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.416670208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.29079665
Short name T140
Test name
Test status
Simulation time 227546103 ps
CPU time 1.06 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 207452 kb
Host smart-8536704c-d0c8-423b-8606-3bcb83909706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29079665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.29079665 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.1201708710
Short name T1176
Test name
Test status
Simulation time 17628230 ps
CPU time 0.81 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:09 PM PDT 24
Peak memory 207048 kb
Host smart-29d0917e-7342-4c8e-bf9d-0d6c6a8b0d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201708710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1201708710 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3875740749
Short name T1197
Test name
Test status
Simulation time 166243557 ps
CPU time 1.41 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 215524 kb
Host smart-35c2ab54-af3f-4729-8a0f-f4eef510c7cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875740749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.3875740749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1590511344
Short name T96
Test name
Test status
Simulation time 33581400 ps
CPU time 1.34 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 215800 kb
Host smart-5ea7a9bd-3ff8-4743-a948-224daeb0b191
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590511344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.1590511344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2881375831
Short name T1154
Test name
Test status
Simulation time 95643422 ps
CPU time 2.46 seconds
Started Jul 09 05:47:02 PM PDT 24
Finished Jul 09 05:47:06 PM PDT 24
Peak memory 215752 kb
Host smart-725c9a19-6d8e-4666-883d-d4b8d66d9fef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881375831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.2881375831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.886767909
Short name T118
Test name
Test status
Simulation time 60524771 ps
CPU time 2.13 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 218544 kb
Host smart-d8372f88-95ef-4527-a6a2-5ce92580fd33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886767909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.886767909 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3236050280
Short name T1107
Test name
Test status
Simulation time 753198873 ps
CPU time 2.73 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:06 PM PDT 24
Peak memory 207220 kb
Host smart-cdd9d074-202c-45fc-b8bb-f98c3bef6d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236050280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3236
050280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2718148523
Short name T137
Test name
Test status
Simulation time 123488150 ps
CPU time 1.49 seconds
Started Jul 09 05:46:56 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 215624 kb
Host smart-97eedcb7-3c99-4f60-898f-55c5bb84d198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718148523 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2718148523 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1359622741
Short name T1103
Test name
Test status
Simulation time 14842077 ps
CPU time 0.93 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:07 PM PDT 24
Peak memory 207248 kb
Host smart-f267c9d4-26e1-48ad-bb10-82269cd12962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359622741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1359622741 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3614956240
Short name T1188
Test name
Test status
Simulation time 90478830 ps
CPU time 0.74 seconds
Started Jul 09 05:47:07 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 207068 kb
Host smart-e52c49ec-3414-4ed8-bcba-b20126823a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614956240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3614956240 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4037815709
Short name T1182
Test name
Test status
Simulation time 65414528 ps
CPU time 1.31 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 215412 kb
Host smart-c56b633a-f5b1-4dd9-afca-8203f8166e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037815709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.4037815709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3903845542
Short name T1238
Test name
Test status
Simulation time 85081085 ps
CPU time 1.03 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 215748 kb
Host smart-59e9fa87-29eb-4b5f-b961-61abda679276
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903845542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.3903845542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3487690813
Short name T1098
Test name
Test status
Simulation time 887459244 ps
CPU time 3.68 seconds
Started Jul 09 05:46:53 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 223740 kb
Host smart-a278e8ab-7d09-4f48-984c-981da23bd934
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487690813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3487690813 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3070283650
Short name T171
Test name
Test status
Simulation time 427027164 ps
CPU time 2.7 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 215596 kb
Host smart-fc3e9558-a7d7-482a-82a0-3aee3afafe3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070283650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3070
283650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3037806742
Short name T1149
Test name
Test status
Simulation time 155041048 ps
CPU time 1.52 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:08 PM PDT 24
Peak memory 215596 kb
Host smart-3e16c97c-e2fc-4c8f-9f67-b980e66a8bac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037806742 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3037806742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2200487687
Short name T1127
Test name
Test status
Simulation time 29422326 ps
CPU time 1.09 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 207348 kb
Host smart-76978bac-f4f0-483f-9921-373ee00822e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200487687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2200487687 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.564268213
Short name T1125
Test name
Test status
Simulation time 30234568 ps
CPU time 0.75 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 206896 kb
Host smart-45254b0b-1d98-4ea1-82e5-2f0e07bcb1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564268213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.564268213 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1756727073
Short name T1132
Test name
Test status
Simulation time 374776984 ps
CPU time 2.35 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 216048 kb
Host smart-f6cd2dfa-8f9d-4147-b007-7d654e90bd25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756727073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.1756727073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3254783140
Short name T1147
Test name
Test status
Simulation time 58668529 ps
CPU time 0.91 seconds
Started Jul 09 05:47:06 PM PDT 24
Finished Jul 09 05:47:11 PM PDT 24
Peak memory 207136 kb
Host smart-fc7fb1c3-41f1-4867-a68e-a60b1f54bfe9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254783140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.3254783140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1815066741
Short name T1157
Test name
Test status
Simulation time 41587490 ps
CPU time 1.47 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:01 PM PDT 24
Peak memory 215448 kb
Host smart-9de4b6b6-97e2-4df1-ac38-0d2bcab49f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815066741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1815066741 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2215058832
Short name T117
Test name
Test status
Simulation time 268796133 ps
CPU time 2.32 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 223780 kb
Host smart-910cabe3-c228-4707-87f8-b7f2325b524b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215058832 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2215058832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3743143024
Short name T144
Test name
Test status
Simulation time 111359137 ps
CPU time 1.1 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 207452 kb
Host smart-758cbbe0-8284-49c1-87e7-a38053abc73a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743143024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3743143024 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.3014077469
Short name T1181
Test name
Test status
Simulation time 181465529 ps
CPU time 0.82 seconds
Started Jul 09 05:47:08 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 207072 kb
Host smart-376ceb93-baad-43b9-ade7-571bfc3804da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014077469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3014077469 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1099273110
Short name T1112
Test name
Test status
Simulation time 40347040 ps
CPU time 2.16 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:11 PM PDT 24
Peak memory 215636 kb
Host smart-2ad1d4e7-da17-4578-ba7f-d56f9613c3c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099273110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.1099273110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1045418020
Short name T98
Test name
Test status
Simulation time 65808460 ps
CPU time 1.34 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 215912 kb
Host smart-56bd0430-0382-4123-ad15-0a88ed19cc22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045418020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.1045418020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2922195898
Short name T1185
Test name
Test status
Simulation time 103132800 ps
CPU time 2.61 seconds
Started Jul 09 05:46:56 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 223532 kb
Host smart-5f04a8b7-32dc-4618-9091-31563560cd7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922195898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.2922195898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.4148435586
Short name T1196
Test name
Test status
Simulation time 2403483982 ps
CPU time 3.64 seconds
Started Jul 09 05:46:53 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 215452 kb
Host smart-a5cdd2eb-8756-4d38-84ac-46ffacb96682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148435586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4148435586 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1548232126
Short name T110
Test name
Test status
Simulation time 337787465 ps
CPU time 2.39 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 215568 kb
Host smart-fd5676ca-b07b-4d7e-9171-59ef96d61cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548232126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1548
232126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1818927428
Short name T1234
Test name
Test status
Simulation time 259220877 ps
CPU time 5.04 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 207312 kb
Host smart-eae5ee55-b84e-4e34-8fe7-ebaf81ec2d35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818927428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1818927
428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1891010934
Short name T1138
Test name
Test status
Simulation time 1976993265 ps
CPU time 18.94 seconds
Started Jul 09 05:46:44 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 207448 kb
Host smart-f3a8d91a-9ef5-4981-a3e3-b358b4f99914
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891010934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1891010
934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3557967821
Short name T1174
Test name
Test status
Simulation time 51288802 ps
CPU time 1.07 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:46 PM PDT 24
Peak memory 207436 kb
Host smart-a523c529-f67f-47db-82d2-d0abc4862d83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557967821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3557967
821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3512772382
Short name T116
Test name
Test status
Simulation time 172678085 ps
CPU time 1.55 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 215632 kb
Host smart-a9943707-b76d-41d3-92fe-02498a2fca7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512772382 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3512772382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.4182808034
Short name T134
Test name
Test status
Simulation time 96917942 ps
CPU time 1.13 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:08 PM PDT 24
Peak memory 215540 kb
Host smart-666c2382-c1d5-43f8-92b0-e74f42dc676e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182808034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.4182808034 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2817559659
Short name T1205
Test name
Test status
Simulation time 16163896 ps
CPU time 0.79 seconds
Started Jul 09 05:46:54 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 207084 kb
Host smart-e8245174-6cc1-40ab-ac94-deaae67e397c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817559659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2817559659 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2377132707
Short name T1158
Test name
Test status
Simulation time 36895218 ps
CPU time 0.69 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 207184 kb
Host smart-67fdd6a5-8280-442f-972b-21a5d23c0c55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377132707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2377132707
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1927822850
Short name T1180
Test name
Test status
Simulation time 93785644 ps
CPU time 1.46 seconds
Started Jul 09 05:46:44 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 215612 kb
Host smart-c27a6651-5e13-4c95-bf78-866d929144fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927822850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1927822850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3979073124
Short name T1120
Test name
Test status
Simulation time 81803344 ps
CPU time 1.09 seconds
Started Jul 09 05:46:40 PM PDT 24
Finished Jul 09 05:46:42 PM PDT 24
Peak memory 215940 kb
Host smart-ca173dd4-54b8-45f1-83d9-18627e132175
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979073124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3979073124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2310197272
Short name T1191
Test name
Test status
Simulation time 39405110 ps
CPU time 2.37 seconds
Started Jul 09 05:46:38 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 215916 kb
Host smart-9c98e95d-1182-4def-8a88-9413f6c48657
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310197272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2310197272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3477061032
Short name T1193
Test name
Test status
Simulation time 109918854 ps
CPU time 1.92 seconds
Started Jul 09 05:46:46 PM PDT 24
Finished Jul 09 05:46:49 PM PDT 24
Peak memory 215556 kb
Host smart-3113a121-ecce-4e1e-9380-a4a4fceec7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477061032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3477061032 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1563437479
Short name T1131
Test name
Test status
Simulation time 147685615 ps
CPU time 2.32 seconds
Started Jul 09 05:46:48 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 218040 kb
Host smart-f2b9c60e-3523-44bc-98ea-4b5e63c4eba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563437479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.15634
37479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.433210081
Short name T1146
Test name
Test status
Simulation time 102987740 ps
CPU time 0.71 seconds
Started Jul 09 05:47:17 PM PDT 24
Finished Jul 09 05:47:19 PM PDT 24
Peak memory 207088 kb
Host smart-77db5c84-cd14-4a0d-a827-141dfd60d106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433210081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.433210081 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.500323875
Short name T1175
Test name
Test status
Simulation time 28335628 ps
CPU time 0.74 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 206944 kb
Host smart-381560f1-e1ef-49a8-a225-ba1012faf0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500323875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.500323875 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.4268307052
Short name T143
Test name
Test status
Simulation time 32875796 ps
CPU time 0.8 seconds
Started Jul 09 05:47:09 PM PDT 24
Finished Jul 09 05:47:13 PM PDT 24
Peak memory 206896 kb
Host smart-aac4aff6-a2f6-465e-aff9-cd7b9985379e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268307052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.4268307052 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3870910184
Short name T1233
Test name
Test status
Simulation time 41281718 ps
CPU time 0.8 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 207056 kb
Host smart-c011e4e5-49da-461d-8d08-79a0b65caf46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870910184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3870910184 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2890013864
Short name T1136
Test name
Test status
Simulation time 51763191 ps
CPU time 0.72 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 206988 kb
Host smart-c3e21899-772b-41e2-9f27-337e7318e8b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890013864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2890013864 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.570212425
Short name T142
Test name
Test status
Simulation time 14822738 ps
CPU time 0.76 seconds
Started Jul 09 05:47:09 PM PDT 24
Finished Jul 09 05:47:13 PM PDT 24
Peak memory 207052 kb
Host smart-28c2b823-cdc2-4884-9f4d-fc41c30bbb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570212425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.570212425 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2122757897
Short name T1170
Test name
Test status
Simulation time 47593832 ps
CPU time 0.75 seconds
Started Jul 09 05:47:21 PM PDT 24
Finished Jul 09 05:47:22 PM PDT 24
Peak memory 207064 kb
Host smart-dc9bda2c-b373-45c1-9c0c-b04066633555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122757897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2122757897 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.695052487
Short name T1198
Test name
Test status
Simulation time 24391525 ps
CPU time 0.74 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 207052 kb
Host smart-75ad6e4d-0258-41cc-95d1-5f78a4ad62f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695052487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.695052487 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1039671195
Short name T1220
Test name
Test status
Simulation time 40709849 ps
CPU time 0.75 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:09 PM PDT 24
Peak memory 207028 kb
Host smart-6285ebe9-c2c0-4384-b23d-9226eaad88ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039671195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1039671195 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3629876188
Short name T1212
Test name
Test status
Simulation time 37767315 ps
CPU time 0.74 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:08 PM PDT 24
Peak memory 207084 kb
Host smart-009c0bf9-8d9d-4316-8186-1136fbe81714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629876188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3629876188 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3138387463
Short name T1094
Test name
Test status
Simulation time 428161344 ps
CPU time 4.9 seconds
Started Jul 09 05:46:44 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 206936 kb
Host smart-c1c6f0ec-03c7-4c13-a9e1-ebf7947f33fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138387463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3138387
463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.932051740
Short name T1204
Test name
Test status
Simulation time 661227342 ps
CPU time 8.02 seconds
Started Jul 09 05:46:50 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 207416 kb
Host smart-4a3a4d9a-d526-433f-a591-37f6cb641d67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932051740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.93205174
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3836739563
Short name T135
Test name
Test status
Simulation time 71748360 ps
CPU time 0.93 seconds
Started Jul 09 05:47:02 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 207028 kb
Host smart-7bd0e348-c1c1-4151-a9ea-31b655c561d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836739563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3836739
563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1334574156
Short name T1217
Test name
Test status
Simulation time 58837934 ps
CPU time 1.72 seconds
Started Jul 09 05:46:48 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 223800 kb
Host smart-63889cd2-3f48-4213-ae43-d658e611d650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334574156 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1334574156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2237652633
Short name T1096
Test name
Test status
Simulation time 26411132 ps
CPU time 1.07 seconds
Started Jul 09 05:46:54 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 215608 kb
Host smart-b9a0b6f8-7d40-4303-8751-bdb89409d0e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237652633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2237652633 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.3308538893
Short name T1128
Test name
Test status
Simulation time 39233384 ps
CPU time 0.74 seconds
Started Jul 09 05:46:39 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 207084 kb
Host smart-51c5f721-b576-4bc1-9265-d61751d799fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308538893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3308538893 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2645006608
Short name T128
Test name
Test status
Simulation time 111641942 ps
CPU time 1.12 seconds
Started Jul 09 05:46:39 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 215480 kb
Host smart-418fd014-c446-428a-8332-74d7cd0d4948
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645006608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2645006608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1153191189
Short name T1084
Test name
Test status
Simulation time 173052535 ps
CPU time 0.72 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 207176 kb
Host smart-690d55f9-1fba-49e4-b959-a7efdd30a929
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153191189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1153191189
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.593954563
Short name T1093
Test name
Test status
Simulation time 414799144 ps
CPU time 1.57 seconds
Started Jul 09 05:46:46 PM PDT 24
Finished Jul 09 05:46:48 PM PDT 24
Peak memory 216136 kb
Host smart-e950082e-89aa-42e5-921e-167561cf2526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593954563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_
outstanding.593954563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.183829972
Short name T1203
Test name
Test status
Simulation time 37485453 ps
CPU time 1.01 seconds
Started Jul 09 05:46:43 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 215748 kb
Host smart-6596fc88-7d81-48ce-b1b5-1c523053bd54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183829972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.183829972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2002968432
Short name T1095
Test name
Test status
Simulation time 46867046 ps
CPU time 2.39 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 215868 kb
Host smart-8fac0611-3569-4a73-b7b4-9c5aa3f33624
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002968432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.2002968432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1515242822
Short name T1218
Test name
Test status
Simulation time 382654607 ps
CPU time 1.38 seconds
Started Jul 09 05:46:46 PM PDT 24
Finished Jul 09 05:46:48 PM PDT 24
Peak memory 215636 kb
Host smart-073ea572-c85f-47d7-97eb-e3eb30a68150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515242822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1515242822 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1280367757
Short name T168
Test name
Test status
Simulation time 281023428 ps
CPU time 4.58 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 215668 kb
Host smart-b6702348-839c-4b00-a9d5-2e5fc021bdcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280367757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.12803
67757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.3538061930
Short name T1139
Test name
Test status
Simulation time 13412640 ps
CPU time 0.76 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 207064 kb
Host smart-01e40831-f528-447c-ae49-2a846602b06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538061930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3538061930 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1139763927
Short name T1121
Test name
Test status
Simulation time 20543286 ps
CPU time 0.73 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:09 PM PDT 24
Peak memory 207088 kb
Host smart-89491f70-43d4-431f-909f-78bfbf9ce866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139763927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1139763927 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.2995280655
Short name T1228
Test name
Test status
Simulation time 21718043 ps
CPU time 0.79 seconds
Started Jul 09 05:47:09 PM PDT 24
Finished Jul 09 05:47:13 PM PDT 24
Peak memory 207088 kb
Host smart-b3403fb1-f13a-43e6-b56b-7ead0ac2531e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995280655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2995280655 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.4217854740
Short name T161
Test name
Test status
Simulation time 16510287 ps
CPU time 0.78 seconds
Started Jul 09 05:47:02 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 206864 kb
Host smart-1cdfb10b-04ea-4054-bce9-e84af97cca68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217854740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.4217854740 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.3826120103
Short name T1237
Test name
Test status
Simulation time 38589387 ps
CPU time 0.76 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 206992 kb
Host smart-783ab554-de09-4e18-9649-f6a3586b9f8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826120103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3826120103 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.64793460
Short name T1105
Test name
Test status
Simulation time 14727121 ps
CPU time 0.73 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 207060 kb
Host smart-83fdbd39-1b36-496e-84d2-43db0b519447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64793460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.64793460 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.3685240214
Short name T1155
Test name
Test status
Simulation time 41796697 ps
CPU time 0.73 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 206892 kb
Host smart-512c6ce5-17ae-481e-87e2-98028d55ec38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685240214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3685240214 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2334101646
Short name T1111
Test name
Test status
Simulation time 41854265 ps
CPU time 0.74 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:57 PM PDT 24
Peak memory 207084 kb
Host smart-26c884c1-2d7a-4456-9d0e-4a5d4b16af88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334101646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2334101646 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3022020756
Short name T1200
Test name
Test status
Simulation time 16472576 ps
CPU time 0.78 seconds
Started Jul 09 05:47:01 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 207076 kb
Host smart-29d54216-e952-4f44-8e46-546e30a39620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022020756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3022020756 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1149252307
Short name T1224
Test name
Test status
Simulation time 14589187 ps
CPU time 0.76 seconds
Started Jul 09 05:47:07 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 207028 kb
Host smart-833901b7-1db7-4734-8150-8a12a3d6aae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149252307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1149252307 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.580057827
Short name T1090
Test name
Test status
Simulation time 396890284 ps
CPU time 9.4 seconds
Started Jul 09 05:46:43 PM PDT 24
Finished Jul 09 05:46:53 PM PDT 24
Peak memory 207372 kb
Host smart-4194ceee-cffa-4824-9dea-e78d7a7f2f4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580057827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.58005782
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2972478840
Short name T147
Test name
Test status
Simulation time 2955157659 ps
CPU time 20.86 seconds
Started Jul 09 05:46:40 PM PDT 24
Finished Jul 09 05:47:01 PM PDT 24
Peak memory 207512 kb
Host smart-eea107c0-5f6e-4462-963a-8e2906e20e94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972478840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2972478
840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.659510702
Short name T1117
Test name
Test status
Simulation time 20066369 ps
CPU time 0.95 seconds
Started Jul 09 05:46:54 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 207228 kb
Host smart-f8fd3267-2602-4a9a-a239-27772407eb0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659510702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.65951070
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.276215551
Short name T1129
Test name
Test status
Simulation time 163112476 ps
CPU time 1.63 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:09 PM PDT 24
Peak memory 215992 kb
Host smart-032ccb72-cd96-456c-ae8a-106b3aa7539d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276215551 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.276215551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3262267494
Short name T1167
Test name
Test status
Simulation time 19123458 ps
CPU time 0.97 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:49 PM PDT 24
Peak memory 207204 kb
Host smart-a007c2d0-3a87-47eb-b4c9-1a3e476f9210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262267494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3262267494 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3829807474
Short name T1165
Test name
Test status
Simulation time 21564818 ps
CPU time 0.76 seconds
Started Jul 09 05:46:54 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 207060 kb
Host smart-b19a3e17-fcc4-4d5a-af6d-2b437878a94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829807474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3829807474 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1474818434
Short name T127
Test name
Test status
Simulation time 43806860 ps
CPU time 1.44 seconds
Started Jul 09 05:46:48 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 215536 kb
Host smart-108b9807-b489-493b-8fbe-1fec2d2fb643
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474818434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.1474818434 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3198675306
Short name T1153
Test name
Test status
Simulation time 16435586 ps
CPU time 0.76 seconds
Started Jul 09 05:46:53 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 207144 kb
Host smart-f26c26ff-191d-4ea7-a09c-32d5c7ada546
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198675306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3198675306
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3617769987
Short name T1083
Test name
Test status
Simulation time 79995744 ps
CPU time 1.32 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:49 PM PDT 24
Peak memory 215500 kb
Host smart-bfa81dde-887c-4de5-bfbb-ad46fd3f0d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617769987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3617769987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1531914864
Short name T1099
Test name
Test status
Simulation time 108060020 ps
CPU time 1.1 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 215936 kb
Host smart-fb5bc974-11ab-4b78-b152-c1bf52da8a84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531914864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.1531914864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1676829879
Short name T1173
Test name
Test status
Simulation time 761876548 ps
CPU time 3.31 seconds
Started Jul 09 05:46:48 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 223768 kb
Host smart-eee83509-8320-4a63-8fba-2d2583ca066d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676829879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.1676829879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.732368581
Short name T1089
Test name
Test status
Simulation time 44061414 ps
CPU time 1.39 seconds
Started Jul 09 05:46:44 PM PDT 24
Finished Jul 09 05:46:46 PM PDT 24
Peak memory 215564 kb
Host smart-eba17698-3906-47fa-95e5-ee0dd226b0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732368581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.732368581 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1327462163
Short name T138
Test name
Test status
Simulation time 121629524 ps
CPU time 3.05 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 207388 kb
Host smart-1e152a72-36ed-42ed-b259-f66daf021e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327462163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.13274
62163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.550673986
Short name T1171
Test name
Test status
Simulation time 40613807 ps
CPU time 0.74 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 207068 kb
Host smart-ca3b3c67-7133-45bf-973c-40b9134d4e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550673986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.550673986 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.4093440124
Short name T1145
Test name
Test status
Simulation time 146236028 ps
CPU time 0.75 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 207004 kb
Host smart-0acec777-4122-467d-84af-4f1c8ddb63a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093440124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.4093440124 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.2073246923
Short name T1226
Test name
Test status
Simulation time 23659108 ps
CPU time 0.77 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:53 PM PDT 24
Peak memory 207060 kb
Host smart-05c461ef-e4a7-484b-9e6b-1ad543d4798a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073246923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2073246923 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.3715416108
Short name T160
Test name
Test status
Simulation time 15064870 ps
CPU time 0.76 seconds
Started Jul 09 05:47:03 PM PDT 24
Finished Jul 09 05:47:06 PM PDT 24
Peak memory 207092 kb
Host smart-17c78771-60a7-4bc0-a2d4-574d35e627cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715416108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3715416108 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1057922887
Short name T1202
Test name
Test status
Simulation time 49959844 ps
CPU time 0.74 seconds
Started Jul 09 05:47:11 PM PDT 24
Finished Jul 09 05:47:15 PM PDT 24
Peak memory 207088 kb
Host smart-175a2bd7-66ed-4c88-bb05-24641a301152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057922887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1057922887 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.774989405
Short name T1192
Test name
Test status
Simulation time 86740900 ps
CPU time 0.75 seconds
Started Jul 09 05:47:00 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 207076 kb
Host smart-0831829e-4440-484b-a96d-a7d9aee9f3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774989405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.774989405 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.2284103552
Short name T1184
Test name
Test status
Simulation time 177304294 ps
CPU time 0.74 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:57 PM PDT 24
Peak memory 207088 kb
Host smart-f452ff6e-67e9-48f5-846c-2075d605bc54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284103552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2284103552 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.2251140862
Short name T1214
Test name
Test status
Simulation time 45386535 ps
CPU time 0.81 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:08 PM PDT 24
Peak memory 206992 kb
Host smart-dfc6ec2e-24f8-4da0-8f4d-961179ac3fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251140862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2251140862 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.267649480
Short name T114
Test name
Test status
Simulation time 13782008 ps
CPU time 0.77 seconds
Started Jul 09 05:46:59 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 207020 kb
Host smart-b7dbffad-9b2d-4f97-b621-eacc183d520e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267649480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.267649480 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1275544132
Short name T1187
Test name
Test status
Simulation time 23210927 ps
CPU time 0.71 seconds
Started Jul 09 05:47:06 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 207076 kb
Host smart-eb41f1c2-9694-4f16-b096-9a1ac1ea20b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275544132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1275544132 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.422128447
Short name T1172
Test name
Test status
Simulation time 77358178 ps
CPU time 1.44 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 223784 kb
Host smart-b0c08a4b-5197-4ab7-8b1b-e9e964833545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422128447 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.422128447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4085066054
Short name T1163
Test name
Test status
Simulation time 45123480 ps
CPU time 1.09 seconds
Started Jul 09 05:46:53 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 207416 kb
Host smart-72a7330a-a793-4fa1-87a4-614702d1113d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085066054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.4085066054 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1848196354
Short name T1178
Test name
Test status
Simulation time 42147073 ps
CPU time 0.76 seconds
Started Jul 09 05:47:02 PM PDT 24
Finished Jul 09 05:47:04 PM PDT 24
Peak memory 207060 kb
Host smart-956c8670-e1cf-4523-8011-f480da5495cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848196354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1848196354 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.481727704
Short name T1152
Test name
Test status
Simulation time 43882450 ps
CPU time 1.38 seconds
Started Jul 09 05:49:25 PM PDT 24
Finished Jul 09 05:49:27 PM PDT 24
Peak memory 215664 kb
Host smart-96f73063-7dc0-4c99-86e9-d8349bc3c235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481727704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.481727704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3568993553
Short name T1124
Test name
Test status
Simulation time 74263990 ps
CPU time 1.26 seconds
Started Jul 09 05:46:43 PM PDT 24
Finished Jul 09 05:46:45 PM PDT 24
Peak memory 215920 kb
Host smart-91303328-b741-4cdb-87bf-0033eca62bc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568993553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.3568993553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.402888799
Short name T1119
Test name
Test status
Simulation time 129200025 ps
CPU time 1.73 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 216144 kb
Host smart-3df36bd9-b13c-4d5e-80bb-ed22e9c8c480
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402888799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.402888799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.101704616
Short name T1137
Test name
Test status
Simulation time 195089770 ps
CPU time 2.74 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:48 PM PDT 24
Peak memory 215600 kb
Host smart-743dfe9b-d775-4cbd-b638-1e28b91b8502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101704616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.101704616 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.961542314
Short name T166
Test name
Test status
Simulation time 98787248 ps
CPU time 4.15 seconds
Started Jul 09 05:47:05 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 215588 kb
Host smart-9a08b96f-34bf-449d-9fa4-8a556ebd3978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961542314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.961542
314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.543578814
Short name T1159
Test name
Test status
Simulation time 48454582 ps
CPU time 1.68 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 216040 kb
Host smart-4e54f23b-cf59-4c2e-8ce4-4424eb41fba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543578814 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.543578814 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.568821555
Short name T1156
Test name
Test status
Simulation time 15583525 ps
CPU time 1.07 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 215660 kb
Host smart-798a7b58-4a0d-4fb2-a3f0-990f72473af2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568821555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.568821555 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.1291514933
Short name T1113
Test name
Test status
Simulation time 22681022 ps
CPU time 0.87 seconds
Started Jul 09 05:46:48 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 207084 kb
Host smart-daeb483c-799e-45af-89de-4da9282065d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291514933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1291514933 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2772578943
Short name T1225
Test name
Test status
Simulation time 314547570 ps
CPU time 1.59 seconds
Started Jul 09 05:46:56 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 216044 kb
Host smart-de0f175e-24b5-41a7-b633-3513f62bc458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772578943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.2772578943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3037460129
Short name T101
Test name
Test status
Simulation time 62361303 ps
CPU time 1.37 seconds
Started Jul 09 05:46:53 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 215976 kb
Host smart-85a4ff82-27a1-4a26-920c-b3357c129f3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037460129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3037460129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2582821132
Short name T1142
Test name
Test status
Simulation time 116486773 ps
CPU time 1.6 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:49 PM PDT 24
Peak memory 215892 kb
Host smart-c6d9dce1-bfdc-41c2-9198-b3c5c395339d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582821132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2582821132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2274776763
Short name T119
Test name
Test status
Simulation time 72061417 ps
CPU time 1.35 seconds
Started Jul 09 05:46:37 PM PDT 24
Finished Jul 09 05:46:39 PM PDT 24
Peak memory 215820 kb
Host smart-c667997a-4644-4364-b46b-672ed735db2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274776763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2274776763 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3216759011
Short name T1240
Test name
Test status
Simulation time 423171269 ps
CPU time 2.79 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:59 PM PDT 24
Peak memory 215588 kb
Host smart-7a508e06-dc3b-4f93-bc3b-5aaedf0efdfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216759011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.32167
59011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1297319693
Short name T1189
Test name
Test status
Simulation time 53701748 ps
CPU time 1.45 seconds
Started Jul 09 05:46:50 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 222276 kb
Host smart-76f9947e-fe23-4976-ad07-4c4f19326245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297319693 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1297319693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2940344665
Short name T1122
Test name
Test status
Simulation time 35934773 ps
CPU time 1.07 seconds
Started Jul 09 05:46:52 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 207456 kb
Host smart-6fd28243-1170-485f-85a3-a3fae592c30a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940344665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2940344665 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.2061006880
Short name T1213
Test name
Test status
Simulation time 14467384 ps
CPU time 0.73 seconds
Started Jul 09 05:46:43 PM PDT 24
Finished Jul 09 05:46:45 PM PDT 24
Peak memory 207072 kb
Host smart-fc94fffa-f265-4ab5-8f4e-4f15b30ec02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061006880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2061006880 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2130861298
Short name T1109
Test name
Test status
Simulation time 262550153 ps
CPU time 1.52 seconds
Started Jul 09 05:46:48 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 215904 kb
Host smart-c394986c-94b5-4c53-b4f7-858de8d06996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130861298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2130861298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3519336425
Short name T1179
Test name
Test status
Simulation time 27475028 ps
CPU time 1.07 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:57 PM PDT 24
Peak memory 215924 kb
Host smart-6106bf96-91c8-4000-8a76-e8fcc8303d74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519336425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.3519336425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2571941864
Short name T1134
Test name
Test status
Simulation time 380077822 ps
CPU time 2.74 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:48 PM PDT 24
Peak memory 215956 kb
Host smart-2ca44460-f462-420f-8cba-00bd732c3d9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571941864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2571941864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2114970121
Short name T115
Test name
Test status
Simulation time 375917847 ps
CPU time 1.76 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 215556 kb
Host smart-2f2febab-bea1-4a84-a318-97d0bd48642d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114970121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2114970121 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3679593729
Short name T1162
Test name
Test status
Simulation time 816298636 ps
CPU time 4.45 seconds
Started Jul 09 05:46:46 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 215784 kb
Host smart-79f996e2-37c0-43b2-9d8e-d401c90f309c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679593729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.36795
93729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.749083060
Short name T1201
Test name
Test status
Simulation time 25021936 ps
CPU time 1.69 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 223704 kb
Host smart-68ddb857-428f-41ee-8c40-065ba1718d62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749083060 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.749083060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1938815317
Short name T1100
Test name
Test status
Simulation time 15403136 ps
CPU time 1.05 seconds
Started Jul 09 05:46:54 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 215572 kb
Host smart-8f1c6049-d758-4e1e-a801-259950a82bdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938815317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1938815317 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3375634054
Short name T1236
Test name
Test status
Simulation time 12929449 ps
CPU time 0.79 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 207080 kb
Host smart-474f6e30-cf8c-4f4b-9dfd-f78787e54709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375634054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3375634054 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2827635031
Short name T1199
Test name
Test status
Simulation time 92324709 ps
CPU time 1.55 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:55 PM PDT 24
Peak memory 215524 kb
Host smart-4defbc5b-e73b-481a-a36d-e706b442b663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827635031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.2827635031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3586486663
Short name T1239
Test name
Test status
Simulation time 37154355 ps
CPU time 1.2 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:54 PM PDT 24
Peak memory 215924 kb
Host smart-9e2f1537-3f82-4833-9d32-a3aecc714182
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586486663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.3586486663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2045638458
Short name T1229
Test name
Test status
Simulation time 124563268 ps
CPU time 1.81 seconds
Started Jul 09 05:46:57 PM PDT 24
Finished Jul 09 05:47:03 PM PDT 24
Peak memory 215916 kb
Host smart-b35dcf01-ab3a-4ab4-a995-6ea6f6f11190
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045638458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.2045638458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2427312763
Short name T1088
Test name
Test status
Simulation time 26101070 ps
CPU time 1.53 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:46:57 PM PDT 24
Peak memory 218728 kb
Host smart-51b0bbac-ef53-43ec-8f1b-16aace43558e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427312763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2427312763 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3452410859
Short name T1219
Test name
Test status
Simulation time 494191591 ps
CPU time 4.8 seconds
Started Jul 09 05:46:55 PM PDT 24
Finished Jul 09 05:47:01 PM PDT 24
Peak memory 215612 kb
Host smart-bf9174e2-0386-4314-8782-2b1de0f902a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452410859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.34524
10859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3356121244
Short name T1114
Test name
Test status
Simulation time 63982317 ps
CPU time 2.17 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:02 PM PDT 24
Peak memory 216664 kb
Host smart-c4d9647e-a800-49c8-9276-c3206c89e062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356121244 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3356121244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.958905521
Short name T1207
Test name
Test status
Simulation time 14051678 ps
CPU time 0.86 seconds
Started Jul 09 05:46:50 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 207164 kb
Host smart-9e9b6c7f-0c02-4fe5-9ef8-332bd8254b3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958905521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.958905521 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.1294754573
Short name T1161
Test name
Test status
Simulation time 45726199 ps
CPU time 0.78 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 207084 kb
Host smart-607ba3d1-1f4a-4e86-ba88-84766cceac4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294754573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1294754573 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3749609753
Short name T136
Test name
Test status
Simulation time 72763897 ps
CPU time 1.49 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:01 PM PDT 24
Peak memory 215712 kb
Host smart-6c4def19-7081-45f3-a2da-7ed0909805ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749609753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.3749609753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.700383397
Short name T1141
Test name
Test status
Simulation time 42418688 ps
CPU time 1.26 seconds
Started Jul 09 05:46:58 PM PDT 24
Finished Jul 09 05:47:01 PM PDT 24
Peak memory 216000 kb
Host smart-2ba72d17-3a45-4d5e-8558-8619c5869ac7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700383397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.700383397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4088963567
Short name T103
Test name
Test status
Simulation time 248114626 ps
CPU time 2.28 seconds
Started Jul 09 05:47:04 PM PDT 24
Finished Jul 09 05:47:10 PM PDT 24
Peak memory 223820 kb
Host smart-85f70897-c1bd-403e-b14c-5865b3e8cfaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088963567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.4088963567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2936551455
Short name T1150
Test name
Test status
Simulation time 73955601 ps
CPU time 1.38 seconds
Started Jul 09 05:47:02 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 215564 kb
Host smart-7911a401-9876-4bbc-93a8-4a2e191a5f57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936551455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2936551455 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4010370943
Short name T164
Test name
Test status
Simulation time 317229496 ps
CPU time 4.87 seconds
Started Jul 09 05:46:54 PM PDT 24
Finished Jul 09 05:47:00 PM PDT 24
Peak memory 215612 kb
Host smart-0ffd7b2d-7677-4237-8465-7890c025ee4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010370943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.40103
70943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.2857310824
Short name T786
Test name
Test status
Simulation time 22661663 ps
CPU time 0.77 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 05:49:29 PM PDT 24
Peak memory 205356 kb
Host smart-f7db0c97-6268-446a-9b4e-e0b2a8465ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857310824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2857310824 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.275492080
Short name T847
Test name
Test status
Simulation time 2927880618 ps
CPU time 110.69 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 05:51:18 PM PDT 24
Peak memory 232188 kb
Host smart-99477b60-f21d-4ad0-9deb-a4cb58670691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275492080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.275492080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.2618717791
Short name T808
Test name
Test status
Simulation time 48020048695 ps
CPU time 171.47 seconds
Started Jul 09 05:49:29 PM PDT 24
Finished Jul 09 05:52:21 PM PDT 24
Peak memory 236132 kb
Host smart-4010357e-b3c1-4d62-b409-242031886a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618717791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2618717791 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2469639739
Short name T992
Test name
Test status
Simulation time 37426368091 ps
CPU time 537.02 seconds
Started Jul 09 05:49:25 PM PDT 24
Finished Jul 09 05:58:23 PM PDT 24
Peak memory 238520 kb
Host smart-623a75eb-4758-41f7-85dc-acdc9f055498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469639739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2469639739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.2584134323
Short name T1065
Test name
Test status
Simulation time 191836517 ps
CPU time 6.3 seconds
Started Jul 09 05:49:28 PM PDT 24
Finished Jul 09 05:49:35 PM PDT 24
Peak memory 220568 kb
Host smart-ec3612d3-7bce-441c-bd9d-7b8262aae4dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2584134323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2584134323 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.1608462930
Short name T867
Test name
Test status
Simulation time 839674627 ps
CPU time 16.03 seconds
Started Jul 09 05:49:24 PM PDT 24
Finished Jul 09 05:49:40 PM PDT 24
Peak memory 219492 kb
Host smart-e8f1f555-ee1b-4368-a15c-f6d5cb48da58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1608462930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1608462930 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.2346803600
Short name T1031
Test name
Test status
Simulation time 10401915596 ps
CPU time 51.51 seconds
Started Jul 09 05:49:24 PM PDT 24
Finished Jul 09 05:50:16 PM PDT 24
Peak memory 223464 kb
Host smart-7d830112-a30f-4c63-ad44-19ee11709b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346803600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2346803600 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.438076331
Short name T24
Test name
Test status
Simulation time 3664740325 ps
CPU time 127.09 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:51:49 PM PDT 24
Peak memory 248408 kb
Host smart-a4b011f9-6326-464a-91fd-6b73ddbdd0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438076331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.438076331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3331458330
Short name T669
Test name
Test status
Simulation time 4407954670 ps
CPU time 5.51 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 05:49:34 PM PDT 24
Peak memory 215648 kb
Host smart-4488bef0-1042-4452-942f-35d6dd364a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331458330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3331458330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.878425200
Short name T916
Test name
Test status
Simulation time 125734390 ps
CPU time 1.31 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:49:43 PM PDT 24
Peak memory 215632 kb
Host smart-3fb38097-363a-494a-be98-af839ce4064c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878425200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.878425200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.4054026703
Short name T703
Test name
Test status
Simulation time 154418536289 ps
CPU time 698.43 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 06:01:06 PM PDT 24
Peak memory 285972 kb
Host smart-6a049583-6cb2-40b3-a2db-ac2bacf4f44f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054026703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.4054026703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.3999131150
Short name T411
Test name
Test status
Simulation time 159325486 ps
CPU time 10.82 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 05:49:38 PM PDT 24
Peak memory 224020 kb
Host smart-5f534143-edf3-4c0c-8e80-33d19275ca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999131150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3999131150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.3021673866
Short name T74
Test name
Test status
Simulation time 2437388460 ps
CPU time 34.31 seconds
Started Jul 09 05:49:20 PM PDT 24
Finished Jul 09 05:49:55 PM PDT 24
Peak memory 248364 kb
Host smart-38e76be6-99ac-4a53-8e6d-b21ec5c6c3b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021673866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3021673866 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.4152221614
Short name T272
Test name
Test status
Simulation time 1475070805 ps
CPU time 27.56 seconds
Started Jul 09 05:49:28 PM PDT 24
Finished Jul 09 05:49:56 PM PDT 24
Peak memory 235040 kb
Host smart-6f021b84-1278-49a8-9e7d-7df633fe87a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152221614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.4152221614 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2862699693
Short name T906
Test name
Test status
Simulation time 1899354048 ps
CPU time 24.45 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 05:49:59 PM PDT 24
Peak memory 220428 kb
Host smart-7b9d8040-637d-4453-8f8c-95caeeed77f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862699693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2862699693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.89343314
Short name T902
Test name
Test status
Simulation time 64859339775 ps
CPU time 404.39 seconds
Started Jul 09 05:49:25 PM PDT 24
Finished Jul 09 05:56:10 PM PDT 24
Peak memory 285348 kb
Host smart-129f2452-c583-483b-8ea9-84e91289a23f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=89343314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.89343314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.1814628457
Short name T1069
Test name
Test status
Simulation time 67259153 ps
CPU time 3.98 seconds
Started Jul 09 05:49:29 PM PDT 24
Finished Jul 09 05:49:34 PM PDT 24
Peak memory 215648 kb
Host smart-f5c7c988-f30e-477e-ac17-763c4ded92d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814628457 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.1814628457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2499213722
Short name T228
Test name
Test status
Simulation time 249223667 ps
CPU time 3.81 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 05:49:31 PM PDT 24
Peak memory 215668 kb
Host smart-2676e5da-349c-4402-ad58-08cc231fbf11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499213722 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2499213722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3799303265
Short name T1064
Test name
Test status
Simulation time 101004948143 ps
CPU time 1937.27 seconds
Started Jul 09 05:49:21 PM PDT 24
Finished Jul 09 06:21:39 PM PDT 24
Peak memory 387956 kb
Host smart-3d9a4a71-d92d-4c17-acdc-13bcce98a397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3799303265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3799303265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.523284067
Short name T260
Test name
Test status
Simulation time 92659632082 ps
CPU time 1649.74 seconds
Started Jul 09 05:49:28 PM PDT 24
Finished Jul 09 06:16:59 PM PDT 24
Peak memory 375424 kb
Host smart-503454b4-c24d-489d-b59a-608ca6fc7dfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=523284067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.523284067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.4279358199
Short name T302
Test name
Test status
Simulation time 18083919439 ps
CPU time 1164.81 seconds
Started Jul 09 05:49:54 PM PDT 24
Finished Jul 09 06:09:21 PM PDT 24
Peak memory 329520 kb
Host smart-b4c75c06-5c8b-4df1-b639-ae5dcefa292c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4279358199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.4279358199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.831800702
Short name T458
Test name
Test status
Simulation time 59933894042 ps
CPU time 921.22 seconds
Started Jul 09 05:49:11 PM PDT 24
Finished Jul 09 06:04:33 PM PDT 24
Peak memory 290168 kb
Host smart-acaca3be-88ca-440a-a34b-1f18436e71fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=831800702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.831800702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1846293480
Short name T622
Test name
Test status
Simulation time 259537823824 ps
CPU time 5373.66 seconds
Started Jul 09 05:49:25 PM PDT 24
Finished Jul 09 07:19:00 PM PDT 24
Peak memory 661640 kb
Host smart-31ba4145-514c-490f-bd0f-d46e8f71b45e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1846293480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1846293480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.2546507743
Short name T218
Test name
Test status
Simulation time 89390136971 ps
CPU time 3184.73 seconds
Started Jul 09 05:49:23 PM PDT 24
Finished Jul 09 06:42:29 PM PDT 24
Peak memory 553300 kb
Host smart-64edd37b-cc3c-45ac-969a-c528dcbd3d66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2546507743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2546507743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.1504539135
Short name T81
Test name
Test status
Simulation time 40248846 ps
CPU time 0.74 seconds
Started Jul 09 05:49:31 PM PDT 24
Finished Jul 09 05:49:32 PM PDT 24
Peak memory 205260 kb
Host smart-954c5113-2a08-48a7-85e9-2b06646b0be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504539135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1504539135 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.3740934535
Short name T774
Test name
Test status
Simulation time 59940739210 ps
CPU time 286.11 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:54:28 PM PDT 24
Peak memory 246716 kb
Host smart-9f432795-6447-483c-bb22-b470854ed07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740934535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3740934535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.3371939739
Short name T365
Test name
Test status
Simulation time 13639731440 ps
CPU time 268.84 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:54:11 PM PDT 24
Peak memory 243144 kb
Host smart-5cf4824e-354f-4ce7-9737-7c78f160d197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371939739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.3371939739 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1821195531
Short name T878
Test name
Test status
Simulation time 941553960 ps
CPU time 34.96 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 05:50:03 PM PDT 24
Peak memory 217976 kb
Host smart-c0185520-7d5b-4bdb-b1e5-d9090cfe463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821195531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1821195531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.2164933426
Short name T178
Test name
Test status
Simulation time 3521092859 ps
CPU time 35.61 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 05:50:12 PM PDT 24
Peak memory 223808 kb
Host smart-46ff9434-bb23-4e0b-8604-729fe992fcf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2164933426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2164933426 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.474375651
Short name T183
Test name
Test status
Simulation time 2822905177 ps
CPU time 18.14 seconds
Started Jul 09 05:49:38 PM PDT 24
Finished Jul 09 05:49:56 PM PDT 24
Peak memory 223828 kb
Host smart-c47842c3-cca2-482e-b5ca-d89ec6cb20ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=474375651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.474375651 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.934029926
Short name T482
Test name
Test status
Simulation time 16282315233 ps
CPU time 45.91 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:50:36 PM PDT 24
Peak memory 223844 kb
Host smart-f9b80b23-082c-49a4-8ca1-c1e00de7e9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934029926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.934029926 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.915354385
Short name T1051
Test name
Test status
Simulation time 18151415993 ps
CPU time 345.47 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 05:55:29 PM PDT 24
Peak memory 249492 kb
Host smart-e650873f-5817-4e58-b11c-a382b7077578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915354385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.915354385 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1495715318
Short name T754
Test name
Test status
Simulation time 1252944806 ps
CPU time 43.57 seconds
Started Jul 09 05:49:29 PM PDT 24
Finished Jul 09 05:50:13 PM PDT 24
Peak memory 239712 kb
Host smart-52971037-a810-4c7a-8a42-3fb37d9c5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495715318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1495715318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.3651830120
Short name T640
Test name
Test status
Simulation time 2282644355 ps
CPU time 8.81 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:49:51 PM PDT 24
Peak memory 207520 kb
Host smart-f169edf7-2df2-4743-a5e5-745f94f8d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651830120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3651830120 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.218171800
Short name T35
Test name
Test status
Simulation time 59966984 ps
CPU time 1.23 seconds
Started Jul 09 05:49:27 PM PDT 24
Finished Jul 09 05:49:29 PM PDT 24
Peak memory 215544 kb
Host smart-2b8cb3f8-79e3-4ee5-94fa-a891ce498181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218171800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.218171800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1823217527
Short name T594
Test name
Test status
Simulation time 27264861778 ps
CPU time 272.57 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:54:21 PM PDT 24
Peak memory 243428 kb
Host smart-b596bce0-cb6b-4693-8105-2cdad9a82f04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823217527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1823217527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.180224182
Short name T853
Test name
Test status
Simulation time 20937171425 ps
CPU time 118.99 seconds
Started Jul 09 05:49:33 PM PDT 24
Finished Jul 09 05:51:33 PM PDT 24
Peak memory 232436 kb
Host smart-7e4fb16a-b070-4eb7-80a7-09a014d052fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180224182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.180224182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.1279295942
Short name T796
Test name
Test status
Simulation time 60119670389 ps
CPU time 254.04 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 05:53:50 PM PDT 24
Peak memory 241504 kb
Host smart-652989ca-c50a-4a3a-a237-09740e11b058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279295942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1279295942 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2510650746
Short name T528
Test name
Test status
Simulation time 9876541115 ps
CPU time 45.49 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 05:50:25 PM PDT 24
Peak memory 215780 kb
Host smart-73c9d58e-28ac-4910-9e1d-e015cbae7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510650746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2510650746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1638844251
Short name T491
Test name
Test status
Simulation time 124725655020 ps
CPU time 1436.18 seconds
Started Jul 09 05:49:30 PM PDT 24
Finished Jul 09 06:13:27 PM PDT 24
Peak memory 366308 kb
Host smart-bca0cea7-57a0-48b3-af69-b21818646cc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1638844251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1638844251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.1460282020
Short name T222
Test name
Test status
Simulation time 256499697 ps
CPU time 3.95 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 05:49:40 PM PDT 24
Peak memory 215680 kb
Host smart-68f6da16-4d18-4cad-bdb8-134705d4ad99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460282020 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.1460282020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.398347247
Short name T578
Test name
Test status
Simulation time 66377569 ps
CPU time 3.95 seconds
Started Jul 09 05:49:24 PM PDT 24
Finished Jul 09 05:49:28 PM PDT 24
Peak memory 215596 kb
Host smart-9ba7796c-2562-4e2d-94ea-6995d27db6bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398347247 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.kmac_test_vectors_kmac_xof.398347247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.1450280216
Short name T1039
Test name
Test status
Simulation time 75745208078 ps
CPU time 1616.99 seconds
Started Jul 09 05:49:33 PM PDT 24
Finished Jul 09 06:16:35 PM PDT 24
Peak memory 394080 kb
Host smart-40b9a227-d026-46fe-ac22-668cc8104275
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1450280216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1450280216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.276707627
Short name T1045
Test name
Test status
Simulation time 62745699455 ps
CPU time 1752.36 seconds
Started Jul 09 05:49:25 PM PDT 24
Finished Jul 09 06:18:38 PM PDT 24
Peak memory 368592 kb
Host smart-04c6aec7-af34-4617-9197-762bd99bee82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=276707627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.276707627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.1079763277
Short name T504
Test name
Test status
Simulation time 71880612876 ps
CPU time 1304.65 seconds
Started Jul 09 05:49:30 PM PDT 24
Finished Jul 09 06:11:16 PM PDT 24
Peak memory 330320 kb
Host smart-2694b799-29d8-43c8-926b-2c2f29dc3a72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1079763277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1079763277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.1770972848
Short name T710
Test name
Test status
Simulation time 42892526803 ps
CPU time 794.78 seconds
Started Jul 09 05:49:30 PM PDT 24
Finished Jul 09 06:02:45 PM PDT 24
Peak memory 293956 kb
Host smart-65ce050d-e43d-46fb-99ef-ba64a6407645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1770972848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1770972848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3212644313
Short name T247
Test name
Test status
Simulation time 63778164909 ps
CPU time 3300.94 seconds
Started Jul 09 05:49:30 PM PDT 24
Finished Jul 09 06:44:32 PM PDT 24
Peak memory 563140 kb
Host smart-63036210-787d-4983-a467-ef574b5d0d58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3212644313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3212644313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_app.3567153817
Short name T596
Test name
Test status
Simulation time 2406416337 ps
CPU time 109.13 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:51:39 PM PDT 24
Peak memory 231360 kb
Host smart-ea686136-1940-41e6-a65b-abe6e67e7b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567153817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.3567153817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.3367775989
Short name T2
Test name
Test status
Simulation time 14506611999 ps
CPU time 327.68 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 05:55:32 PM PDT 24
Peak memory 227744 kb
Host smart-c755a8ad-5d15-4f02-ae63-b287d2ca094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367775989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3367775989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.1611748813
Short name T904
Test name
Test status
Simulation time 1716837884 ps
CPU time 33.55 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 05:50:30 PM PDT 24
Peak memory 223688 kb
Host smart-c0785f3f-18a9-4516-a323-9ad4a5f90d0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1611748813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1611748813 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.1862591505
Short name T1029
Test name
Test status
Simulation time 629170770 ps
CPU time 3.42 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:49:57 PM PDT 24
Peak memory 215576 kb
Host smart-263995b8-6115-41fe-afd8-88381387e612
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862591505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1862591505 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.1735499883
Short name T123
Test name
Test status
Simulation time 69433827708 ps
CPU time 303.3 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:54:58 PM PDT 24
Peak memory 243656 kb
Host smart-97109911-c191-4b02-adf9-d92e49eae85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735499883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1735499883 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.2553116153
Short name T830
Test name
Test status
Simulation time 47938786098 ps
CPU time 233.14 seconds
Started Jul 09 05:49:52 PM PDT 24
Finished Jul 09 05:53:48 PM PDT 24
Peak memory 250540 kb
Host smart-d617dcb0-34bf-4d53-8355-46e89314cf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553116153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2553116153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.2130957505
Short name T65
Test name
Test status
Simulation time 322939440 ps
CPU time 2.06 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 05:49:59 PM PDT 24
Peak memory 215820 kb
Host smart-3ad07209-fcca-4609-adf0-dca2b8b54171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130957505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2130957505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.209812965
Short name T505
Test name
Test status
Simulation time 154412773 ps
CPU time 1.28 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:49:54 PM PDT 24
Peak memory 215652 kb
Host smart-c98160b2-f5e2-4376-89db-c03d7b86fb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209812965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.209812965 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.4266218853
Short name T947
Test name
Test status
Simulation time 84244190884 ps
CPU time 614.08 seconds
Started Jul 09 05:50:01 PM PDT 24
Finished Jul 09 06:00:15 PM PDT 24
Peak memory 278348 kb
Host smart-06c911a8-79e5-4dbb-8dff-c3c6512271e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266218853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.4266218853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2837674891
Short name T430
Test name
Test status
Simulation time 20506440841 ps
CPU time 111.89 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 05:51:48 PM PDT 24
Peak memory 227476 kb
Host smart-9780b935-3b2b-4222-80a7-83045a1fe33b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837674891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2837674891 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.1580591443
Short name T1000
Test name
Test status
Simulation time 3391138102 ps
CPU time 55.14 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 05:50:50 PM PDT 24
Peak memory 219184 kb
Host smart-e544c378-beb4-406e-906c-6c833dbd9b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580591443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1580591443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2772024737
Short name T446
Test name
Test status
Simulation time 89022337099 ps
CPU time 966.2 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 06:05:51 PM PDT 24
Peak memory 352612 kb
Host smart-e257bb98-f459-45c7-9883-dac04c23c7f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2772024737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2772024737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.2302945301
Short name T692
Test name
Test status
Simulation time 171926066 ps
CPU time 4.3 seconds
Started Jul 09 05:49:56 PM PDT 24
Finished Jul 09 05:50:01 PM PDT 24
Peak memory 208804 kb
Host smart-2971fb34-4770-4c35-8251-887f76e378bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302945301 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.2302945301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.2465836329
Short name T851
Test name
Test status
Simulation time 547135762 ps
CPU time 3.75 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:49:57 PM PDT 24
Peak memory 215628 kb
Host smart-a0b5f314-ae09-412e-9d30-fe164747d8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465836329 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.2465836329 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.16662145
Short name T623
Test name
Test status
Simulation time 130089077427 ps
CPU time 1919.34 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 06:21:52 PM PDT 24
Peak memory 392728 kb
Host smart-b9a9c246-1e09-4aaa-bbd4-67c0445dec98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16662145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.16662145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.2171782575
Short name T537
Test name
Test status
Simulation time 95663170286 ps
CPU time 1907.2 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 06:21:52 PM PDT 24
Peak memory 379100 kb
Host smart-6bb87c69-3ce3-4f7f-b9f5-819a4533c40f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2171782575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2171782575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.1925310030
Short name T778
Test name
Test status
Simulation time 59435958517 ps
CPU time 1338.37 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:12:06 PM PDT 24
Peak memory 328580 kb
Host smart-c06496af-8d2a-455f-a892-8e2003dfb83d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1925310030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.1925310030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.3473395208
Short name T242
Test name
Test status
Simulation time 41493768807 ps
CPU time 842.23 seconds
Started Jul 09 05:49:52 PM PDT 24
Finished Jul 09 06:03:57 PM PDT 24
Peak memory 290600 kb
Host smart-a8999488-0c70-4ac6-b873-0f96e524dfe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3473395208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.3473395208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.211552671
Short name T838
Test name
Test status
Simulation time 352554488351 ps
CPU time 4728.93 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 07:08:42 PM PDT 24
Peak memory 655760 kb
Host smart-b2784df7-28e0-4986-8b7e-9ad93c276d1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=211552671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.211552671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.627163233
Short name T494
Test name
Test status
Simulation time 432811487844 ps
CPU time 4155.3 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 06:59:12 PM PDT 24
Peak memory 560624 kb
Host smart-2f0d5c3b-e020-4af6-9750-c85c97d6b253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=627163233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.627163233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.1889912661
Short name T275
Test name
Test status
Simulation time 14371847 ps
CPU time 0.8 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:49:54 PM PDT 24
Peak memory 205348 kb
Host smart-73f6d4d1-870c-4632-b07e-3040c28d0bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889912661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1889912661 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2355932782
Short name T107
Test name
Test status
Simulation time 1830010193 ps
CPU time 32.59 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:23 PM PDT 24
Peak memory 223844 kb
Host smart-4659a725-005f-40f2-bec5-55bd557a7b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355932782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2355932782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.397548994
Short name T571
Test name
Test status
Simulation time 64436938701 ps
CPU time 326.66 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:55:18 PM PDT 24
Peak memory 226944 kb
Host smart-589ce049-1c44-4254-b9e9-d14d59010592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397548994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.397548994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1565140442
Short name T395
Test name
Test status
Simulation time 871498176 ps
CPU time 5.97 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:49:59 PM PDT 24
Peak memory 218860 kb
Host smart-e0a3ce10-de49-4d5b-8156-4e7b6925ff88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1565140442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1565140442 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.3102848329
Short name T221
Test name
Test status
Simulation time 8595997921 ps
CPU time 46.66 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:50:32 PM PDT 24
Peak memory 238052 kb
Host smart-7ff5197c-a145-44da-8e5e-3e2d26ec32f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3102848329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3102848329 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3838603884
Short name T154
Test name
Test status
Simulation time 10867627637 ps
CPU time 45.37 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:50:39 PM PDT 24
Peak memory 223124 kb
Host smart-f9e9a196-adf1-443a-93e7-e50dc1de9b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838603884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3838603884 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.3563630072
Short name T725
Test name
Test status
Simulation time 15134368435 ps
CPU time 248.82 seconds
Started Jul 09 05:49:57 PM PDT 24
Finished Jul 09 05:54:06 PM PDT 24
Peak memory 255848 kb
Host smart-8db45c34-5ed8-418c-b41d-ce44fa3a3159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563630072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3563630072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.3523051414
Short name T61
Test name
Test status
Simulation time 3438822792 ps
CPU time 5.5 seconds
Started Jul 09 05:50:03 PM PDT 24
Finished Jul 09 05:50:09 PM PDT 24
Peak memory 207520 kb
Host smart-425b8d8a-8370-4286-b9ca-796d17b1a6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523051414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3523051414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.1090822338
Short name T421
Test name
Test status
Simulation time 41671305 ps
CPU time 1.26 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 05:50:06 PM PDT 24
Peak memory 215628 kb
Host smart-a882ea8b-b7dc-4b6b-9bb6-01f90c987893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090822338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1090822338 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.128585583
Short name T665
Test name
Test status
Simulation time 350708699439 ps
CPU time 1700.66 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 06:18:11 PM PDT 24
Peak memory 368360 kb
Host smart-edf2ad44-2cdb-47b8-bd04-a3e32c6bfd06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128585583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an
d_output.128585583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.3191611454
Short name T364
Test name
Test status
Simulation time 146350299 ps
CPU time 4.13 seconds
Started Jul 09 05:50:03 PM PDT 24
Finished Jul 09 05:50:08 PM PDT 24
Peak memory 223800 kb
Host smart-e047159d-abf1-4eb3-a1f7-622ff0d18b77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191611454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3191611454 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.2113787270
Short name T907
Test name
Test status
Simulation time 8382831784 ps
CPU time 22.32 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 05:50:17 PM PDT 24
Peak memory 218756 kb
Host smart-69092249-4ed8-44a0-9b84-89b5c0488e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113787270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2113787270 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.2231830198
Short name T930
Test name
Test status
Simulation time 2927429240 ps
CPU time 228.36 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:53:40 PM PDT 24
Peak memory 239496 kb
Host smart-d6481033-b39b-4c2f-8944-d6dacc482ae1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2231830198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2231830198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.850944732
Short name T106
Test name
Test status
Simulation time 244076865 ps
CPU time 4.93 seconds
Started Jul 09 05:49:58 PM PDT 24
Finished Jul 09 05:50:04 PM PDT 24
Peak memory 215672 kb
Host smart-93218fa3-ad5b-4f71-8866-e1704126876a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850944732 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.kmac_test_vectors_kmac.850944732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2853527222
Short name T698
Test name
Test status
Simulation time 242274914 ps
CPU time 4.7 seconds
Started Jul 09 05:49:52 PM PDT 24
Finished Jul 09 05:50:00 PM PDT 24
Peak memory 215668 kb
Host smart-e3d550ea-fe00-41a1-a94d-7d6dc5a59b22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853527222 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2853527222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.1754974171
Short name T204
Test name
Test status
Simulation time 95794582178 ps
CPU time 1798.97 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 06:19:51 PM PDT 24
Peak memory 388292 kb
Host smart-9e04eb1f-c4cf-4fe1-9f9b-41e36cef8a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1754974171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.1754974171 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.3409586014
Short name T628
Test name
Test status
Simulation time 60729973054 ps
CPU time 1716.08 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:18:25 PM PDT 24
Peak memory 368328 kb
Host smart-453373dc-8a9b-46d2-b193-0a5645d4c50e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3409586014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3409586014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.813917227
Short name T788
Test name
Test status
Simulation time 49660501004 ps
CPU time 1268.88 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 06:11:06 PM PDT 24
Peak memory 336820 kb
Host smart-af9aca69-ba0e-4403-9650-06b073d2e5c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=813917227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.813917227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.239241184
Short name T325
Test name
Test status
Simulation time 172899228772 ps
CPU time 902.54 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:04:51 PM PDT 24
Peak memory 298864 kb
Host smart-1f1431c5-b477-4ff4-9088-abaafbf1d918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=239241184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.239241184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.3143303238
Short name T427
Test name
Test status
Simulation time 1026045370876 ps
CPU time 5283.86 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 07:17:58 PM PDT 24
Peak memory 650656 kb
Host smart-69f12fe8-45c2-4390-ab2d-5ceee8711a31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3143303238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.3143303238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.1354274906
Short name T858
Test name
Test status
Simulation time 87422959597 ps
CPU time 3188.4 seconds
Started Jul 09 05:49:57 PM PDT 24
Finished Jul 09 06:43:06 PM PDT 24
Peak memory 569616 kb
Host smart-210a0b3f-edf4-4beb-8bdd-f144e49ebbc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1354274906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1354274906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.3551435788
Short name T240
Test name
Test status
Simulation time 17962690 ps
CPU time 0.77 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:49:50 PM PDT 24
Peak memory 205348 kb
Host smart-78e7953d-c0b2-4898-ae0a-9b482a3cb719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551435788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3551435788 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.550535630
Short name T449
Test name
Test status
Simulation time 48489975275 ps
CPU time 49.02 seconds
Started Jul 09 05:49:52 PM PDT 24
Finished Jul 09 05:50:44 PM PDT 24
Peak memory 224120 kb
Host smart-932f8709-8532-4b42-8b90-411e6791c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550535630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.550535630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3119141875
Short name T889
Test name
Test status
Simulation time 2682846933 ps
CPU time 19.75 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:50:13 PM PDT 24
Peak memory 221244 kb
Host smart-a601a96b-01a1-457e-9ad6-f76a2c676ca6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3119141875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3119141875 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.4052571036
Short name T905
Test name
Test status
Simulation time 31274579037 ps
CPU time 47.17 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 05:50:41 PM PDT 24
Peak memory 221820 kb
Host smart-93c3313e-1b8e-4322-ae12-d3c7a6e8c569
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4052571036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4052571036 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.636276461
Short name T587
Test name
Test status
Simulation time 10476729030 ps
CPU time 47.14 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:38 PM PDT 24
Peak memory 223896 kb
Host smart-6c96ff3f-d36b-40d2-910e-b3b26b711684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636276461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.636276461 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.1870813316
Short name T48
Test name
Test status
Simulation time 2232281601 ps
CPU time 47.35 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:39 PM PDT 24
Peak memory 239672 kb
Host smart-c47d0d27-a15c-4719-9ce3-573c5cd11c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870813316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1870813316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.4225704305
Short name T715
Test name
Test status
Simulation time 1060554216 ps
CPU time 3.57 seconds
Started Jul 09 05:49:51 PM PDT 24
Finished Jul 09 05:49:58 PM PDT 24
Peak memory 207348 kb
Host smart-8eb2c27c-46b8-4347-a499-ad8cf4ddfc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225704305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.4225704305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.3148289885
Short name T597
Test name
Test status
Simulation time 303950106 ps
CPU time 1.06 seconds
Started Jul 09 05:49:59 PM PDT 24
Finished Jul 09 05:50:01 PM PDT 24
Peak memory 215572 kb
Host smart-d9212653-3994-4906-b273-e99c72c2e074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148289885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3148289885 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.3110398367
Short name T890
Test name
Test status
Simulation time 35763992557 ps
CPU time 1041.56 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 06:07:14 PM PDT 24
Peak memory 320064 kb
Host smart-ad23c92d-d5d4-4002-a5e8-a5bb711c1fae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110398367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.3110398367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1829013790
Short name T814
Test name
Test status
Simulation time 2496076443 ps
CPU time 174 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:52:44 PM PDT 24
Peak memory 237240 kb
Host smart-6bdac50a-c380-4ea6-8235-dd531476ef48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829013790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1829013790 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.2373413381
Short name T254
Test name
Test status
Simulation time 3975801823 ps
CPU time 50.98 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:50:42 PM PDT 24
Peak memory 223876 kb
Host smart-ac236e4a-a3a9-446e-90f1-681b03e5e570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373413381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2373413381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.2476224475
Short name T663
Test name
Test status
Simulation time 266557498 ps
CPU time 3.88 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 05:50:10 PM PDT 24
Peak memory 215824 kb
Host smart-c5c55f0c-c598-43b8-8344-8c969efd70eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2476224475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2476224475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.1309239466
Short name T900
Test name
Test status
Simulation time 674925746 ps
CPU time 4.37 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:49:51 PM PDT 24
Peak memory 215588 kb
Host smart-fc578115-95e6-435d-a0cc-cc9e39cc426f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309239466 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.1309239466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1386211750
Short name T736
Test name
Test status
Simulation time 966565283 ps
CPU time 4.61 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:49:58 PM PDT 24
Peak memory 215740 kb
Host smart-e586485d-0cf6-4b5a-aeca-84d8a4288ab4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386211750 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1386211750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1668765318
Short name T402
Test name
Test status
Simulation time 127980302186 ps
CPU time 1876.29 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:21:06 PM PDT 24
Peak memory 379412 kb
Host smart-7fa0d095-b624-4a83-9e11-834ad01a75fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1668765318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1668765318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3906312370
Short name T1032
Test name
Test status
Simulation time 18806129249 ps
CPU time 1427.95 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 06:13:45 PM PDT 24
Peak memory 386852 kb
Host smart-d9e77110-ac7a-4726-b73f-7bf8510aa84b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3906312370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3906312370 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.2283045132
Short name T1027
Test name
Test status
Simulation time 101986125426 ps
CPU time 1115.03 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:08:23 PM PDT 24
Peak memory 327644 kb
Host smart-acf89485-e711-43c8-93aa-0fe1da2e4d35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2283045132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2283045132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.3065804423
Short name T666
Test name
Test status
Simulation time 85407414077 ps
CPU time 900.47 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 06:04:56 PM PDT 24
Peak memory 296824 kb
Host smart-42b6d51c-3bbe-4bc4-95a6-3699afde141f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3065804423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.3065804423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.996439327
Short name T998
Test name
Test status
Simulation time 346768666162 ps
CPU time 4608.13 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 07:06:42 PM PDT 24
Peak memory 638336 kb
Host smart-8afbf6a8-65a1-4b03-8e43-db2a523d1f67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=996439327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.996439327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.2730257309
Short name T332
Test name
Test status
Simulation time 862056031490 ps
CPU time 4566.75 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 07:06:00 PM PDT 24
Peak memory 556860 kb
Host smart-902a3d7c-e6e4-4ee5-94f0-45e5d236341b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2730257309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2730257309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.1926164829
Short name T20
Test name
Test status
Simulation time 13031189 ps
CPU time 0.77 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:50:07 PM PDT 24
Peak memory 205340 kb
Host smart-53c589c6-b6ad-4bd0-9a77-ba119808ffd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926164829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1926164829 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.1212806570
Short name T792
Test name
Test status
Simulation time 2618396844 ps
CPU time 72.27 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:50:59 PM PDT 24
Peak memory 227676 kb
Host smart-de933e12-f30d-43c1-b14b-9a631e44fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212806570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1212806570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.2394298253
Short name T979
Test name
Test status
Simulation time 19036912139 ps
CPU time 403.25 seconds
Started Jul 09 05:50:02 PM PDT 24
Finished Jul 09 05:56:46 PM PDT 24
Peak memory 229712 kb
Host smart-0d6bd1ce-eee7-4442-9b9c-526885ee8c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394298253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2394298253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.3393918271
Short name T1
Test name
Test status
Simulation time 260661377 ps
CPU time 7.36 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:49:55 PM PDT 24
Peak memory 223676 kb
Host smart-7682c08e-2601-4c53-b499-f96ba8644695
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3393918271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3393918271 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.1109113432
Short name T226
Test name
Test status
Simulation time 3375028279 ps
CPU time 38.13 seconds
Started Jul 09 05:50:03 PM PDT 24
Finished Jul 09 05:50:41 PM PDT 24
Peak memory 222128 kb
Host smart-aae4cdd8-054b-49b5-8b63-9dfa2936ef0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109113432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1109113432 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.813246824
Short name T393
Test name
Test status
Simulation time 5034114931 ps
CPU time 94.13 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 05:51:40 PM PDT 24
Peak memory 228676 kb
Host smart-cbd7b682-ed23-4bbc-9e52-69c5554efffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813246824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.813246824 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2238080077
Short name T485
Test name
Test status
Simulation time 48362650264 ps
CPU time 244.01 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:54:11 PM PDT 24
Peak memory 248500 kb
Host smart-5126c9b2-82ab-4955-bdce-176baab3ccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238080077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2238080077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.1116757144
Short name T741
Test name
Test status
Simulation time 1725827103 ps
CPU time 8.23 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 05:50:02 PM PDT 24
Peak memory 207416 kb
Host smart-953f0665-5f60-459b-974b-32a260d59e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116757144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1116757144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.242966214
Short name T751
Test name
Test status
Simulation time 468913429202 ps
CPU time 2586.85 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 06:33:00 PM PDT 24
Peak memory 435728 kb
Host smart-034c9310-c54a-4dfc-bc83-7ad425f15dce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242966214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.242966214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.2866371073
Short name T327
Test name
Test status
Simulation time 10844960161 ps
CPU time 133.29 seconds
Started Jul 09 05:50:02 PM PDT 24
Finished Jul 09 05:52:16 PM PDT 24
Peak memory 229396 kb
Host smart-1d3ad5f8-d493-4890-b9dd-447aa7e20d9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866371073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2866371073 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.2476425471
Short name T924
Test name
Test status
Simulation time 8249147404 ps
CPU time 49.34 seconds
Started Jul 09 05:50:10 PM PDT 24
Finished Jul 09 05:51:00 PM PDT 24
Peak memory 218676 kb
Host smart-41cf0ec4-9389-4cd9-b0a4-1b9dbaff70cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476425471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2476425471 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.1523806554
Short name T246
Test name
Test status
Simulation time 2342028525 ps
CPU time 82.32 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:51:15 PM PDT 24
Peak memory 237236 kb
Host smart-544709f2-1e54-40fb-810b-60a8ba9b5f6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1523806554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1523806554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.4270559317
Short name T961
Test name
Test status
Simulation time 238349019 ps
CPU time 4.39 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 05:50:12 PM PDT 24
Peak memory 215720 kb
Host smart-0ccdc9f6-2735-4d94-8589-3b954b00bdf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270559317 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.4270559317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3402534418
Short name T970
Test name
Test status
Simulation time 187895159 ps
CPU time 4.76 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:49:54 PM PDT 24
Peak memory 215656 kb
Host smart-f7f52394-4c74-4b39-91a9-608bca2a3fc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402534418 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3402534418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.1180418751
Short name T850
Test name
Test status
Simulation time 264451455796 ps
CPU time 1906.51 seconds
Started Jul 09 05:50:01 PM PDT 24
Finished Jul 09 06:21:48 PM PDT 24
Peak memory 376248 kb
Host smart-21cdf21d-d281-407b-8cb6-bdce07064dd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1180418751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1180418751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.3957806760
Short name T1066
Test name
Test status
Simulation time 61762504421 ps
CPU time 1805.69 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 06:20:11 PM PDT 24
Peak memory 370728 kb
Host smart-7b08540f-5a61-42cf-882b-18186b20c1fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3957806760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.3957806760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3453932021
Short name T375
Test name
Test status
Simulation time 197122219554 ps
CPU time 1330.32 seconds
Started Jul 09 05:49:58 PM PDT 24
Finished Jul 09 06:12:09 PM PDT 24
Peak memory 337088 kb
Host smart-0cf87b4f-b2c3-4224-b6a1-f6d5818d1f76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3453932021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3453932021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.1484606684
Short name T274
Test name
Test status
Simulation time 60161736532 ps
CPU time 916.3 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 06:05:13 PM PDT 24
Peak memory 296820 kb
Host smart-ec1365db-a7dc-4610-8348-bf122b72d34b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1484606684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.1484606684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.1043743689
Short name T864
Test name
Test status
Simulation time 193561278124 ps
CPU time 4058.37 seconds
Started Jul 09 05:50:01 PM PDT 24
Finished Jul 09 06:57:40 PM PDT 24
Peak memory 640092 kb
Host smart-b96bd5c6-905d-4fb9-913d-3097f81d736a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1043743689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.1043743689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.3748446071
Short name T714
Test name
Test status
Simulation time 1205712354386 ps
CPU time 3604.88 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 06:50:00 PM PDT 24
Peak memory 557740 kb
Host smart-7c11df8a-6b3f-4e9a-b5c5-24b47b7342e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3748446071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3748446071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.711565341
Short name T747
Test name
Test status
Simulation time 13199018 ps
CPU time 0.74 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:50:07 PM PDT 24
Peak memory 205284 kb
Host smart-0ace9892-7c6b-4feb-ad2d-ae07b78a4020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711565341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.711565341 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.425718502
Short name T920
Test name
Test status
Simulation time 100712387147 ps
CPU time 294.11 seconds
Started Jul 09 05:50:12 PM PDT 24
Finished Jul 09 05:55:07 PM PDT 24
Peak memory 245432 kb
Host smart-81b52803-3b4b-431c-9dd2-052cca26da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425718502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.425718502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.2015397478
Short name T301
Test name
Test status
Simulation time 701859792 ps
CPU time 51.58 seconds
Started Jul 09 05:50:11 PM PDT 24
Finished Jul 09 05:51:03 PM PDT 24
Peak memory 223864 kb
Host smart-581856c6-dd0a-4bfb-b5f2-0fa4553bf1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015397478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2015397478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.834663007
Short name T846
Test name
Test status
Simulation time 1201383252 ps
CPU time 22.91 seconds
Started Jul 09 05:50:12 PM PDT 24
Finished Jul 09 05:50:35 PM PDT 24
Peak memory 219000 kb
Host smart-b94ffb4e-8659-40e7-9676-023e7e78d50d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=834663007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.834663007 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.375346610
Short name T437
Test name
Test status
Simulation time 310510499 ps
CPU time 20.91 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:50:27 PM PDT 24
Peak memory 219928 kb
Host smart-5c51e7d4-84b7-464a-b7f8-97c364989aef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=375346610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.375346610 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.243833182
Short name T560
Test name
Test status
Simulation time 9961249539 ps
CPU time 90.51 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:51:37 PM PDT 24
Peak memory 229380 kb
Host smart-ac40735b-3e1e-4cff-9cba-5e7196684416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243833182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.243833182 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.3011839788
Short name T71
Test name
Test status
Simulation time 3120019214 ps
CPU time 85.38 seconds
Started Jul 09 05:50:10 PM PDT 24
Finished Jul 09 05:51:36 PM PDT 24
Peak memory 234812 kb
Host smart-0e0ec553-0e6b-47bc-8e99-3a8ec76f7443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011839788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3011839788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.481076331
Short name T60
Test name
Test status
Simulation time 485006830 ps
CPU time 1.32 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 05:50:07 PM PDT 24
Peak memory 207016 kb
Host smart-192a9c3b-7b22-420e-a3f7-577856f9c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481076331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.481076331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.2955357387
Short name T580
Test name
Test status
Simulation time 67297771 ps
CPU time 1.36 seconds
Started Jul 09 05:50:02 PM PDT 24
Finished Jul 09 05:50:04 PM PDT 24
Peak memory 215908 kb
Host smart-957041a2-dbdd-4dc2-b200-823e70ef9172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955357387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2955357387 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.1632630160
Short name T191
Test name
Test status
Simulation time 1503309983100 ps
CPU time 2008.89 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 06:23:30 PM PDT 24
Peak memory 402756 kb
Host smart-36122b37-11cc-42c7-968a-9215c5d6e854
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632630160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.1632630160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.1141779152
Short name T292
Test name
Test status
Simulation time 4288575407 ps
CPU time 78.72 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 05:51:24 PM PDT 24
Peak memory 226212 kb
Host smart-16767f8f-6cd3-4e7b-b7b5-047762acfc0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141779152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1141779152 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.3463801742
Short name T828
Test name
Test status
Simulation time 2313454811 ps
CPU time 46.53 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 05:50:52 PM PDT 24
Peak memory 216720 kb
Host smart-da9ba368-77ab-452b-8981-e3a196c3e669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463801742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3463801742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.348958962
Short name T507
Test name
Test status
Simulation time 56139799864 ps
CPU time 1352.27 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 06:12:41 PM PDT 24
Peak memory 375956 kb
Host smart-d5276888-1082-4e2c-92f8-9258a35689b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=348958962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.348958962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.4190284288
Short name T720
Test name
Test status
Simulation time 363826164 ps
CPU time 5.23 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 05:50:10 PM PDT 24
Peak memory 215656 kb
Host smart-41d0a027-b1eb-422b-9526-d4cc78b807b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190284288 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.4190284288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.2889329401
Short name T861
Test name
Test status
Simulation time 259656441 ps
CPU time 3.97 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 05:49:58 PM PDT 24
Peak memory 215652 kb
Host smart-ecc5e1f6-3fad-477e-9226-78c05fb5399b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889329401 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.2889329401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.2365743260
Short name T568
Test name
Test status
Simulation time 79266616844 ps
CPU time 1654.44 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 06:17:29 PM PDT 24
Peak memory 396016 kb
Host smart-e5596b48-0deb-4d7e-965a-4af33a4da12a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2365743260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2365743260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.3190941822
Short name T214
Test name
Test status
Simulation time 333054345399 ps
CPU time 1734.97 seconds
Started Jul 09 05:50:11 PM PDT 24
Finished Jul 09 06:19:07 PM PDT 24
Peak memory 376948 kb
Host smart-4379f93c-5048-4184-9283-bb8217035a46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3190941822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.3190941822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1581170399
Short name T588
Test name
Test status
Simulation time 192197654174 ps
CPU time 1329.53 seconds
Started Jul 09 05:50:01 PM PDT 24
Finished Jul 09 06:12:11 PM PDT 24
Peak memory 330724 kb
Host smart-02282b32-ef85-4acf-858d-8f1bf763a894
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1581170399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1581170399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.2620634548
Short name T363
Test name
Test status
Simulation time 205433122445 ps
CPU time 981.65 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 06:06:29 PM PDT 24
Peak memory 296828 kb
Host smart-eb978ebf-81b8-4eaa-a5b1-ce7086fc1e40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2620634548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.2620634548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.3235826015
Short name T89
Test name
Test status
Simulation time 187289197824 ps
CPU time 3849.97 seconds
Started Jul 09 05:50:08 PM PDT 24
Finished Jul 09 06:54:19 PM PDT 24
Peak memory 642228 kb
Host smart-f175db79-a994-433c-9ead-42a809dd5da4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3235826015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3235826015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.2868747127
Short name T208
Test name
Test status
Simulation time 178920848497 ps
CPU time 3207.36 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 06:43:22 PM PDT 24
Peak memory 555620 kb
Host smart-475e2d0c-d892-4b79-a37e-d35827a9b391
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2868747127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2868747127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.21428903
Short name T603
Test name
Test status
Simulation time 44922451 ps
CPU time 0.73 seconds
Started Jul 09 05:50:10 PM PDT 24
Finished Jul 09 05:50:11 PM PDT 24
Peak memory 205296 kb
Host smart-f0ce141e-f686-4081-a8df-f61d886aad40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21428903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.21428903 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.76611913
Short name T674
Test name
Test status
Simulation time 2622333803 ps
CPU time 116.74 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 05:51:57 PM PDT 24
Peak memory 233244 kb
Host smart-bc9c589c-2911-475f-9a35-7cbd2d1c0df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76611913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.76611913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.3330891916
Short name T569
Test name
Test status
Simulation time 30223755159 ps
CPU time 514.41 seconds
Started Jul 09 05:50:17 PM PDT 24
Finished Jul 09 05:58:52 PM PDT 24
Peak memory 231800 kb
Host smart-51c82bfa-48ce-4741-b48d-f14eca8144f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330891916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.3330891916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1390910686
Short name T794
Test name
Test status
Simulation time 1036731108 ps
CPU time 19.02 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 05:50:27 PM PDT 24
Peak memory 219424 kb
Host smart-c0c4c3a3-761d-4574-a48d-53f5b9545adc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1390910686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1390910686 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.590740414
Short name T592
Test name
Test status
Simulation time 2780395980 ps
CPU time 16.89 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 05:50:23 PM PDT 24
Peak memory 223776 kb
Host smart-059f300a-cf97-4000-8ad6-dc8421202d03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=590740414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.590740414 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.3719020286
Short name T443
Test name
Test status
Simulation time 2853467299 ps
CPU time 71.09 seconds
Started Jul 09 05:50:05 PM PDT 24
Finished Jul 09 05:51:17 PM PDT 24
Peak memory 226480 kb
Host smart-7b39a6b7-765b-4fee-a556-2f19722f009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719020286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3719020286 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.1361178859
Short name T32
Test name
Test status
Simulation time 16819451323 ps
CPU time 217.05 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 05:53:42 PM PDT 24
Peak memory 256372 kb
Host smart-46386137-af6a-45bd-9027-8dc16fe42643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361178859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1361178859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.2607348905
Short name T648
Test name
Test status
Simulation time 697923143 ps
CPU time 2.44 seconds
Started Jul 09 05:50:08 PM PDT 24
Finished Jul 09 05:50:11 PM PDT 24
Peak memory 207392 kb
Host smart-8cd066f8-1dd1-4b5d-9bc2-6ba2157f5bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607348905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2607348905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2662077831
Short name T7
Test name
Test status
Simulation time 59683008 ps
CPU time 1.46 seconds
Started Jul 09 05:50:08 PM PDT 24
Finished Jul 09 05:50:10 PM PDT 24
Peak memory 215652 kb
Host smart-e91664d4-e9c6-4463-b516-40ae06b90e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662077831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2662077831 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1468229100
Short name T1030
Test name
Test status
Simulation time 60627174769 ps
CPU time 1260.2 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 06:11:05 PM PDT 24
Peak memory 330372 kb
Host smart-cd7b7ef9-712e-4b2f-92e3-02b5bcd7a6d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468229100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1468229100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.4058509180
Short name T461
Test name
Test status
Simulation time 4800717999 ps
CPU time 413.67 seconds
Started Jul 09 05:50:10 PM PDT 24
Finished Jul 09 05:57:05 PM PDT 24
Peak memory 249976 kb
Host smart-28ef4741-4aa5-4f50-b7f8-5c24ea1a8ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058509180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.4058509180 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.4068891702
Short name T956
Test name
Test status
Simulation time 2455582139 ps
CPU time 50.97 seconds
Started Jul 09 05:50:09 PM PDT 24
Finished Jul 09 05:51:01 PM PDT 24
Peak memory 215708 kb
Host smart-3107bb6a-7c31-4105-a2be-f758c4cc656f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068891702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.4068891702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.323295848
Short name T690
Test name
Test status
Simulation time 9168875048 ps
CPU time 321.25 seconds
Started Jul 09 05:50:10 PM PDT 24
Finished Jul 09 05:55:32 PM PDT 24
Peak memory 282132 kb
Host smart-b20d6962-f477-4bf6-8ca6-09ab6c3de065
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=323295848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.323295848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1132504110
Short name T499
Test name
Test status
Simulation time 232367349 ps
CPU time 4.18 seconds
Started Jul 09 05:50:09 PM PDT 24
Finished Jul 09 05:50:14 PM PDT 24
Peak memory 215696 kb
Host smart-beb9db72-0c1f-4f7f-b74f-29ba40ce324a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132504110 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1132504110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3025032379
Short name T291
Test name
Test status
Simulation time 179569363 ps
CPU time 4.58 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:50:12 PM PDT 24
Peak memory 215652 kb
Host smart-30a27c6a-3ac8-42c9-b702-d52303e83395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025032379 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3025032379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.3724888014
Short name T278
Test name
Test status
Simulation time 37060751448 ps
CPU time 1536.54 seconds
Started Jul 09 05:50:10 PM PDT 24
Finished Jul 09 06:15:48 PM PDT 24
Peak memory 378004 kb
Host smart-d5812b4a-007d-4e57-ab9b-5fdfb052e00a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3724888014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.3724888014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.4185480764
Short name T882
Test name
Test status
Simulation time 249126330508 ps
CPU time 1699.52 seconds
Started Jul 09 05:50:13 PM PDT 24
Finished Jul 09 06:18:33 PM PDT 24
Peak memory 366104 kb
Host smart-297dd5d2-c374-4924-ab26-f97deeefdeae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4185480764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.4185480764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.4262504889
Short name T276
Test name
Test status
Simulation time 54732470672 ps
CPU time 1060.19 seconds
Started Jul 09 05:50:09 PM PDT 24
Finished Jul 09 06:07:50 PM PDT 24
Peak memory 335568 kb
Host smart-b6e95830-f5ae-4743-954c-6a705926a792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4262504889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.4262504889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2712148751
Short name T672
Test name
Test status
Simulation time 42890936744 ps
CPU time 859.82 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 06:04:27 PM PDT 24
Peak memory 291780 kb
Host smart-972da95d-29db-4141-8805-4a23dcbd47ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2712148751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2712148751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.4079299634
Short name T326
Test name
Test status
Simulation time 51135294863 ps
CPU time 4202.87 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 655104 kb
Host smart-823e9eeb-0abd-4e17-afe8-95ad3ab0a6cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4079299634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.4079299634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.956103231
Short name T933
Test name
Test status
Simulation time 309794182573 ps
CPU time 3629.32 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 06:50:34 PM PDT 24
Peak memory 563188 kb
Host smart-683e770a-4a42-4365-ba9a-9baec0a0f615
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=956103231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.956103231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2947219984
Short name T352
Test name
Test status
Simulation time 42429240 ps
CPU time 0.75 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 05:50:08 PM PDT 24
Peak memory 205364 kb
Host smart-4357c90c-4dff-4c3f-8d74-20d1e1e36540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947219984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2947219984 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.3926718899
Short name T1017
Test name
Test status
Simulation time 4676141333 ps
CPU time 242.82 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:54:10 PM PDT 24
Peak memory 246220 kb
Host smart-f84de32f-4728-4d95-844b-1e561dbde25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926718899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3926718899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2993529778
Short name T253
Test name
Test status
Simulation time 6411271413 ps
CPU time 38.16 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 05:50:45 PM PDT 24
Peak memory 219956 kb
Host smart-062e261b-a444-44ea-9a2b-4c79b9485aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993529778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2993529778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.64500433
Short name T695
Test name
Test status
Simulation time 1663719004 ps
CPU time 30.45 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 05:50:46 PM PDT 24
Peak memory 220612 kb
Host smart-2bdeae40-f131-48ed-bb0e-bb80e48ce0d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=64500433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.64500433 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.544193767
Short name T175
Test name
Test status
Simulation time 113492170 ps
CPU time 7.2 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 05:50:15 PM PDT 24
Peak memory 216576 kb
Host smart-d2e86af9-9dd1-4f9f-848a-295a66ab2dbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=544193767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.544193767 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.3314251432
Short name T479
Test name
Test status
Simulation time 8020876915 ps
CPU time 161.78 seconds
Started Jul 09 05:50:11 PM PDT 24
Finished Jul 09 05:52:54 PM PDT 24
Peak memory 235564 kb
Host smart-4b6dd677-6141-4252-b761-635df5b5ccd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314251432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3314251432 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.2267575087
Short name T803
Test name
Test status
Simulation time 31253035385 ps
CPU time 216.23 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 05:53:41 PM PDT 24
Peak memory 253700 kb
Host smart-c8547594-27d2-4381-acdb-5b9a2fd27ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267575087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2267575087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.1782548882
Short name T888
Test name
Test status
Simulation time 2230897418 ps
CPU time 5.74 seconds
Started Jul 09 05:50:08 PM PDT 24
Finished Jul 09 05:50:15 PM PDT 24
Peak memory 207396 kb
Host smart-f6c5aeb7-8e17-4856-b4b7-9170015f6425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782548882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1782548882 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2335281239
Short name T497
Test name
Test status
Simulation time 143242317 ps
CPU time 1.17 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 05:50:18 PM PDT 24
Peak memory 215596 kb
Host smart-03e193ef-9a52-4529-8b9b-c40177f276db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335281239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2335281239 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3847680843
Short name T966
Test name
Test status
Simulation time 187823725822 ps
CPU time 1333.24 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 06:12:21 PM PDT 24
Peak memory 352632 kb
Host smart-ce8db3a0-a212-44fb-98a0-2d513adff1ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847680843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3847680843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.1908650952
Short name T642
Test name
Test status
Simulation time 10568470476 ps
CPU time 177.9 seconds
Started Jul 09 05:50:11 PM PDT 24
Finished Jul 09 05:53:10 PM PDT 24
Peak memory 237880 kb
Host smart-a7f61b74-176e-4e7a-b73a-0096f6cf526d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908650952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1908650952 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.3653398002
Short name T262
Test name
Test status
Simulation time 1563400150 ps
CPU time 26.79 seconds
Started Jul 09 05:50:13 PM PDT 24
Finished Jul 09 05:50:40 PM PDT 24
Peak memory 218916 kb
Host smart-a5e0bdf9-103e-4a56-9968-d87e3695cccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653398002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3653398002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.1666730921
Short name T1023
Test name
Test status
Simulation time 2446268995 ps
CPU time 44.18 seconds
Started Jul 09 05:50:12 PM PDT 24
Finished Jul 09 05:50:57 PM PDT 24
Peak memory 223884 kb
Host smart-6e482389-c578-4c48-8e93-c11d30f31e3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1666730921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1666730921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.814366723
Short name T564
Test name
Test status
Simulation time 1148688122 ps
CPU time 4.61 seconds
Started Jul 09 05:50:08 PM PDT 24
Finished Jul 09 05:50:13 PM PDT 24
Peak memory 215700 kb
Host smart-6d75ccad-2f2a-485e-af4b-e0f656783166
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814366723 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.kmac_test_vectors_kmac.814366723 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.1233391960
Short name T734
Test name
Test status
Simulation time 166367665 ps
CPU time 3.85 seconds
Started Jul 09 05:50:08 PM PDT 24
Finished Jul 09 05:50:12 PM PDT 24
Peak memory 215604 kb
Host smart-ff1feed1-f612-4848-a981-d6e7ebe439ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233391960 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.1233391960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.2574853149
Short name T187
Test name
Test status
Simulation time 99552458255 ps
CPU time 2162.18 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 06:26:10 PM PDT 24
Peak memory 389932 kb
Host smart-7f5620a1-d72c-45f5-bdb8-ff4e9ac4fef8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2574853149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.2574853149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.401122506
Short name T949
Test name
Test status
Simulation time 373804806382 ps
CPU time 1761.04 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 06:19:26 PM PDT 24
Peak memory 367332 kb
Host smart-f8b1f38c-0514-478a-b65a-32d38a5d5f42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=401122506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.401122506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.3524094357
Short name T493
Test name
Test status
Simulation time 95231470677 ps
CPU time 1344.83 seconds
Started Jul 09 05:50:13 PM PDT 24
Finished Jul 09 06:12:38 PM PDT 24
Peak memory 327852 kb
Host smart-ea335c92-6bb5-4660-999a-0690d828269e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3524094357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.3524094357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.2168883840
Short name T376
Test name
Test status
Simulation time 40340021765 ps
CPU time 775.73 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 06:03:03 PM PDT 24
Peak memory 288304 kb
Host smart-beabb561-5f24-4bd1-b660-9fed829e8123
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2168883840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.2168883840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.438561086
Short name T972
Test name
Test status
Simulation time 930849152095 ps
CPU time 4707.19 seconds
Started Jul 09 05:50:06 PM PDT 24
Finished Jul 09 07:08:34 PM PDT 24
Peak memory 653288 kb
Host smart-1642d5e1-ce02-42e6-9c81-0eb40d350eda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=438561086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.438561086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.3369561666
Short name T176
Test name
Test status
Simulation time 45431611857 ps
CPU time 3423.38 seconds
Started Jul 09 05:50:07 PM PDT 24
Finished Jul 09 06:47:11 PM PDT 24
Peak memory 568676 kb
Host smart-492fc75e-6f5e-4ab9-9f4e-5b4e2e510a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3369561666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.3369561666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.2481169233
Short name T543
Test name
Test status
Simulation time 49931008 ps
CPU time 0.77 seconds
Started Jul 09 05:50:14 PM PDT 24
Finished Jul 09 05:50:15 PM PDT 24
Peak memory 205316 kb
Host smart-bc25d833-f880-44b6-b6ab-ea56e6beb6d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481169233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2481169233 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.300931935
Short name T523
Test name
Test status
Simulation time 1382202754 ps
CPU time 49.25 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:51:13 PM PDT 24
Peak memory 224024 kb
Host smart-be721ab6-b2fc-4741-a26d-68e736d10102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300931935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.300931935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.1753872212
Short name T604
Test name
Test status
Simulation time 17980224451 ps
CPU time 419.89 seconds
Started Jul 09 05:50:15 PM PDT 24
Finished Jul 09 05:57:15 PM PDT 24
Peak memory 230708 kb
Host smart-570c917e-a10f-4e03-b315-83edb7ed41e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753872212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1753872212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.81664713
Short name T727
Test name
Test status
Simulation time 909989773 ps
CPU time 12.05 seconds
Started Jul 09 05:50:13 PM PDT 24
Finished Jul 09 05:50:26 PM PDT 24
Peak memory 215564 kb
Host smart-252e299b-d742-4daa-a580-446b113d4878
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81664713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.81664713 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.2102686743
Short name T977
Test name
Test status
Simulation time 1038607904 ps
CPU time 6.15 seconds
Started Jul 09 05:50:18 PM PDT 24
Finished Jul 09 05:50:25 PM PDT 24
Peak memory 219036 kb
Host smart-1ab11835-5e43-4028-b19d-f9e36976a266
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2102686743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2102686743 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.4040770589
Short name T304
Test name
Test status
Simulation time 14932347497 ps
CPU time 287.99 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 05:55:04 PM PDT 24
Peak memory 242044 kb
Host smart-d7fd4660-14fd-44b3-837f-c86e26a85295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040770589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.4040770589 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.3749380206
Short name T988
Test name
Test status
Simulation time 2042782527 ps
CPU time 156.79 seconds
Started Jul 09 05:50:12 PM PDT 24
Finished Jul 09 05:52:49 PM PDT 24
Peak memory 249168 kb
Host smart-8478afde-101b-49b8-a100-09000f8bfdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749380206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3749380206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.2011154558
Short name T718
Test name
Test status
Simulation time 278410785 ps
CPU time 1.31 seconds
Started Jul 09 05:50:20 PM PDT 24
Finished Jul 09 05:50:21 PM PDT 24
Peak memory 215580 kb
Host smart-234536ed-ccb8-442b-99bc-ba3e1ca63065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011154558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2011154558 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2529529927
Short name T308
Test name
Test status
Simulation time 37734659868 ps
CPU time 1045.23 seconds
Started Jul 09 05:50:11 PM PDT 24
Finished Jul 09 06:07:37 PM PDT 24
Peak memory 320396 kb
Host smart-5b51e40f-d8a9-4d79-bd2e-242206293f21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529529927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2529529927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.235852085
Short name T436
Test name
Test status
Simulation time 1083671738 ps
CPU time 55.7 seconds
Started Jul 09 05:50:12 PM PDT 24
Finished Jul 09 05:51:09 PM PDT 24
Peak memory 223884 kb
Host smart-2890dfa5-1c95-48fe-84d9-422f73c4c775
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235852085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.235852085 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.1512241646
Short name T531
Test name
Test status
Simulation time 771010946 ps
CPU time 4.73 seconds
Started Jul 09 05:50:12 PM PDT 24
Finished Jul 09 05:50:17 PM PDT 24
Peak memory 216676 kb
Host smart-83d3ce57-0b1a-4cdf-971b-cc9bd7ca8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512241646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1512241646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.631726903
Short name T831
Test name
Test status
Simulation time 248303601427 ps
CPU time 1472.68 seconds
Started Jul 09 05:50:14 PM PDT 24
Finished Jul 09 06:14:47 PM PDT 24
Peak memory 371520 kb
Host smart-85e118d1-7f1d-41ea-96b9-02d6a523c682
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=631726903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.631726903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.3254531843
Short name T341
Test name
Test status
Simulation time 124377377 ps
CPU time 3.85 seconds
Started Jul 09 05:50:14 PM PDT 24
Finished Jul 09 05:50:18 PM PDT 24
Peak memory 215616 kb
Host smart-0b204fa5-4ac5-48f3-b398-b4a2b769bc7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254531843 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.3254531843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.2827122546
Short name T675
Test name
Test status
Simulation time 295213262 ps
CPU time 4.08 seconds
Started Jul 09 05:50:19 PM PDT 24
Finished Jul 09 05:50:24 PM PDT 24
Peak memory 215640 kb
Host smart-c3f12975-1ab6-4798-aa80-1fdc3ff1a618
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827122546 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.2827122546 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.1352923384
Short name T964
Test name
Test status
Simulation time 208888425017 ps
CPU time 1459.3 seconds
Started Jul 09 05:50:15 PM PDT 24
Finished Jul 09 06:14:35 PM PDT 24
Peak memory 391108 kb
Host smart-5835c827-ec55-467a-90fb-f0e51eb3f3ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1352923384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1352923384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3789774184
Short name T708
Test name
Test status
Simulation time 18507762721 ps
CPU time 1421.17 seconds
Started Jul 09 05:50:09 PM PDT 24
Finished Jul 09 06:13:50 PM PDT 24
Peak memory 374012 kb
Host smart-29c69cdb-972a-4f61-8450-1847f3f21847
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3789774184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3789774184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.2408535880
Short name T503
Test name
Test status
Simulation time 242262441130 ps
CPU time 1234.77 seconds
Started Jul 09 05:50:15 PM PDT 24
Finished Jul 09 06:10:50 PM PDT 24
Peak memory 333712 kb
Host smart-68ffb7db-c054-4088-a336-70c2a3507bc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2408535880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.2408535880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.1389215782
Short name T282
Test name
Test status
Simulation time 197517922601 ps
CPU time 1063.75 seconds
Started Jul 09 05:50:11 PM PDT 24
Finished Jul 09 06:07:55 PM PDT 24
Peak memory 297320 kb
Host smart-37e11450-5218-4d40-b683-df14035651ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1389215782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1389215782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.3920961993
Short name T896
Test name
Test status
Simulation time 1400653444877 ps
CPU time 4850.97 seconds
Started Jul 09 05:50:10 PM PDT 24
Finished Jul 09 07:11:02 PM PDT 24
Peak memory 656248 kb
Host smart-a5b59a4b-4150-4306-a4d2-26682a97ef76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3920961993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3920961993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.3105939647
Short name T586
Test name
Test status
Simulation time 52929371723 ps
CPU time 3404.59 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 06:47:01 PM PDT 24
Peak memory 552592 kb
Host smart-8342a82b-a06a-4633-a0dc-afcc5e846c74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3105939647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3105939647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2077923266
Short name T655
Test name
Test status
Simulation time 42176904 ps
CPU time 0.75 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:50:25 PM PDT 24
Peak memory 205356 kb
Host smart-c145728c-8cd3-40ad-b00e-79661975de4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077923266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2077923266 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.804121846
Short name T610
Test name
Test status
Simulation time 4220092390 ps
CPU time 116.7 seconds
Started Jul 09 05:50:18 PM PDT 24
Finished Jul 09 05:52:15 PM PDT 24
Peak memory 234520 kb
Host smart-64f724b4-c8ee-485a-a65a-9e51e652f5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804121846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.804121846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.972328580
Short name T994
Test name
Test status
Simulation time 61387998277 ps
CPU time 411.9 seconds
Started Jul 09 05:50:17 PM PDT 24
Finished Jul 09 05:57:10 PM PDT 24
Peak memory 229324 kb
Host smart-a89bc6ed-6020-4576-bba3-15815f84fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972328580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.972328580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1203978394
Short name T795
Test name
Test status
Simulation time 3703148741 ps
CPU time 6 seconds
Started Jul 09 05:50:22 PM PDT 24
Finished Jul 09 05:50:28 PM PDT 24
Peak memory 223784 kb
Host smart-7ca976e1-d43f-4a79-85ea-862d83d79c21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1203978394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1203978394 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2271586900
Short name T654
Test name
Test status
Simulation time 4030829330 ps
CPU time 33.23 seconds
Started Jul 09 05:50:23 PM PDT 24
Finished Jul 09 05:50:56 PM PDT 24
Peak memory 223828 kb
Host smart-3af66a12-387f-4c32-9101-ae89cf13096d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2271586900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2271586900 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.2489918589
Short name T667
Test name
Test status
Simulation time 530704788 ps
CPU time 37.24 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:51:01 PM PDT 24
Peak memory 222104 kb
Host smart-244dfde0-fe5c-470f-bf91-16c0bbbe0068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489918589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2489918589 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.372707452
Short name T899
Test name
Test status
Simulation time 9552091965 ps
CPU time 181.58 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:53:26 PM PDT 24
Peak memory 240412 kb
Host smart-41ca98c1-1f55-4b32-b842-55cd3de14fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372707452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.372707452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.2965553655
Short name T643
Test name
Test status
Simulation time 2309141007 ps
CPU time 6.72 seconds
Started Jul 09 05:50:22 PM PDT 24
Finished Jul 09 05:50:29 PM PDT 24
Peak memory 207424 kb
Host smart-5f145aee-e973-4257-bce5-7d2bf6c1a867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965553655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2965553655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.4036537281
Short name T769
Test name
Test status
Simulation time 27485780 ps
CPU time 1.19 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 05:50:33 PM PDT 24
Peak memory 215696 kb
Host smart-93ff3b83-b697-49cb-86a6-c52b34857906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036537281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.4036537281 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2747336921
Short name T840
Test name
Test status
Simulation time 139390493993 ps
CPU time 2022.25 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 06:23:59 PM PDT 24
Peak memory 410176 kb
Host smart-39c8df22-246c-43cb-a532-ec2dd979800d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747336921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2747336921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.478828717
Short name T477
Test name
Test status
Simulation time 5475334139 ps
CPU time 355.14 seconds
Started Jul 09 05:50:18 PM PDT 24
Finished Jul 09 05:56:13 PM PDT 24
Peak memory 252544 kb
Host smart-8e53f4cd-e6ae-42d5-aa80-1ef7a7e747c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478828717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.478828717 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.1654241761
Short name T533
Test name
Test status
Simulation time 1912355257 ps
CPU time 38.98 seconds
Started Jul 09 05:50:13 PM PDT 24
Finished Jul 09 05:50:53 PM PDT 24
Peak memory 217960 kb
Host smart-fa862c46-6882-4f6e-a6d0-e9951cd6bc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654241761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1654241761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.1184483650
Short name T26
Test name
Test status
Simulation time 18877680153 ps
CPU time 466.55 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:58:11 PM PDT 24
Peak memory 297868 kb
Host smart-948eff75-406f-4b54-ad2e-360831b95282
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1184483650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1184483650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.2876551752
Short name T385
Test name
Test status
Simulation time 240145944 ps
CPU time 4.68 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:50:29 PM PDT 24
Peak memory 215652 kb
Host smart-10f6977a-4b4c-4981-8600-eb798181b22d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876551752 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.2876551752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.390828969
Short name T358
Test name
Test status
Simulation time 99070135 ps
CPU time 4.01 seconds
Started Jul 09 05:50:18 PM PDT 24
Finished Jul 09 05:50:22 PM PDT 24
Peak memory 215672 kb
Host smart-5cae4356-845a-46d5-8559-6c9893f74bef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390828969 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.390828969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.798694894
Short name T298
Test name
Test status
Simulation time 76357227895 ps
CPU time 1400.86 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 06:13:38 PM PDT 24
Peak memory 374196 kb
Host smart-a2534390-1b88-4759-a7ef-079602265fd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=798694894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.798694894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.1009376029
Short name T239
Test name
Test status
Simulation time 73849905726 ps
CPU time 1419.1 seconds
Started Jul 09 05:50:19 PM PDT 24
Finished Jul 09 06:13:58 PM PDT 24
Peak memory 374040 kb
Host smart-78df0d77-3026-48e8-87d6-78f62f237cf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1009376029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1009376029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.967018805
Short name T380
Test name
Test status
Simulation time 13612770137 ps
CPU time 1069.02 seconds
Started Jul 09 05:50:17 PM PDT 24
Finished Jul 09 06:08:07 PM PDT 24
Peak memory 331480 kb
Host smart-86c11cc3-a454-4cca-8894-60c6f7bbf0a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=967018805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.967018805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1607286138
Short name T404
Test name
Test status
Simulation time 65700571882 ps
CPU time 899.66 seconds
Started Jul 09 05:50:16 PM PDT 24
Finished Jul 09 06:05:16 PM PDT 24
Peak memory 295716 kb
Host smart-80439689-6c93-4972-8305-0286fb1b04fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1607286138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1607286138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.1179936684
Short name T417
Test name
Test status
Simulation time 741285772213 ps
CPU time 4609.61 seconds
Started Jul 09 05:50:18 PM PDT 24
Finished Jul 09 07:07:09 PM PDT 24
Peak memory 641236 kb
Host smart-1c41756b-3cdd-477c-8dfe-534b16174df7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1179936684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.1179936684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.3616906136
Short name T737
Test name
Test status
Simulation time 148859009973 ps
CPU time 3821.59 seconds
Started Jul 09 05:50:19 PM PDT 24
Finished Jul 09 06:54:01 PM PDT 24
Peak memory 554720 kb
Host smart-6c1f58bd-1db3-4070-96f8-975b132c2fa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3616906136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.3616906136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2746840472
Short name T181
Test name
Test status
Simulation time 18510982 ps
CPU time 0.75 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 05:50:34 PM PDT 24
Peak memory 205316 kb
Host smart-01c955e2-4ea6-4269-b4fa-ce8075c67ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746840472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2746840472 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3983273818
Short name T381
Test name
Test status
Simulation time 3445598734 ps
CPU time 209.35 seconds
Started Jul 09 05:50:25 PM PDT 24
Finished Jul 09 05:53:55 PM PDT 24
Peak memory 242800 kb
Host smart-bc0e00b9-6cb4-4759-b166-7951e8ee766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983273818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3983273818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2871231179
Short name T296
Test name
Test status
Simulation time 30298014654 ps
CPU time 689.73 seconds
Started Jul 09 05:50:23 PM PDT 24
Finished Jul 09 06:01:53 PM PDT 24
Peak memory 231752 kb
Host smart-670fdf12-ba31-4e04-831a-5b493d9455b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871231179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2871231179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.2014665996
Short name T73
Test name
Test status
Simulation time 1681135875 ps
CPU time 20.79 seconds
Started Jul 09 05:50:29 PM PDT 24
Finished Jul 09 05:50:50 PM PDT 24
Peak memory 219764 kb
Host smart-6ce7b547-5693-4c1b-aff3-f41fbb67df75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2014665996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2014665996 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.509040411
Short name T812
Test name
Test status
Simulation time 9866318519 ps
CPU time 48.72 seconds
Started Jul 09 05:50:26 PM PDT 24
Finished Jul 09 05:51:15 PM PDT 24
Peak memory 223764 kb
Host smart-4d1217b3-da6d-47df-8b8d-734702a61323
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=509040411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.509040411 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.1906233682
Short name T716
Test name
Test status
Simulation time 7431254703 ps
CPU time 164.57 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:53:10 PM PDT 24
Peak memory 235692 kb
Host smart-2fcfb9b0-fed1-4aa6-9be1-f2c25edd34aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906233682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1906233682 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.2217112018
Short name T423
Test name
Test status
Simulation time 6450726105 ps
CPU time 184.22 seconds
Started Jul 09 05:50:29 PM PDT 24
Finished Jul 09 05:53:34 PM PDT 24
Peak memory 256632 kb
Host smart-5426925e-b3ea-42e8-b1e9-00684afb0caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217112018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2217112018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.3156299172
Short name T316
Test name
Test status
Simulation time 5518510721 ps
CPU time 7.69 seconds
Started Jul 09 05:50:27 PM PDT 24
Finished Jul 09 05:50:35 PM PDT 24
Peak memory 207464 kb
Host smart-9849b29b-40fe-4cf6-b36c-b4d7bba49fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156299172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3156299172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.2711841804
Short name T799
Test name
Test status
Simulation time 223361770 ps
CPU time 4.08 seconds
Started Jul 09 05:50:28 PM PDT 24
Finished Jul 09 05:50:32 PM PDT 24
Peak memory 220060 kb
Host smart-160e6fba-529f-4e98-b65f-d15f50033f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711841804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2711841804 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.412547587
Short name T1041
Test name
Test status
Simulation time 53580221284 ps
CPU time 1477.42 seconds
Started Jul 09 05:50:25 PM PDT 24
Finished Jul 09 06:15:03 PM PDT 24
Peak memory 366960 kb
Host smart-07c543fb-e86c-4782-a77a-4db56e75e5c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412547587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_an
d_output.412547587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2812291378
Short name T772
Test name
Test status
Simulation time 3076633019 ps
CPU time 63.63 seconds
Started Jul 09 05:50:22 PM PDT 24
Finished Jul 09 05:51:26 PM PDT 24
Peak memory 223864 kb
Host smart-96120dee-dc4f-4ff6-ab46-fe08c3f568a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812291378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2812291378 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.1461599695
Short name T581
Test name
Test status
Simulation time 621524425 ps
CPU time 30.24 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 05:51:02 PM PDT 24
Peak memory 215984 kb
Host smart-2c7651cd-3457-4394-b2a8-071cc566a847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461599695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1461599695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.276283306
Short name T515
Test name
Test status
Simulation time 84988999076 ps
CPU time 532.59 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 05:59:26 PM PDT 24
Peak memory 314232 kb
Host smart-535c9361-3895-4259-8a7e-747d06de609f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=276283306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.276283306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.564838408
Short name T538
Test name
Test status
Simulation time 329285965 ps
CPU time 4.14 seconds
Started Jul 09 05:50:30 PM PDT 24
Finished Jul 09 05:50:35 PM PDT 24
Peak memory 215724 kb
Host smart-9a19e9df-b5e7-46e0-9d89-3d8482754756
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564838408 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.564838408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.4266431591
Short name T238
Test name
Test status
Simulation time 543464769 ps
CPU time 4.76 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 05:50:30 PM PDT 24
Peak memory 215756 kb
Host smart-31a215b9-a777-497e-9261-6a9d016204a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266431591 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.4266431591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.1529115384
Short name T869
Test name
Test status
Simulation time 66730095204 ps
CPU time 1864.98 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 06:21:40 PM PDT 24
Peak memory 402420 kb
Host smart-4c8570ae-56af-4010-bab7-e1a830ad180f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1529115384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.1529115384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.670019436
Short name T194
Test name
Test status
Simulation time 72209310754 ps
CPU time 1526.71 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 06:16:00 PM PDT 24
Peak memory 387672 kb
Host smart-262e2b39-38d5-4dc2-8470-edc61777ef6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=670019436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.670019436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.302424157
Short name T486
Test name
Test status
Simulation time 244124552943 ps
CPU time 1265.23 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 06:11:38 PM PDT 24
Peak memory 335572 kb
Host smart-2a009c01-e188-4dc6-acd8-f3a3a42f7ad3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=302424157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.302424157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.4126325189
Short name T197
Test name
Test status
Simulation time 34209265302 ps
CPU time 898.98 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 06:05:31 PM PDT 24
Peak memory 296200 kb
Host smart-9994916c-8de1-494f-b9d0-b4e9680a20ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4126325189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.4126325189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.2393288925
Short name T806
Test name
Test status
Simulation time 260788593778 ps
CPU time 5113.02 seconds
Started Jul 09 05:50:23 PM PDT 24
Finished Jul 09 07:15:37 PM PDT 24
Peak memory 656184 kb
Host smart-ca13cb86-81af-4d59-9082-e2bfe6eb4bce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2393288925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.2393288925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.425371217
Short name T480
Test name
Test status
Simulation time 584547008267 ps
CPU time 4146.34 seconds
Started Jul 09 05:50:30 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 564772 kb
Host smart-63a4b5e4-b592-4310-ab4a-348fc5b74e6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=425371217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.425371217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.462655772
Short name T1063
Test name
Test status
Simulation time 43498158 ps
CPU time 0.75 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 05:49:34 PM PDT 24
Peak memory 205332 kb
Host smart-27d06c44-09ca-47c2-8e60-c912d6819ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462655772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.462655772 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.2438918029
Short name T348
Test name
Test status
Simulation time 3556796543 ps
CPU time 38.8 seconds
Started Jul 09 05:49:20 PM PDT 24
Finished Jul 09 05:50:00 PM PDT 24
Peak memory 223828 kb
Host smart-febe4f25-34a6-4921-ae57-a01d4f0c883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438918029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2438918029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.60690892
Short name T957
Test name
Test status
Simulation time 25599197753 ps
CPU time 184.44 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 05:52:49 PM PDT 24
Peak memory 237836 kb
Host smart-bccd1e06-6c73-4d87-a7a7-2ab9c629a367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60690892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.60690892 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.268652250
Short name T1005
Test name
Test status
Simulation time 887609859 ps
CPU time 70.69 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 223804 kb
Host smart-8e40ead5-3579-4884-aad3-17b98d896aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268652250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.268652250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1388922333
Short name T1071
Test name
Test status
Simulation time 1205559293 ps
CPU time 11.27 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:49:53 PM PDT 24
Peak memory 223596 kb
Host smart-dc582666-fffc-40c4-abb1-63839dc78634
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1388922333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1388922333 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.676070275
Short name T72
Test name
Test status
Simulation time 292447829 ps
CPU time 21.66 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 05:49:58 PM PDT 24
Peak memory 223740 kb
Host smart-daaa4391-e230-4120-a0dc-26ef64ff8ce3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=676070275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.676070275 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3831555766
Short name T47
Test name
Test status
Simulation time 3345867828 ps
CPU time 33.08 seconds
Started Jul 09 05:49:33 PM PDT 24
Finished Jul 09 05:50:07 PM PDT 24
Peak memory 216824 kb
Host smart-b09d042b-b61b-4f65-8aab-27261ce4eda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831555766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3831555766 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.2191098763
Short name T44
Test name
Test status
Simulation time 9122021097 ps
CPU time 264.67 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 05:54:21 PM PDT 24
Peak memory 244284 kb
Host smart-f29f7240-b1cd-49d4-97c3-906ad2d07e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191098763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.2191098763 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.1645511172
Short name T520
Test name
Test status
Simulation time 18185820724 ps
CPU time 217.7 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:53:31 PM PDT 24
Peak memory 248476 kb
Host smart-60aa91aa-7aa6-4f02-ad65-9dd9d3659216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645511172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1645511172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.3293565654
Short name T809
Test name
Test status
Simulation time 5790363084 ps
CPU time 6.45 seconds
Started Jul 09 05:49:33 PM PDT 24
Finished Jul 09 05:49:41 PM PDT 24
Peak memory 215656 kb
Host smart-f276da1a-a774-4fc6-b1e7-00a721098974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293565654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3293565654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.1117850861
Short name T9
Test name
Test status
Simulation time 479442947 ps
CPU time 1.47 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 05:49:37 PM PDT 24
Peak memory 215600 kb
Host smart-097600ef-3d8d-4232-8f29-b657abdd4524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117850861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1117850861 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.1792099237
Short name T506
Test name
Test status
Simulation time 17281187866 ps
CPU time 274.41 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 05:54:10 PM PDT 24
Peak memory 247316 kb
Host smart-8f24c260-d10b-4f77-8b76-07d68ee5d100
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792099237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.1792099237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.4257788123
Short name T913
Test name
Test status
Simulation time 5855858043 ps
CPU time 77.66 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:51:05 PM PDT 24
Peak memory 227972 kb
Host smart-35e5341c-4d74-4710-8d9a-2cd3718024f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257788123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.4257788123 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.1502124236
Short name T11
Test name
Test status
Simulation time 21302673975 ps
CPU time 54.8 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 252068 kb
Host smart-81cb6e36-a121-4bb7-980b-8cbd2848bb6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502124236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1502124236 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.326572750
Short name T347
Test name
Test status
Simulation time 5351522854 ps
CPU time 66.84 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 05:50:46 PM PDT 24
Peak memory 224172 kb
Host smart-176c4e6a-cad2-4bbf-ae72-827d679749ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326572750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.326572750 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3567063819
Short name T950
Test name
Test status
Simulation time 807479963 ps
CPU time 17.15 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 05:49:52 PM PDT 24
Peak memory 217008 kb
Host smart-0e811cdb-a633-4da7-845b-c604ee688179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567063819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3567063819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.1123879712
Short name T413
Test name
Test status
Simulation time 62704420864 ps
CPU time 1160.02 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 06:09:03 PM PDT 24
Peak memory 371516 kb
Host smart-bbf5e93f-5fa3-4de8-b928-27d29c42c09a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1123879712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1123879712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.1453502137
Short name T3
Test name
Test status
Simulation time 543746882 ps
CPU time 5.08 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 05:49:41 PM PDT 24
Peak memory 215644 kb
Host smart-ba4a2c3e-8da6-418e-9e6c-3a8acecd04bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453502137 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.1453502137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.959873777
Short name T450
Test name
Test status
Simulation time 67172665 ps
CPU time 3.86 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 05:49:45 PM PDT 24
Peak memory 215572 kb
Host smart-0ccc3da0-322c-4b68-bb9d-0413895a0683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959873777 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.959873777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.1990329173
Short name T243
Test name
Test status
Simulation time 202334042963 ps
CPU time 1898.99 seconds
Started Jul 09 05:49:31 PM PDT 24
Finished Jul 09 06:21:10 PM PDT 24
Peak memory 391536 kb
Host smart-02edb2d2-9edd-4719-87d8-842b9aee2300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1990329173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1990329173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.2136839500
Short name T605
Test name
Test status
Simulation time 330879993010 ps
CPU time 1845.43 seconds
Started Jul 09 05:49:56 PM PDT 24
Finished Jul 09 06:20:43 PM PDT 24
Peak memory 378512 kb
Host smart-6309fa1f-3669-4091-888b-19d2ce1587e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2136839500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2136839500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2741524608
Short name T653
Test name
Test status
Simulation time 518479456450 ps
CPU time 1274.54 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 06:10:55 PM PDT 24
Peak memory 333992 kb
Host smart-a83c8efd-383e-40e7-81f4-64c45aca3c22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2741524608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2741524608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1273873701
Short name T532
Test name
Test status
Simulation time 193520878056 ps
CPU time 917.24 seconds
Started Jul 09 05:49:29 PM PDT 24
Finished Jul 09 06:04:47 PM PDT 24
Peak memory 292720 kb
Host smart-2d82a727-6251-4011-8858-bb390b923eff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1273873701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1273873701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.1035356358
Short name T761
Test name
Test status
Simulation time 434112066986 ps
CPU time 4805.3 seconds
Started Jul 09 05:49:28 PM PDT 24
Finished Jul 09 07:09:35 PM PDT 24
Peak memory 644304 kb
Host smart-0b3df983-cdb4-4600-b653-fa4b861b0979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1035356358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1035356358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.2495220457
Short name T822
Test name
Test status
Simulation time 225129203641 ps
CPU time 4150.21 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 06:58:51 PM PDT 24
Peak memory 558768 kb
Host smart-5a40f802-7b22-4802-bf01-a37198db02df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2495220457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2495220457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3453070185
Short name T932
Test name
Test status
Simulation time 46128659 ps
CPU time 0.78 seconds
Started Jul 09 05:50:30 PM PDT 24
Finished Jul 09 05:50:31 PM PDT 24
Peak memory 205360 kb
Host smart-b42a812f-66f3-4ef1-b846-62fb2235c8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453070185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3453070185 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.1529767505
Short name T593
Test name
Test status
Simulation time 1916524968 ps
CPU time 33.46 seconds
Started Jul 09 05:50:29 PM PDT 24
Finished Jul 09 05:51:03 PM PDT 24
Peak memory 220064 kb
Host smart-b0d357b8-c7a2-4cfb-8511-0e15540ddb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529767505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1529767505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.4110851421
Short name T498
Test name
Test status
Simulation time 21605078355 ps
CPU time 331.46 seconds
Started Jul 09 05:50:26 PM PDT 24
Finished Jul 09 05:55:58 PM PDT 24
Peak memory 227132 kb
Host smart-d4bfff04-b66a-46f6-80a7-779884273b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110851421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.4110851421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.1708037228
Short name T217
Test name
Test status
Simulation time 8946842512 ps
CPU time 140.39 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 05:52:52 PM PDT 24
Peak memory 232924 kb
Host smart-b5246f81-a11a-4cc5-8fe9-e12ca9541865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708037228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1708037228 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.4058685431
Short name T807
Test name
Test status
Simulation time 36057178564 ps
CPU time 229.22 seconds
Started Jul 09 05:50:29 PM PDT 24
Finished Jul 09 05:54:19 PM PDT 24
Peak memory 250388 kb
Host smart-d4a25b92-975a-4b8e-a98d-dbf98041cdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058685431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.4058685431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.2855978491
Short name T63
Test name
Test status
Simulation time 966203353 ps
CPU time 4.62 seconds
Started Jul 09 05:50:29 PM PDT 24
Finished Jul 09 05:50:34 PM PDT 24
Peak memory 207280 kb
Host smart-2d03b0fa-e6fc-4f9d-bacf-03df6cc93ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855978491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2855978491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.577814788
Short name T76
Test name
Test status
Simulation time 60803079 ps
CPU time 1.19 seconds
Started Jul 09 05:50:30 PM PDT 24
Finished Jul 09 05:50:32 PM PDT 24
Peak memory 215652 kb
Host smart-c9547ec7-03c8-454f-ad23-4f329d91b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577814788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.577814788 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.854156455
Short name T616
Test name
Test status
Simulation time 14308044012 ps
CPU time 1239.32 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 06:11:13 PM PDT 24
Peak memory 352692 kb
Host smart-61b75e11-8eda-4d8e-b181-ec453ba7a17a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854156455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an
d_output.854156455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.3248447305
Short name T881
Test name
Test status
Simulation time 4878751589 ps
CPU time 66.07 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 05:51:39 PM PDT 24
Peak memory 224684 kb
Host smart-322a5eea-e36a-4c6f-9bc4-3f1673be04da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248447305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3248447305 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.1589086207
Short name T344
Test name
Test status
Simulation time 2733325655 ps
CPU time 15.08 seconds
Started Jul 09 05:50:28 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 215696 kb
Host smart-16068a49-bee8-4538-b25f-1d792f220cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589086207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1589086207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.1794831287
Short name T909
Test name
Test status
Simulation time 199270592564 ps
CPU time 1280.16 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 06:11:51 PM PDT 24
Peak memory 355664 kb
Host smart-74e8772c-7cf2-456e-afec-efcc09267e46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1794831287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1794831287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.3237757127
Short name T67
Test name
Test status
Simulation time 63388007 ps
CPU time 3.77 seconds
Started Jul 09 05:50:29 PM PDT 24
Finished Jul 09 05:50:33 PM PDT 24
Peak memory 215676 kb
Host smart-8c7fa35d-3cc2-42f1-b9a4-5c25791bdfd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237757127 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.3237757127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2729106284
Short name T784
Test name
Test status
Simulation time 1033372187 ps
CPU time 5.4 seconds
Started Jul 09 05:50:30 PM PDT 24
Finished Jul 09 05:50:36 PM PDT 24
Peak memory 215604 kb
Host smart-ec350b27-d565-4206-90ce-e7f2cdb59d5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729106284 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2729106284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.2596791853
Short name T184
Test name
Test status
Simulation time 67431612930 ps
CPU time 1735.6 seconds
Started Jul 09 05:50:27 PM PDT 24
Finished Jul 09 06:19:23 PM PDT 24
Peak memory 390436 kb
Host smart-47691d04-377f-4e76-99d9-e1304ca33056
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2596791853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2596791853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.515212598
Short name T277
Test name
Test status
Simulation time 252425430355 ps
CPU time 1617.1 seconds
Started Jul 09 05:50:24 PM PDT 24
Finished Jul 09 06:17:22 PM PDT 24
Peak memory 371180 kb
Host smart-edbbed3e-6470-4c83-857b-7fa990657907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=515212598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.515212598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.3547413259
Short name T256
Test name
Test status
Simulation time 54330533265 ps
CPU time 1130.97 seconds
Started Jul 09 05:50:25 PM PDT 24
Finished Jul 09 06:09:17 PM PDT 24
Peak memory 334164 kb
Host smart-215e1560-2a5e-42e2-ac08-fce8df80bcb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3547413259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.3547413259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.3168529565
Short name T234
Test name
Test status
Simulation time 87827583517 ps
CPU time 879.77 seconds
Started Jul 09 05:50:27 PM PDT 24
Finished Jul 09 06:05:07 PM PDT 24
Peak memory 294400 kb
Host smart-6bbc0fa3-5ff9-4e0c-b1d9-467d2ae4b6ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3168529565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3168529565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2283791722
Short name T550
Test name
Test status
Simulation time 225942788441 ps
CPU time 4354.19 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 07:03:07 PM PDT 24
Peak memory 634628 kb
Host smart-7e8dedbd-8114-451f-a38d-f287678b8ee8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2283791722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2283791722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.3344824777
Short name T575
Test name
Test status
Simulation time 460569158894 ps
CPU time 4423.65 seconds
Started Jul 09 05:50:47 PM PDT 24
Finished Jul 09 07:04:31 PM PDT 24
Peak memory 560460 kb
Host smart-f5875402-a4c5-4a44-98ba-e46320d3b174
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3344824777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3344824777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.3631764201
Short name T579
Test name
Test status
Simulation time 20897581 ps
CPU time 0.73 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 05:50:34 PM PDT 24
Peak memory 205364 kb
Host smart-4b8aff7e-6fd3-4444-beb6-7e8b9aaf7c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631764201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3631764201 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.154154905
Short name T987
Test name
Test status
Simulation time 12027549937 ps
CPU time 299.31 seconds
Started Jul 09 05:50:34 PM PDT 24
Finished Jul 09 05:55:34 PM PDT 24
Peak memory 245096 kb
Host smart-61565b9b-43a8-4808-9544-1fbe5b9a8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154154905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.154154905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.4147917579
Short name T852
Test name
Test status
Simulation time 2611886422 ps
CPU time 53.86 seconds
Started Jul 09 05:50:30 PM PDT 24
Finished Jul 09 05:51:25 PM PDT 24
Peak memory 219820 kb
Host smart-9745fb5f-d823-4587-a9fe-a9c3661ec5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147917579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.4147917579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.187416469
Short name T636
Test name
Test status
Simulation time 23746086744 ps
CPU time 205.41 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 05:54:00 PM PDT 24
Peak memory 239540 kb
Host smart-10fee1fe-ef70-4113-88ee-965a09626c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187416469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.187416469 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.73055443
Short name T496
Test name
Test status
Simulation time 981052191 ps
CPU time 73.13 seconds
Started Jul 09 05:50:34 PM PDT 24
Finished Jul 09 05:51:48 PM PDT 24
Peak memory 238044 kb
Host smart-b55d630c-ba7f-4f71-84d4-07988260dcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73055443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.73055443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.1485665869
Short name T412
Test name
Test status
Simulation time 1487638321 ps
CPU time 8.02 seconds
Started Jul 09 05:50:34 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 207396 kb
Host smart-a515456a-2989-467c-9356-c6aca8adc0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485665869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1485665869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.2015753038
Short name T834
Test name
Test status
Simulation time 174335800 ps
CPU time 1.25 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 05:50:35 PM PDT 24
Peak memory 215576 kb
Host smart-b43debe6-481d-40a1-be4e-4c19b19f0aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015753038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2015753038 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.3319947014
Short name T213
Test name
Test status
Simulation time 15771391566 ps
CPU time 337.11 seconds
Started Jul 09 05:50:30 PM PDT 24
Finished Jul 09 05:56:08 PM PDT 24
Peak memory 255404 kb
Host smart-5f1b8790-059a-426d-a7aa-8770e202a216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319947014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.3319947014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.1836959065
Short name T1034
Test name
Test status
Simulation time 1110956061 ps
CPU time 79.87 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 05:51:51 PM PDT 24
Peak memory 226052 kb
Host smart-b89ba8e1-710f-4d36-9056-6c8eef734aa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836959065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1836959065 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.2428992460
Short name T227
Test name
Test status
Simulation time 391154451 ps
CPU time 4.84 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 05:50:36 PM PDT 24
Peak memory 221384 kb
Host smart-44b7bd38-2f3a-41bb-9efc-29664fdc4121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428992460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2428992460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.1649102536
Short name T1006
Test name
Test status
Simulation time 28511202883 ps
CPU time 126.38 seconds
Started Jul 09 05:50:36 PM PDT 24
Finished Jul 09 05:52:43 PM PDT 24
Peak memory 240300 kb
Host smart-a15d25d7-f014-4155-9101-d43cb706f202
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1649102536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1649102536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3626875289
Short name T526
Test name
Test status
Simulation time 330884296 ps
CPU time 4.44 seconds
Started Jul 09 05:50:36 PM PDT 24
Finished Jul 09 05:50:41 PM PDT 24
Peak memory 215664 kb
Host smart-a4424000-f0c4-4f15-bb80-bb0fd6fbbf4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626875289 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3626875289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.732349131
Short name T19
Test name
Test status
Simulation time 173558768 ps
CPU time 4.6 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 05:50:39 PM PDT 24
Peak memory 215640 kb
Host smart-d5d0b6e5-d273-47f5-9b27-feaf4631287b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732349131 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.kmac_test_vectors_kmac_xof.732349131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.2740841720
Short name T892
Test name
Test status
Simulation time 127929869748 ps
CPU time 1740.51 seconds
Started Jul 09 05:50:28 PM PDT 24
Finished Jul 09 06:19:30 PM PDT 24
Peak memory 379196 kb
Host smart-e010ce92-1db3-44d3-bbeb-fef3417755d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2740841720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2740841720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2489230277
Short name T122
Test name
Test status
Simulation time 18701204090 ps
CPU time 1405.7 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 06:14:00 PM PDT 24
Peak memory 374708 kb
Host smart-e46dd5d3-4e17-4214-99be-a0e382c01728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2489230277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2489230277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.2054702128
Short name T600
Test name
Test status
Simulation time 47841998608 ps
CPU time 1319.08 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 06:12:33 PM PDT 24
Peak memory 334632 kb
Host smart-38f44e9d-a9d7-4be0-83c8-da3aff04a328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2054702128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2054702128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.3157030082
Short name T785
Test name
Test status
Simulation time 9936923345 ps
CPU time 783.73 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 06:03:38 PM PDT 24
Peak memory 296048 kb
Host smart-f5772d3c-6323-4c06-9354-52fa9896c1d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3157030082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3157030082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.166589500
Short name T475
Test name
Test status
Simulation time 262146080981 ps
CPU time 4836.71 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 07:11:11 PM PDT 24
Peak memory 651416 kb
Host smart-11caadbb-c216-4b5a-927e-f9d4047dc4e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=166589500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.166589500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.1140360784
Short name T567
Test name
Test status
Simulation time 721018685254 ps
CPU time 3998.18 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 06:57:12 PM PDT 24
Peak memory 558652 kb
Host smart-b5be4db9-0e28-4d76-b124-319bd120dc13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1140360784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.1140360784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.76315463
Short name T941
Test name
Test status
Simulation time 23620558 ps
CPU time 0.75 seconds
Started Jul 09 05:50:41 PM PDT 24
Finished Jul 09 05:50:42 PM PDT 24
Peak memory 205568 kb
Host smart-9d723260-05f3-45b0-81bc-a007a2ef8973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76315463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.76315463 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3099349264
Short name T731
Test name
Test status
Simulation time 2658363053 ps
CPU time 113.9 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 05:52:32 PM PDT 24
Peak memory 233616 kb
Host smart-92a56dac-b45d-4018-8e64-6e2b3e5c062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099349264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3099349264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1775248628
Short name T552
Test name
Test status
Simulation time 15904830533 ps
CPU time 188.54 seconds
Started Jul 09 05:50:31 PM PDT 24
Finished Jul 09 05:53:40 PM PDT 24
Peak memory 234572 kb
Host smart-15daf2d3-7f8c-4e01-9867-5fc72c534a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775248628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1775248628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.241722889
Short name T835
Test name
Test status
Simulation time 33878341760 ps
CPU time 328 seconds
Started Jul 09 05:50:37 PM PDT 24
Finished Jul 09 05:56:05 PM PDT 24
Peak memory 245020 kb
Host smart-11a688fc-f5e9-42c5-b736-64df9afb98d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241722889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.241722889 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.3770555894
Short name T224
Test name
Test status
Simulation time 4423547078 ps
CPU time 116.4 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 05:52:35 PM PDT 24
Peak memory 240076 kb
Host smart-979cfd61-81b5-417c-a44e-4183046f9e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770555894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3770555894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.850033308
Short name T765
Test name
Test status
Simulation time 3411916706 ps
CPU time 6.3 seconds
Started Jul 09 05:50:36 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 207444 kb
Host smart-1fcca78d-6ad9-4ab4-ae85-614eae1e17e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850033308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.850033308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.3568225372
Short name T83
Test name
Test status
Simulation time 120069120 ps
CPU time 1.21 seconds
Started Jul 09 05:50:36 PM PDT 24
Finished Jul 09 05:50:38 PM PDT 24
Peak memory 219840 kb
Host smart-4c90b77c-0edc-4444-8490-8faa246d5a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568225372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3568225372 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.2838786312
Short name T409
Test name
Test status
Simulation time 47053663383 ps
CPU time 2062.95 seconds
Started Jul 09 05:50:35 PM PDT 24
Finished Jul 09 06:24:58 PM PDT 24
Peak memory 443884 kb
Host smart-38b9ca5c-410e-4f3f-9786-fed249ecdd22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838786312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.2838786312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3438388524
Short name T244
Test name
Test status
Simulation time 4095045337 ps
CPU time 52.61 seconds
Started Jul 09 05:50:33 PM PDT 24
Finished Jul 09 05:51:27 PM PDT 24
Peak memory 223908 kb
Host smart-1fe3cc0e-e36b-4aff-949e-50974d20a0b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438388524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3438388524 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.1494745486
Short name T583
Test name
Test status
Simulation time 1046650914 ps
CPU time 14.27 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 05:50:48 PM PDT 24
Peak memory 218408 kb
Host smart-8bf6bef4-8ca1-4279-83ed-590a08292610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494745486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1494745486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3233558158
Short name T87
Test name
Test status
Simulation time 43419972722 ps
CPU time 784.73 seconds
Started Jul 09 05:50:35 PM PDT 24
Finished Jul 09 06:03:41 PM PDT 24
Peak memory 321580 kb
Host smart-7c13afb1-0411-4568-8e45-724ff47d2763
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3233558158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3233558158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.288523581
Short name T877
Test name
Test status
Simulation time 655061528 ps
CPU time 4.49 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 215732 kb
Host smart-43e00880-0202-4f23-a8d4-3ec5e230fc40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288523581 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.kmac_test_vectors_kmac.288523581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.570048661
Short name T186
Test name
Test status
Simulation time 704705726 ps
CPU time 4.19 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 215732 kb
Host smart-2f4f7bf4-7b3a-4bd7-902b-608f3a5263e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570048661 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.kmac_test_vectors_kmac_xof.570048661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.4183267604
Short name T511
Test name
Test status
Simulation time 405583825910 ps
CPU time 2169.85 seconds
Started Jul 09 05:50:32 PM PDT 24
Finished Jul 09 06:26:43 PM PDT 24
Peak memory 392852 kb
Host smart-646af6cc-c354-4844-84eb-e6fc5e5208f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4183267604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.4183267604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.1335724132
Short name T502
Test name
Test status
Simulation time 253438753609 ps
CPU time 1596.32 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 06:17:15 PM PDT 24
Peak memory 372272 kb
Host smart-c73af53b-e6c1-43ca-a091-160757c27dd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1335724132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1335724132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.2352382919
Short name T683
Test name
Test status
Simulation time 43278363056 ps
CPU time 1068.58 seconds
Started Jul 09 05:50:35 PM PDT 24
Finished Jul 09 06:08:24 PM PDT 24
Peak memory 330156 kb
Host smart-57c6ac94-508e-42a1-b610-fec7dda1d3e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2352382919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2352382919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.1572629341
Short name T771
Test name
Test status
Simulation time 49869156678 ps
CPU time 1055.59 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 06:08:14 PM PDT 24
Peak memory 297332 kb
Host smart-6c6c7637-738a-4e99-a3a8-6518433f21b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1572629341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.1572629341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.4067958937
Short name T752
Test name
Test status
Simulation time 179464876790 ps
CPU time 4612.21 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 07:07:31 PM PDT 24
Peak memory 651408 kb
Host smart-59dfe0e5-4153-4832-a4e6-029941ca9b0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4067958937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.4067958937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.4058674088
Short name T668
Test name
Test status
Simulation time 857573189168 ps
CPU time 4317.98 seconds
Started Jul 09 05:50:38 PM PDT 24
Finished Jul 09 07:02:36 PM PDT 24
Peak memory 551820 kb
Host smart-3076ab33-8c8a-421b-b54d-43eb591304b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4058674088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.4058674088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.1730235796
Short name T746
Test name
Test status
Simulation time 24446145 ps
CPU time 0.76 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 05:50:44 PM PDT 24
Peak memory 205324 kb
Host smart-0f621f0d-c7e5-4bfe-8158-380e51fa6db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730235796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1730235796 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.2525379199
Short name T1022
Test name
Test status
Simulation time 5695571076 ps
CPU time 33.7 seconds
Started Jul 09 05:50:39 PM PDT 24
Finished Jul 09 05:51:13 PM PDT 24
Peak memory 221064 kb
Host smart-aad71342-ea7c-418e-b45c-83e34764677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525379199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2525379199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.2849554608
Short name T462
Test name
Test status
Simulation time 54597976685 ps
CPU time 517.03 seconds
Started Jul 09 05:50:41 PM PDT 24
Finished Jul 09 05:59:19 PM PDT 24
Peak memory 230344 kb
Host smart-b535f9dd-ecb4-4b02-8a42-f32ba886e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849554608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2849554608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.950244698
Short name T235
Test name
Test status
Simulation time 6236723791 ps
CPU time 88.31 seconds
Started Jul 09 05:50:39 PM PDT 24
Finished Jul 09 05:52:08 PM PDT 24
Peak memory 227620 kb
Host smart-b0eb42a9-f26d-42e7-b28e-05c054251357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950244698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.950244698 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_key_error.291025361
Short name T64
Test name
Test status
Simulation time 2117433238 ps
CPU time 3.08 seconds
Started Jul 09 05:50:41 PM PDT 24
Finished Jul 09 05:50:44 PM PDT 24
Peak memory 215452 kb
Host smart-ed81961f-7c1a-4f94-8428-79b07935dc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291025361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.291025361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3362598585
Short name T6
Test name
Test status
Simulation time 785952534 ps
CPU time 49.28 seconds
Started Jul 09 05:50:44 PM PDT 24
Finished Jul 09 05:51:33 PM PDT 24
Peak memory 232124 kb
Host smart-011cac23-3040-49e2-bc18-e00c38e3f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362598585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3362598585 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.167181450
Short name T963
Test name
Test status
Simulation time 25150029025 ps
CPU time 2151.38 seconds
Started Jul 09 05:50:44 PM PDT 24
Finished Jul 09 06:26:36 PM PDT 24
Peak memory 456156 kb
Host smart-dcc1e9b6-f578-4533-b931-7c6172327783
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167181450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_an
d_output.167181450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.1986761867
Short name T1058
Test name
Test status
Simulation time 3852445632 ps
CPU time 207.34 seconds
Started Jul 09 05:50:40 PM PDT 24
Finished Jul 09 05:54:08 PM PDT 24
Peak memory 237244 kb
Host smart-f5e73c0b-c627-43a1-b9f2-481519288fe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986761867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1986761867 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1429060085
Short name T312
Test name
Test status
Simulation time 9862149055 ps
CPU time 41.11 seconds
Started Jul 09 05:50:40 PM PDT 24
Finished Jul 09 05:51:21 PM PDT 24
Peak memory 221840 kb
Host smart-7a4b4f56-47c0-4ea3-b2a5-f01de01cda53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429060085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1429060085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.4117660341
Short name T522
Test name
Test status
Simulation time 24542747990 ps
CPU time 230.08 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 05:54:33 PM PDT 24
Peak memory 263224 kb
Host smart-f651491b-88a2-413f-b3e5-94ee3329abe8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4117660341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.4117660341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1883178309
Short name T894
Test name
Test status
Simulation time 68466390 ps
CPU time 3.6 seconds
Started Jul 09 05:50:40 PM PDT 24
Finished Jul 09 05:50:44 PM PDT 24
Peak memory 215708 kb
Host smart-584bb153-0ff8-4c3d-af96-025921c103f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883178309 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1883178309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.2726264996
Short name T1014
Test name
Test status
Simulation time 400096396 ps
CPU time 4.43 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 05:50:48 PM PDT 24
Peak memory 215668 kb
Host smart-b094149f-bbc2-42dd-a62e-30525bb26901
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726264996 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.2726264996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.682545417
Short name T1021
Test name
Test status
Simulation time 126179678294 ps
CPU time 1613.91 seconds
Started Jul 09 05:50:40 PM PDT 24
Finished Jul 09 06:17:35 PM PDT 24
Peak memory 394356 kb
Host smart-69a862c1-532b-484d-9fcf-083fd28edd7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=682545417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.682545417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.3071832210
Short name T631
Test name
Test status
Simulation time 75014522704 ps
CPU time 1496.91 seconds
Started Jul 09 05:50:41 PM PDT 24
Finished Jul 09 06:15:39 PM PDT 24
Peak memory 387352 kb
Host smart-6df43d8a-6502-450d-832c-d635f27880b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3071832210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.3071832210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2929222702
Short name T333
Test name
Test status
Simulation time 165684465603 ps
CPU time 1450.57 seconds
Started Jul 09 05:50:40 PM PDT 24
Finished Jul 09 06:14:51 PM PDT 24
Peak memory 339212 kb
Host smart-2961c883-ae3d-4818-adee-35fc3f1f3262
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2929222702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2929222702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.1796639020
Short name T508
Test name
Test status
Simulation time 10051135042 ps
CPU time 771.33 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 06:03:35 PM PDT 24
Peak memory 299540 kb
Host smart-91f162d4-955d-4ecf-8c11-e2110383a200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1796639020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1796639020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.2861160581
Short name T70
Test name
Test status
Simulation time 203292750970 ps
CPU time 4131.77 seconds
Started Jul 09 05:50:39 PM PDT 24
Finished Jul 09 06:59:31 PM PDT 24
Peak memory 650708 kb
Host smart-86301c65-26ce-4379-9d78-ccaa0f0d4578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2861160581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2861160581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3460911486
Short name T968
Test name
Test status
Simulation time 44676952089 ps
CPU time 3538.94 seconds
Started Jul 09 05:50:39 PM PDT 24
Finished Jul 09 06:49:39 PM PDT 24
Peak memory 572288 kb
Host smart-7f266101-8294-4b64-9b20-afda12867ce6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3460911486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3460911486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.1476706862
Short name T541
Test name
Test status
Simulation time 21477546 ps
CPU time 0.73 seconds
Started Jul 09 05:50:48 PM PDT 24
Finished Jul 09 05:50:49 PM PDT 24
Peak memory 205364 kb
Host smart-e04139b5-516b-4f9f-b251-1d13cb1b8698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476706862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1476706862 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.610089742
Short name T442
Test name
Test status
Simulation time 42009706233 ps
CPU time 203.53 seconds
Started Jul 09 05:50:47 PM PDT 24
Finished Jul 09 05:54:11 PM PDT 24
Peak memory 239652 kb
Host smart-ece6b760-67c5-404c-a9bb-d694f06dd76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610089742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.610089742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.214665205
Short name T908
Test name
Test status
Simulation time 16840012232 ps
CPU time 74.68 seconds
Started Jul 09 05:50:44 PM PDT 24
Finished Jul 09 05:51:59 PM PDT 24
Peak memory 219624 kb
Host smart-5bbedbfa-ce25-4c5e-b027-1acadee59198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214665205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.214665205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.1230013012
Short name T873
Test name
Test status
Simulation time 654164480 ps
CPU time 10.49 seconds
Started Jul 09 05:50:50 PM PDT 24
Finished Jul 09 05:51:01 PM PDT 24
Peak memory 215652 kb
Host smart-ee61d00c-d5bc-4846-98cb-20a1dc515f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230013012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1230013012 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.3412761884
Short name T473
Test name
Test status
Simulation time 15450611673 ps
CPU time 78.47 seconds
Started Jul 09 05:50:45 PM PDT 24
Finished Jul 09 05:52:04 PM PDT 24
Peak memory 240248 kb
Host smart-81bee6ba-3324-4fb8-bf48-a2e67e5ade6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412761884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3412761884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.1299814421
Short name T62
Test name
Test status
Simulation time 1407755159 ps
CPU time 1.81 seconds
Started Jul 09 05:50:48 PM PDT 24
Finished Jul 09 05:50:51 PM PDT 24
Peak memory 207288 kb
Host smart-4390912d-28a0-424b-8859-7ea9d86fface
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299814421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1299814421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.3335225570
Short name T36
Test name
Test status
Simulation time 81608841 ps
CPU time 1.13 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 05:50:48 PM PDT 24
Peak memory 215608 kb
Host smart-7bb495d9-bb66-4d10-b8b8-5930d8706600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335225570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3335225570 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3067077493
Short name T911
Test name
Test status
Simulation time 10432324459 ps
CPU time 415.79 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 05:57:40 PM PDT 24
Peak memory 267772 kb
Host smart-dac4e774-2a10-47f1-9e4b-e94c018d4255
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067077493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3067077493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.798331398
Short name T997
Test name
Test status
Simulation time 2621177138 ps
CPU time 106.7 seconds
Started Jul 09 05:50:45 PM PDT 24
Finished Jul 09 05:52:32 PM PDT 24
Peak memory 229144 kb
Host smart-8c9b9888-403c-4ead-87cd-dc74a2b9db23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798331398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.798331398 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.788855848
Short name T945
Test name
Test status
Simulation time 15295168343 ps
CPU time 51.71 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 05:51:36 PM PDT 24
Peak memory 220520 kb
Host smart-7cadcf46-6cc7-4869-a2e6-717f15d4db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788855848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.788855848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.3200748569
Short name T670
Test name
Test status
Simulation time 136941703263 ps
CPU time 773.84 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 06:03:40 PM PDT 24
Peak memory 286148 kb
Host smart-6132afea-de27-4ba8-9cae-60a43bd9de32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3200748569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3200748569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.1728106933
Short name T432
Test name
Test status
Simulation time 69249670 ps
CPU time 3.64 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 05:50:50 PM PDT 24
Peak memory 215748 kb
Host smart-b36a9f62-b1f1-4d3f-b467-6f88b8383e37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728106933 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.1728106933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.4194495258
Short name T397
Test name
Test status
Simulation time 66435524 ps
CPU time 3.88 seconds
Started Jul 09 05:50:47 PM PDT 24
Finished Jul 09 05:50:51 PM PDT 24
Peak memory 208836 kb
Host smart-3174b341-8d41-408a-9909-0bd0838cbc97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194495258 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.4194495258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1917303935
Short name T1010
Test name
Test status
Simulation time 39513547981 ps
CPU time 1606.75 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 06:17:30 PM PDT 24
Peak memory 394456 kb
Host smart-f56c5657-5787-4c24-a321-5885672a381d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1917303935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1917303935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.670356202
Short name T148
Test name
Test status
Simulation time 124853906176 ps
CPU time 1802.16 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 06:20:48 PM PDT 24
Peak memory 374080 kb
Host smart-280c6902-7d7c-4a9c-8c1b-5e1d272b018b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=670356202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.670356202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.3876514284
Short name T868
Test name
Test status
Simulation time 94454533789 ps
CPU time 1324.4 seconds
Started Jul 09 05:50:42 PM PDT 24
Finished Jul 09 06:12:46 PM PDT 24
Peak memory 336524 kb
Host smart-4e2ecce4-14c0-4703-843b-452b5bac3c5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3876514284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.3876514284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.1253639126
Short name T386
Test name
Test status
Simulation time 481930943860 ps
CPU time 956.14 seconds
Started Jul 09 05:50:43 PM PDT 24
Finished Jul 09 06:06:40 PM PDT 24
Peak memory 292664 kb
Host smart-ce27f268-c45e-4e3f-ac7c-2d71e7759640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1253639126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.1253639126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.1720083332
Short name T185
Test name
Test status
Simulation time 100964679096 ps
CPU time 3944.35 seconds
Started Jul 09 05:50:48 PM PDT 24
Finished Jul 09 06:56:33 PM PDT 24
Peak memory 641084 kb
Host smart-e616a991-29a8-46e4-8144-23f8c145aa3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1720083332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.1720083332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.2884169900
Short name T1070
Test name
Test status
Simulation time 577933734631 ps
CPU time 3787.95 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 06:53:55 PM PDT 24
Peak memory 556828 kb
Host smart-4a313391-d377-422a-889f-66ced0644b44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2884169900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.2884169900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.1186708387
Short name T448
Test name
Test status
Simulation time 67190605 ps
CPU time 0.76 seconds
Started Jul 09 05:50:49 PM PDT 24
Finished Jul 09 05:50:50 PM PDT 24
Peak memory 205356 kb
Host smart-00233bc4-1793-4c4f-bf28-f8ce01c39ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186708387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1186708387 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.3807946285
Short name T585
Test name
Test status
Simulation time 12103056791 ps
CPU time 166.5 seconds
Started Jul 09 05:50:48 PM PDT 24
Finished Jul 09 05:53:35 PM PDT 24
Peak memory 235548 kb
Host smart-160893ef-1a74-4a79-a921-b215ed14cc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807946285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3807946285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.1012299302
Short name T1012
Test name
Test status
Simulation time 45586076293 ps
CPU time 599.77 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 06:00:46 PM PDT 24
Peak memory 231152 kb
Host smart-e46dbad0-31ba-4187-bdc3-a0dc28e27aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012299302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1012299302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.3464594169
Short name T337
Test name
Test status
Simulation time 13968924457 ps
CPU time 250.94 seconds
Started Jul 09 05:50:48 PM PDT 24
Finished Jul 09 05:55:00 PM PDT 24
Peak memory 244504 kb
Host smart-ebb64dcf-6b1c-4b80-84df-75c028da6570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464594169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3464594169 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.3481858811
Short name T33
Test name
Test status
Simulation time 17595035098 ps
CPU time 192.85 seconds
Started Jul 09 05:50:50 PM PDT 24
Finished Jul 09 05:54:04 PM PDT 24
Peak memory 255960 kb
Host smart-9eee7cd2-32cc-46b7-af19-9a45d50cef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481858811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3481858811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.2715472915
Short name T390
Test name
Test status
Simulation time 1288321440 ps
CPU time 4.93 seconds
Started Jul 09 05:50:51 PM PDT 24
Finished Jul 09 05:50:56 PM PDT 24
Peak memory 207256 kb
Host smart-4b744f3f-3573-47e5-b56e-c7c8ae3aeb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715472915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2715472915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.1344231839
Short name T719
Test name
Test status
Simulation time 44075586 ps
CPU time 1.31 seconds
Started Jul 09 05:50:50 PM PDT 24
Finished Jul 09 05:50:52 PM PDT 24
Peak memory 215668 kb
Host smart-33a25f85-8eaa-4718-8e20-4f694d3404c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344231839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1344231839 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.4265784113
Short name T912
Test name
Test status
Simulation time 3591143912 ps
CPU time 79.49 seconds
Started Jul 09 05:50:50 PM PDT 24
Finished Jul 09 05:52:09 PM PDT 24
Peak memory 221896 kb
Host smart-2edabc30-c6f1-4f08-b707-75d7482f3373
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265784113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.4265784113 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.1781845917
Short name T713
Test name
Test status
Simulation time 6411603792 ps
CPU time 225.22 seconds
Started Jul 09 05:50:47 PM PDT 24
Finished Jul 09 05:54:32 PM PDT 24
Peak memory 239692 kb
Host smart-f7310d54-2d7f-4cd5-a84e-4b4bdfd1d275
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781845917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1781845917 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.731939749
Short name T483
Test name
Test status
Simulation time 323655508 ps
CPU time 16.84 seconds
Started Jul 09 05:50:46 PM PDT 24
Finished Jul 09 05:51:04 PM PDT 24
Peak memory 219180 kb
Host smart-f87514ee-4093-464e-aed0-e36ac891105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731939749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.731939749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.1908345319
Short name T401
Test name
Test status
Simulation time 31508473304 ps
CPU time 235.86 seconds
Started Jul 09 05:50:48 PM PDT 24
Finished Jul 09 05:54:44 PM PDT 24
Peak memory 252812 kb
Host smart-6407a627-7b61-4344-8155-9326fb608c71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1908345319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.1908345319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.440174929
Short name T530
Test name
Test status
Simulation time 708988907 ps
CPU time 4.62 seconds
Started Jul 09 05:50:49 PM PDT 24
Finished Jul 09 05:50:54 PM PDT 24
Peak memory 215740 kb
Host smart-cec70270-d250-4f20-8ab7-48faa1d0c883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440174929 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.kmac_test_vectors_kmac.440174929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.2391412411
Short name T200
Test name
Test status
Simulation time 173328444 ps
CPU time 4.34 seconds
Started Jul 09 05:50:51 PM PDT 24
Finished Jul 09 05:50:56 PM PDT 24
Peak memory 215596 kb
Host smart-c065f96f-08be-4ab0-8825-1ad0068ec145
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391412411 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.2391412411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.3957118409
Short name T290
Test name
Test status
Simulation time 35246732909 ps
CPU time 1379.45 seconds
Started Jul 09 05:50:49 PM PDT 24
Finished Jul 09 06:13:49 PM PDT 24
Peak memory 371440 kb
Host smart-b3ae2325-3310-4ab5-9f70-422352d2b4af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3957118409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.3957118409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.2189423845
Short name T935
Test name
Test status
Simulation time 56043318628 ps
CPU time 1216.4 seconds
Started Jul 09 05:50:47 PM PDT 24
Finished Jul 09 06:11:03 PM PDT 24
Peak memory 343140 kb
Host smart-385ee59f-6459-4e35-bff8-c3c275672c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2189423845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.2189423845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.179777431
Short name T248
Test name
Test status
Simulation time 189957610735 ps
CPU time 901.3 seconds
Started Jul 09 05:50:51 PM PDT 24
Finished Jul 09 06:05:53 PM PDT 24
Peak memory 292520 kb
Host smart-9da3250e-0ddf-4da8-851e-5cbd3421c0f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=179777431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.179777431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.3942971069
Short name T688
Test name
Test status
Simulation time 104774333774 ps
CPU time 4036.65 seconds
Started Jul 09 05:50:49 PM PDT 24
Finished Jul 09 06:58:07 PM PDT 24
Peak memory 660088 kb
Host smart-f3a323ac-5e9a-434c-a909-7cce662a8468
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3942971069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.3942971069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.687918928
Short name T762
Test name
Test status
Simulation time 439097620526 ps
CPU time 4523.43 seconds
Started Jul 09 05:50:49 PM PDT 24
Finished Jul 09 07:06:13 PM PDT 24
Peak memory 554944 kb
Host smart-a5b2a957-a5ba-4b24-955a-d40169a29c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=687918928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.687918928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1640857996
Short name T203
Test name
Test status
Simulation time 171073358 ps
CPU time 0.86 seconds
Started Jul 09 05:51:03 PM PDT 24
Finished Jul 09 05:51:04 PM PDT 24
Peak memory 205324 kb
Host smart-8abca230-426c-41c8-a0a8-df02c37ef39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640857996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1640857996 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.888388388
Short name T444
Test name
Test status
Simulation time 38585027629 ps
CPU time 198.96 seconds
Started Jul 09 05:50:55 PM PDT 24
Finished Jul 09 05:54:14 PM PDT 24
Peak memory 237684 kb
Host smart-7a82f1b3-b52c-4354-a4b8-ab7c20897217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888388388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.888388388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.2444250252
Short name T627
Test name
Test status
Simulation time 30818871953 ps
CPU time 657.83 seconds
Started Jul 09 05:50:57 PM PDT 24
Finished Jul 09 06:01:55 PM PDT 24
Peak memory 232496 kb
Host smart-04335560-5b05-4c6b-be20-e4b0079a0e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444250252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2444250252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.1914858979
Short name T590
Test name
Test status
Simulation time 2905421442 ps
CPU time 71.24 seconds
Started Jul 09 05:50:55 PM PDT 24
Finished Jul 09 05:52:07 PM PDT 24
Peak memory 225928 kb
Host smart-3dca5cc6-719b-46f8-93d1-e64929a59ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914858979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1914858979 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.2425395465
Short name T126
Test name
Test status
Simulation time 6746211932 ps
CPU time 177.38 seconds
Started Jul 09 05:50:59 PM PDT 24
Finished Jul 09 05:53:56 PM PDT 24
Peak memory 240320 kb
Host smart-90df24b0-7f3a-4264-91f9-f62ff7412b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425395465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2425395465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.2186057494
Short name T350
Test name
Test status
Simulation time 2576970664 ps
CPU time 3.76 seconds
Started Jul 09 05:50:57 PM PDT 24
Finished Jul 09 05:51:01 PM PDT 24
Peak memory 207380 kb
Host smart-f0f9224d-a0bc-4c4f-b774-c0ccbed5f8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186057494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2186057494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.2882483028
Short name T1079
Test name
Test status
Simulation time 163244424 ps
CPU time 1.38 seconds
Started Jul 09 05:50:56 PM PDT 24
Finished Jul 09 05:50:58 PM PDT 24
Peak memory 215652 kb
Host smart-9ea3ba99-20b9-4075-a258-2a34edfc98f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882483028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2882483028 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.530880952
Short name T563
Test name
Test status
Simulation time 20362715426 ps
CPU time 1687.93 seconds
Started Jul 09 05:50:54 PM PDT 24
Finished Jul 09 06:19:03 PM PDT 24
Peak memory 410972 kb
Host smart-d7418e21-f156-48f3-9c26-dffddb66417e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530880952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_an
d_output.530880952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.2949032419
Short name T207
Test name
Test status
Simulation time 23022513081 ps
CPU time 168.44 seconds
Started Jul 09 05:50:54 PM PDT 24
Finished Jul 09 05:53:43 PM PDT 24
Peak memory 232892 kb
Host smart-f9a9598c-3b39-42d5-b56e-e14a8822b7ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949032419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2949032419 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3146331757
Short name T837
Test name
Test status
Simulation time 324591664 ps
CPU time 13.9 seconds
Started Jul 09 05:50:50 PM PDT 24
Finished Jul 09 05:51:05 PM PDT 24
Peak memory 223816 kb
Host smart-5cbf5a60-4a90-4cab-aa8b-5057146ce2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146331757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3146331757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.2954808279
Short name T958
Test name
Test status
Simulation time 20991688931 ps
CPU time 100.08 seconds
Started Jul 09 05:50:58 PM PDT 24
Finished Jul 09 05:52:38 PM PDT 24
Peak memory 232824 kb
Host smart-89088f58-986f-4012-92c3-577788e042ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2954808279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2954808279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.428148062
Short name T682
Test name
Test status
Simulation time 139352984 ps
CPU time 4.17 seconds
Started Jul 09 05:50:57 PM PDT 24
Finished Jul 09 05:51:01 PM PDT 24
Peak memory 215652 kb
Host smart-45e3d4a2-afee-42d0-bfd3-fe68ab7c9dd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428148062 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.kmac_test_vectors_kmac.428148062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.2161473148
Short name T922
Test name
Test status
Simulation time 68601432 ps
CPU time 3.62 seconds
Started Jul 09 05:50:58 PM PDT 24
Finished Jul 09 05:51:02 PM PDT 24
Peak memory 215748 kb
Host smart-c4b81fd0-bb1d-4d32-af67-6175498e0d22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161473148 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.2161473148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.2216220975
Short name T767
Test name
Test status
Simulation time 416294106981 ps
CPU time 1851.38 seconds
Started Jul 09 05:50:58 PM PDT 24
Finished Jul 09 06:21:50 PM PDT 24
Peak memory 386948 kb
Host smart-d53a4abe-1ce4-4008-8419-b0431539d44d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2216220975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2216220975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.4173489104
Short name T179
Test name
Test status
Simulation time 76108400260 ps
CPU time 1520.11 seconds
Started Jul 09 05:51:00 PM PDT 24
Finished Jul 09 06:16:20 PM PDT 24
Peak memory 391916 kb
Host smart-d94c2250-87c6-40d1-92d1-9d7f26da2dc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4173489104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.4173489104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.1385884338
Short name T464
Test name
Test status
Simulation time 56814044704 ps
CPU time 1234.8 seconds
Started Jul 09 05:50:59 PM PDT 24
Finished Jul 09 06:11:34 PM PDT 24
Peak memory 334580 kb
Host smart-a4ec5e06-be73-4ca4-90ac-a81b26fb6be4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1385884338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.1385884338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.4063460343
Short name T264
Test name
Test status
Simulation time 199256779345 ps
CPU time 913.33 seconds
Started Jul 09 05:50:57 PM PDT 24
Finished Jul 09 06:06:11 PM PDT 24
Peak memory 291192 kb
Host smart-cbcc9671-770b-4726-b1fd-86f968d6cf40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4063460343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.4063460343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.3144016233
Short name T1068
Test name
Test status
Simulation time 2404095713908 ps
CPU time 5258.52 seconds
Started Jul 09 05:50:57 PM PDT 24
Finished Jul 09 07:18:36 PM PDT 24
Peak memory 628680 kb
Host smart-f19ec2a6-768d-46e5-b04d-e55b0c92b4b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3144016233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.3144016233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.3138747987
Short name T962
Test name
Test status
Simulation time 940913345522 ps
CPU time 4154.38 seconds
Started Jul 09 05:50:57 PM PDT 24
Finished Jul 09 07:00:12 PM PDT 24
Peak memory 560228 kb
Host smart-332b0267-6dee-4441-9d26-6c53c71e942d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3138747987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3138747987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.98977362
Short name T931
Test name
Test status
Simulation time 37509723 ps
CPU time 0.77 seconds
Started Jul 09 05:51:10 PM PDT 24
Finished Jul 09 05:51:11 PM PDT 24
Peak memory 205332 kb
Host smart-de76198a-0ea4-4fa6-bfda-3bfe51233819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98977362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.98977362 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.2871572196
Short name T775
Test name
Test status
Simulation time 1107621205 ps
CPU time 59.82 seconds
Started Jul 09 05:51:05 PM PDT 24
Finished Jul 09 05:52:05 PM PDT 24
Peak memory 225748 kb
Host smart-d2cd1504-984f-43b1-ade1-1b5f7f275549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871572196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2871572196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.1218670375
Short name T132
Test name
Test status
Simulation time 31910953170 ps
CPU time 689.38 seconds
Started Jul 09 05:51:02 PM PDT 24
Finished Jul 09 06:02:32 PM PDT 24
Peak memory 232440 kb
Host smart-08406410-e642-4ba5-a26c-423d294a4839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218670375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1218670375 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.364140379
Short name T699
Test name
Test status
Simulation time 1364020973 ps
CPU time 26.83 seconds
Started Jul 09 05:51:05 PM PDT 24
Finished Jul 09 05:51:32 PM PDT 24
Peak memory 220168 kb
Host smart-3ac79356-585b-44c7-9139-548ff3951c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364140379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.364140379 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3283787025
Short name T467
Test name
Test status
Simulation time 6182883148 ps
CPU time 232.96 seconds
Started Jul 09 05:51:06 PM PDT 24
Finished Jul 09 05:54:59 PM PDT 24
Peak memory 256648 kb
Host smart-6cfeaa5a-e1e4-4bb4-a757-ba444c479c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283787025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3283787025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.982087219
Short name T514
Test name
Test status
Simulation time 301009342 ps
CPU time 1.49 seconds
Started Jul 09 05:51:03 PM PDT 24
Finished Jul 09 05:51:05 PM PDT 24
Peak memory 207128 kb
Host smart-a1892e22-f6d1-4ebf-85df-fdf5a9e59cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982087219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.982087219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1373023356
Short name T608
Test name
Test status
Simulation time 185132833 ps
CPU time 1.15 seconds
Started Jul 09 05:51:06 PM PDT 24
Finished Jul 09 05:51:07 PM PDT 24
Peak memory 215580 kb
Host smart-314ac007-1a3d-4f01-8292-2d12d087a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373023356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1373023356 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.2160246799
Short name T492
Test name
Test status
Simulation time 505692587671 ps
CPU time 2527.95 seconds
Started Jul 09 05:51:00 PM PDT 24
Finished Jul 09 06:33:09 PM PDT 24
Peak memory 446912 kb
Host smart-a7eeb879-a0e9-491a-9288-31fa74af28c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160246799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.2160246799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.3299718425
Short name T407
Test name
Test status
Simulation time 53007185881 ps
CPU time 209.81 seconds
Started Jul 09 05:51:00 PM PDT 24
Finished Jul 09 05:54:30 PM PDT 24
Peak memory 235964 kb
Host smart-eaac6f45-87d6-4f7f-b2be-8fed9bb7ee56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299718425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3299718425 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.2821404581
Short name T518
Test name
Test status
Simulation time 9712500620 ps
CPU time 35.75 seconds
Started Jul 09 05:51:01 PM PDT 24
Finished Jul 09 05:51:37 PM PDT 24
Peak memory 223900 kb
Host smart-8711c04d-09fc-4e4e-a9db-f7b0d83473e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821404581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2821404581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.3159213499
Short name T827
Test name
Test status
Simulation time 850553276915 ps
CPU time 1633.34 seconds
Started Jul 09 05:51:06 PM PDT 24
Finished Jul 09 06:18:20 PM PDT 24
Peak memory 395148 kb
Host smart-d2f4fad0-cda2-4a12-b0c5-cb939ffc0762
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3159213499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3159213499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.2313431939
Short name T79
Test name
Test status
Simulation time 764218943 ps
CPU time 4.18 seconds
Started Jul 09 05:51:04 PM PDT 24
Finished Jul 09 05:51:09 PM PDT 24
Peak memory 215668 kb
Host smart-2b9e602c-45ba-448a-a00c-c38fd67bc090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313431939 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.2313431939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.457644698
Short name T897
Test name
Test status
Simulation time 131793424 ps
CPU time 3.84 seconds
Started Jul 09 05:51:03 PM PDT 24
Finished Jul 09 05:51:07 PM PDT 24
Peak memory 215652 kb
Host smart-8ebcd2ce-4339-4ade-99bd-9c8714762265
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457644698 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.kmac_test_vectors_kmac_xof.457644698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.3380853573
Short name T801
Test name
Test status
Simulation time 194904097610 ps
CPU time 1875.43 seconds
Started Jul 09 05:51:00 PM PDT 24
Finished Jul 09 06:22:16 PM PDT 24
Peak memory 371036 kb
Host smart-63914f99-6e85-4951-825d-da3ffa946224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3380853573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.3380853573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.1524282319
Short name T1024
Test name
Test status
Simulation time 424211116394 ps
CPU time 1871.31 seconds
Started Jul 09 05:51:00 PM PDT 24
Finished Jul 09 06:22:11 PM PDT 24
Peak memory 364132 kb
Host smart-85451595-951e-4c5b-843d-36b53b909608
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1524282319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.1524282319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.1985478517
Short name T245
Test name
Test status
Simulation time 195427742258 ps
CPU time 1332.26 seconds
Started Jul 09 05:51:03 PM PDT 24
Finished Jul 09 06:13:16 PM PDT 24
Peak memory 334908 kb
Host smart-53bd6ca9-4bc6-4f63-a681-93df764d32a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1985478517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1985478517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.1117355860
Short name T635
Test name
Test status
Simulation time 19236801192 ps
CPU time 848.78 seconds
Started Jul 09 05:51:04 PM PDT 24
Finished Jul 09 06:05:13 PM PDT 24
Peak memory 297460 kb
Host smart-15cc64d8-193e-4e37-8b30-aaf5ec24366b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1117355860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.1117355860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.2259548643
Short name T885
Test name
Test status
Simulation time 52385491028 ps
CPU time 4188.72 seconds
Started Jul 09 05:51:05 PM PDT 24
Finished Jul 09 07:00:55 PM PDT 24
Peak memory 649156 kb
Host smart-2e596c03-61f5-4eb3-b308-40c64217a7c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2259548643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2259548643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.2782137759
Short name T259
Test name
Test status
Simulation time 225527847838 ps
CPU time 4110.54 seconds
Started Jul 09 05:51:03 PM PDT 24
Finished Jul 09 06:59:34 PM PDT 24
Peak memory 559632 kb
Host smart-d7c0c70d-ddb8-4d38-bdf6-ee44247566de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2782137759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.2782137759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.960961631
Short name T453
Test name
Test status
Simulation time 122487364 ps
CPU time 0.8 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:51:12 PM PDT 24
Peak memory 205324 kb
Host smart-021dee22-be4d-45c2-baae-eea1668fff00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960961631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.960961631 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.715307922
Short name T1038
Test name
Test status
Simulation time 4693145053 ps
CPU time 126.47 seconds
Started Jul 09 05:51:09 PM PDT 24
Finished Jul 09 05:53:16 PM PDT 24
Peak memory 232652 kb
Host smart-b31134d3-b13f-41ee-9a67-ea0f9367bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715307922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.715307922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.272692116
Short name T1025
Test name
Test status
Simulation time 25994806519 ps
CPU time 138.83 seconds
Started Jul 09 05:51:06 PM PDT 24
Finished Jul 09 05:53:26 PM PDT 24
Peak memory 224448 kb
Host smart-ddccd1eb-f847-4c30-8e5b-bba132ae149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272692116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.272692116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.314469274
Short name T787
Test name
Test status
Simulation time 14137608661 ps
CPU time 167.04 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:53:59 PM PDT 24
Peak memory 232632 kb
Host smart-03a9c3e7-e164-4483-9d0c-a8633c2f98fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314469274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.314469274 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.776284903
Short name T996
Test name
Test status
Simulation time 1450705114 ps
CPU time 96.61 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:52:48 PM PDT 24
Peak memory 240328 kb
Host smart-f664df02-16cb-44f1-bdb4-77d772644086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776284903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.776284903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.1559924663
Short name T414
Test name
Test status
Simulation time 583285373 ps
CPU time 3.23 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:51:15 PM PDT 24
Peak memory 207300 kb
Host smart-69aca26b-d057-490c-8197-4c75ca25b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559924663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1559924663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2784812255
Short name T54
Test name
Test status
Simulation time 472138390 ps
CPU time 5.58 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:51:17 PM PDT 24
Peak memory 223888 kb
Host smart-9e3a1456-7f82-4ac5-8a5c-3c96d5abd3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784812255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2784812255 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.1737146018
Short name T438
Test name
Test status
Simulation time 142756965847 ps
CPU time 957.83 seconds
Started Jul 09 05:51:07 PM PDT 24
Finished Jul 09 06:07:06 PM PDT 24
Peak memory 295996 kb
Host smart-305dab95-dd70-4526-910d-9caf17dda4e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737146018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.1737146018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.1344328651
Short name T689
Test name
Test status
Simulation time 57892998218 ps
CPU time 408.57 seconds
Started Jul 09 05:51:10 PM PDT 24
Finished Jul 09 05:57:59 PM PDT 24
Peak memory 247928 kb
Host smart-c0cdd073-fd19-49b7-a912-8e5416a00d17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344328651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1344328651 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.800122751
Short name T1050
Test name
Test status
Simulation time 3216249343 ps
CPU time 26.61 seconds
Started Jul 09 05:51:08 PM PDT 24
Finished Jul 09 05:51:35 PM PDT 24
Peak memory 215756 kb
Host smart-7d883b66-efd7-4250-a9db-a6656045eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800122751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.800122751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.3937114693
Short name T88
Test name
Test status
Simulation time 59858334470 ps
CPU time 2173.71 seconds
Started Jul 09 05:51:09 PM PDT 24
Finished Jul 09 06:27:24 PM PDT 24
Peak memory 482480 kb
Host smart-68cbd6ea-32eb-4e79-a4b4-bebdc840c0d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3937114693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3937114693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.1237557738
Short name T439
Test name
Test status
Simulation time 136000515 ps
CPU time 3.85 seconds
Started Jul 09 05:51:08 PM PDT 24
Finished Jul 09 05:51:12 PM PDT 24
Peak memory 215756 kb
Host smart-c4e7ee67-8597-413b-ac3b-95140de0c403
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237557738 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.1237557738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.2927379054
Short name T180
Test name
Test status
Simulation time 181399723 ps
CPU time 4.98 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:51:16 PM PDT 24
Peak memory 215680 kb
Host smart-c8c5cb78-3a3b-4627-9b02-beddeb8a5359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927379054 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.2927379054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.731988418
Short name T188
Test name
Test status
Simulation time 270293796363 ps
CPU time 1930.91 seconds
Started Jul 09 05:51:10 PM PDT 24
Finished Jul 09 06:23:22 PM PDT 24
Peak memory 391764 kb
Host smart-cc8bfa2e-1eb8-43ce-aedd-8936cdf71272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=731988418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.731988418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.2684702518
Short name T192
Test name
Test status
Simulation time 122833108932 ps
CPU time 1716.05 seconds
Started Jul 09 05:51:07 PM PDT 24
Finished Jul 09 06:19:43 PM PDT 24
Peak memory 368524 kb
Host smart-ba823d9b-ea2e-4507-bc0b-4a1df2bebd8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2684702518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.2684702518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.3018930515
Short name T946
Test name
Test status
Simulation time 290529431086 ps
CPU time 1394.63 seconds
Started Jul 09 05:51:07 PM PDT 24
Finished Jul 09 06:14:22 PM PDT 24
Peak memory 333220 kb
Host smart-9b2ce15b-3d09-4a49-b29a-4524d97c61a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3018930515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3018930515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.2666634247
Short name T824
Test name
Test status
Simulation time 48703628172 ps
CPU time 1002.48 seconds
Started Jul 09 05:51:08 PM PDT 24
Finished Jul 09 06:07:51 PM PDT 24
Peak memory 293924 kb
Host smart-74369a85-4cfb-4d84-9bc6-ee7d2b95626c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2666634247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.2666634247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.481495020
Short name T372
Test name
Test status
Simulation time 298304417915 ps
CPU time 4115.74 seconds
Started Jul 09 05:51:08 PM PDT 24
Finished Jul 09 06:59:44 PM PDT 24
Peak memory 564888 kb
Host smart-8fa59d93-bd27-4679-944b-415bcf53f7a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=481495020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.481495020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.2829583750
Short name T441
Test name
Test status
Simulation time 14234749 ps
CPU time 0.78 seconds
Started Jul 09 05:51:23 PM PDT 24
Finished Jul 09 05:51:25 PM PDT 24
Peak memory 205172 kb
Host smart-60ff631e-acf9-4d82-934b-9a7fb06d9281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829583750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2829583750 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.914551289
Short name T1001
Test name
Test status
Simulation time 3488117045 ps
CPU time 45.2 seconds
Started Jul 09 05:51:15 PM PDT 24
Finished Jul 09 05:52:00 PM PDT 24
Peak memory 223868 kb
Host smart-5f42cd31-b209-453d-8236-e6549b830953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914551289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.914551289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.2397516287
Short name T721
Test name
Test status
Simulation time 42391229545 ps
CPU time 480.9 seconds
Started Jul 09 05:51:14 PM PDT 24
Finished Jul 09 05:59:16 PM PDT 24
Peak memory 230168 kb
Host smart-2778b917-d8b4-4e01-8f1b-358cf20c95b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397516287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2397516287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.822402911
Short name T633
Test name
Test status
Simulation time 13031604898 ps
CPU time 145.1 seconds
Started Jul 09 05:51:15 PM PDT 24
Finished Jul 09 05:53:40 PM PDT 24
Peak memory 236628 kb
Host smart-838ba9d9-89dc-4a30-9e22-2cb75889e0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822402911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.822402911 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.723325811
Short name T609
Test name
Test status
Simulation time 15563468257 ps
CPU time 112.83 seconds
Started Jul 09 05:51:16 PM PDT 24
Finished Jul 09 05:53:09 PM PDT 24
Peak memory 240288 kb
Host smart-337be4d0-5ffd-4054-a018-c715e2222e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723325811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.723325811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.867813081
Short name T591
Test name
Test status
Simulation time 705400021 ps
CPU time 3.83 seconds
Started Jul 09 05:51:19 PM PDT 24
Finished Jul 09 05:51:23 PM PDT 24
Peak memory 207396 kb
Host smart-1c5cb529-e7ef-48a2-8cf1-4414fec23e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867813081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.867813081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1767748740
Short name T199
Test name
Test status
Simulation time 10151072721 ps
CPU time 419.61 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:58:11 PM PDT 24
Peak memory 265012 kb
Host smart-2d2cb819-0fb7-4beb-b70f-11f7469d11bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767748740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1767748740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3418582630
Short name T174
Test name
Test status
Simulation time 1858250594 ps
CPU time 15.55 seconds
Started Jul 09 05:51:15 PM PDT 24
Finished Jul 09 05:51:31 PM PDT 24
Peak memory 223516 kb
Host smart-5b859997-11b3-420b-a261-5fef497b0cde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418582630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3418582630 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.2738708561
Short name T565
Test name
Test status
Simulation time 625700019 ps
CPU time 15.84 seconds
Started Jul 09 05:51:11 PM PDT 24
Finished Jul 09 05:51:27 PM PDT 24
Peak memory 223840 kb
Host smart-8a6936a5-6f98-4e5b-8036-1ffb50439b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738708561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2738708561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.27719528
Short name T488
Test name
Test status
Simulation time 45318268454 ps
CPU time 287.51 seconds
Started Jul 09 05:51:20 PM PDT 24
Finished Jul 09 05:56:08 PM PDT 24
Peak memory 273232 kb
Host smart-2eed7d6f-0af7-491b-a785-c38665356aa7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=27719528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.27719528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.3548556959
Short name T887
Test name
Test status
Simulation time 69012180 ps
CPU time 3.99 seconds
Started Jul 09 05:51:14 PM PDT 24
Finished Jul 09 05:51:19 PM PDT 24
Peak memory 215752 kb
Host smart-a2178b93-0fb6-4dd1-aaa5-1e37c63dbf90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548556959 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.3548556959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.76087009
Short name T842
Test name
Test status
Simulation time 71160263 ps
CPU time 4.38 seconds
Started Jul 09 05:51:17 PM PDT 24
Finished Jul 09 05:51:21 PM PDT 24
Peak memory 215684 kb
Host smart-a158e669-b790-4567-aa0d-afad8aadd576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76087009 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.kmac_test_vectors_kmac_xof.76087009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.1343779039
Short name T953
Test name
Test status
Simulation time 820639948255 ps
CPU time 2104.69 seconds
Started Jul 09 05:51:13 PM PDT 24
Finished Jul 09 06:26:19 PM PDT 24
Peak memory 397076 kb
Host smart-5da3f110-16b7-4e09-a111-4d3a69462ef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1343779039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.1343779039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.2916045711
Short name T614
Test name
Test status
Simulation time 63431604373 ps
CPU time 1668.34 seconds
Started Jul 09 05:51:13 PM PDT 24
Finished Jul 09 06:19:03 PM PDT 24
Peak memory 387588 kb
Host smart-d05d44fe-d1e2-4ea6-9f00-bddb3f304366
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2916045711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.2916045711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.3869144340
Short name T1055
Test name
Test status
Simulation time 126493270939 ps
CPU time 1343.81 seconds
Started Jul 09 05:51:16 PM PDT 24
Finished Jul 09 06:13:41 PM PDT 24
Peak memory 332700 kb
Host smart-e4c4a2a0-80a6-47ce-8ed2-c0ae613f7560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3869144340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3869144340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3152452093
Short name T1077
Test name
Test status
Simulation time 34071133111 ps
CPU time 848.17 seconds
Started Jul 09 05:51:13 PM PDT 24
Finished Jul 09 06:05:22 PM PDT 24
Peak memory 291564 kb
Host smart-9d3f58b0-046c-4bdb-bb1e-a713b45840fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3152452093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.3152452093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1341620237
Short name T265
Test name
Test status
Simulation time 172277891797 ps
CPU time 4661.81 seconds
Started Jul 09 05:51:15 PM PDT 24
Finished Jul 09 07:08:58 PM PDT 24
Peak memory 652812 kb
Host smart-7f4cdf91-5ad8-4f1b-9387-88519d284c82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1341620237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1341620237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.475683655
Short name T620
Test name
Test status
Simulation time 708622905321 ps
CPU time 4626.59 seconds
Started Jul 09 05:51:14 PM PDT 24
Finished Jul 09 07:08:22 PM PDT 24
Peak memory 573588 kb
Host smart-8c54df02-0f52-42d3-bccf-99d060aa6206
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=475683655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.475683655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.3860655220
Short name T649
Test name
Test status
Simulation time 118675770 ps
CPU time 0.78 seconds
Started Jul 09 05:49:54 PM PDT 24
Finished Jul 09 05:49:56 PM PDT 24
Peak memory 205356 kb
Host smart-b739c90d-b5a3-4e49-9f3d-5f228312cc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860655220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3860655220 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.3421382817
Short name T561
Test name
Test status
Simulation time 12398055115 ps
CPU time 150.67 seconds
Started Jul 09 05:49:37 PM PDT 24
Finished Jul 09 05:52:08 PM PDT 24
Peak memory 236020 kb
Host smart-fe7b87d1-3dd2-4827-8b7a-44d6d8b325ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421382817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3421382817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.847707771
Short name T255
Test name
Test status
Simulation time 50547091720 ps
CPU time 238.84 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:53:50 PM PDT 24
Peak memory 240064 kb
Host smart-e7158eab-837a-4431-a91a-9481b0614c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847707771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.847707771 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.445294721
Short name T948
Test name
Test status
Simulation time 24322366439 ps
CPU time 145.64 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 05:52:13 PM PDT 24
Peak memory 224044 kb
Host smart-5f097fef-a50c-4c2b-97c5-8a5b7915877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445294721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.445294721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.2223508912
Short name T297
Test name
Test status
Simulation time 3779830057 ps
CPU time 24.71 seconds
Started Jul 09 05:49:28 PM PDT 24
Finished Jul 09 05:49:54 PM PDT 24
Peak memory 224144 kb
Host smart-28ed2cd5-e9c3-4e07-8daf-1297aeea9e4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2223508912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2223508912 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1758421946
Short name T1019
Test name
Test status
Simulation time 536980160 ps
CPU time 29.14 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:50:22 PM PDT 24
Peak memory 220772 kb
Host smart-307e63f0-262f-45a7-841a-c236aa614030
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1758421946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1758421946 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.2177540577
Short name T562
Test name
Test status
Simulation time 9276263373 ps
CPU time 56.23 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 05:50:31 PM PDT 24
Peak memory 215720 kb
Host smart-39871e7f-2e91-40c6-8860-3d60b3b38bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177540577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2177540577 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.2553235860
Short name T285
Test name
Test status
Simulation time 69856871016 ps
CPU time 68.87 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 05:50:53 PM PDT 24
Peak memory 225460 kb
Host smart-0456e0b7-5bfb-4545-bf43-ce745672879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553235860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2553235860 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.1834545162
Short name T926
Test name
Test status
Simulation time 31016692013 ps
CPU time 167.64 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 05:52:20 PM PDT 24
Peak memory 251612 kb
Host smart-46ddb30a-b475-4c90-b77e-e5721f63e029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834545162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1834545162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.2234107484
Short name T468
Test name
Test status
Simulation time 1548798786 ps
CPU time 4.48 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 05:49:37 PM PDT 24
Peak memory 215560 kb
Host smart-354971ea-359f-4e31-bda1-86a5cf15ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234107484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2234107484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.3576706019
Short name T320
Test name
Test status
Simulation time 217555924 ps
CPU time 5.09 seconds
Started Jul 09 05:49:31 PM PDT 24
Finished Jul 09 05:49:36 PM PDT 24
Peak memory 220572 kb
Host smart-fdae8c0b-a971-4d60-a805-0805c090edd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576706019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3576706019 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2506190151
Short name T664
Test name
Test status
Simulation time 132415539586 ps
CPU time 1385.65 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 06:12:39 PM PDT 24
Peak memory 345628 kb
Host smart-17de39fd-cf7b-4bc2-9a4f-03cbc6ec6864
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506190151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2506190151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.265048385
Short name T832
Test name
Test status
Simulation time 19852173434 ps
CPU time 237.28 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 05:53:37 PM PDT 24
Peak memory 245636 kb
Host smart-046a8d47-c64e-4bcc-bd48-a1159b971b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265048385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.265048385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.3846131651
Short name T12
Test name
Test status
Simulation time 11536557254 ps
CPU time 70.89 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:50:56 PM PDT 24
Peak memory 274068 kb
Host smart-c89eeb8d-3ed0-470d-8b7d-1a01f29192d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846131651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3846131651 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.340785153
Short name T986
Test name
Test status
Simulation time 14310180605 ps
CPU time 395.3 seconds
Started Jul 09 05:49:33 PM PDT 24
Finished Jul 09 05:56:09 PM PDT 24
Peak memory 251568 kb
Host smart-7d047810-829a-468f-805e-e46fccda1d17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340785153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.340785153 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1870526509
Short name T651
Test name
Test status
Simulation time 3096667304 ps
CPU time 47.26 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 05:50:20 PM PDT 24
Peak memory 218672 kb
Host smart-0d953b3c-b3a7-4c51-8382-65e7037f017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870526509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1870526509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.3043600069
Short name T602
Test name
Test status
Simulation time 6758804969 ps
CPU time 158.12 seconds
Started Jul 09 05:49:51 PM PDT 24
Finished Jul 09 05:52:33 PM PDT 24
Peak memory 257924 kb
Host smart-70110165-1754-4331-bf74-d03264819beb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3043600069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3043600069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.2723009262
Short name T359
Test name
Test status
Simulation time 150520848 ps
CPU time 4 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 05:49:58 PM PDT 24
Peak memory 215732 kb
Host smart-b43f90fa-1975-4a41-bf8a-10d513836a39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723009262 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.2723009262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1107203866
Short name T598
Test name
Test status
Simulation time 259688010 ps
CPU time 4.79 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 05:49:48 PM PDT 24
Peak memory 215644 kb
Host smart-02ec6c95-8bb0-44a3-acce-17e3743f5bf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107203866 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1107203866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.467691448
Short name T781
Test name
Test status
Simulation time 188820480927 ps
CPU time 1555.93 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 06:15:40 PM PDT 24
Peak memory 393228 kb
Host smart-7c7a3f34-a417-46df-b1de-dc0f76cef571
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=467691448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.467691448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.2436929858
Short name T728
Test name
Test status
Simulation time 70567454448 ps
CPU time 1411.37 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:13:20 PM PDT 24
Peak memory 372144 kb
Host smart-48535b93-cb05-49b7-bc5b-31a20d9c529a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2436929858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2436929858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.184443310
Short name T362
Test name
Test status
Simulation time 94299342669 ps
CPU time 1427.14 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 06:13:37 PM PDT 24
Peak memory 336756 kb
Host smart-558b37ab-8b00-4de9-a29c-0c6b7856ff10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=184443310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.184443310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1366500985
Short name T451
Test name
Test status
Simulation time 41002176988 ps
CPU time 742.76 seconds
Started Jul 09 05:49:30 PM PDT 24
Finished Jul 09 06:01:53 PM PDT 24
Peak memory 293444 kb
Host smart-219dc693-2461-4624-b9e5-201be4e53561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1366500985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1366500985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.2059599937
Short name T855
Test name
Test status
Simulation time 1036668261534 ps
CPU time 4936.01 seconds
Started Jul 09 05:49:37 PM PDT 24
Finished Jul 09 07:11:54 PM PDT 24
Peak memory 660216 kb
Host smart-fefc50a3-41ee-4186-8b4e-86a8cbda42bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2059599937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2059599937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.1125098075
Short name T576
Test name
Test status
Simulation time 433607099835 ps
CPU time 4197.15 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 06:59:43 PM PDT 24
Peak memory 560660 kb
Host smart-8a43a017-fd82-4fe6-b588-a36fd499cb8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1125098075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1125098075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2603020816
Short name T709
Test name
Test status
Simulation time 24769658 ps
CPU time 0.81 seconds
Started Jul 09 05:51:21 PM PDT 24
Finished Jul 09 05:51:22 PM PDT 24
Peak memory 205364 kb
Host smart-b45aeced-4c8b-49f2-9b3f-df1a1dfe6743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603020816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2603020816 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.1167673494
Short name T717
Test name
Test status
Simulation time 3492542511 ps
CPU time 181.27 seconds
Started Jul 09 05:51:20 PM PDT 24
Finished Jul 09 05:54:21 PM PDT 24
Peak memory 239148 kb
Host smart-068b9f5b-d62d-4460-ae13-2e1b92ad2b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167673494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1167673494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3165941039
Short name T678
Test name
Test status
Simulation time 3841672073 ps
CPU time 160.39 seconds
Started Jul 09 05:51:20 PM PDT 24
Finished Jul 09 05:54:00 PM PDT 24
Peak memory 223544 kb
Host smart-a82c2ec5-aa0f-463e-b33e-474779412487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165941039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3165941039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1769178365
Short name T379
Test name
Test status
Simulation time 6466907986 ps
CPU time 121.7 seconds
Started Jul 09 05:51:21 PM PDT 24
Finished Jul 09 05:53:23 PM PDT 24
Peak memory 231316 kb
Host smart-e48d6ddd-aa50-442e-888a-156c5004fd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769178365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1769178365 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1338093476
Short name T1073
Test name
Test status
Simulation time 30458295119 ps
CPU time 293.98 seconds
Started Jul 09 05:51:21 PM PDT 24
Finished Jul 09 05:56:16 PM PDT 24
Peak memory 248496 kb
Host smart-6d713dc5-b741-472d-8234-9c11c9146cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338093476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1338093476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.3785125084
Short name T1074
Test name
Test status
Simulation time 7426212480 ps
CPU time 7.46 seconds
Started Jul 09 05:51:19 PM PDT 24
Finished Jul 09 05:51:27 PM PDT 24
Peak memory 207464 kb
Host smart-53481a79-28a5-4bd8-93cc-9679b05a4a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785125084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3785125084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.1843480041
Short name T284
Test name
Test status
Simulation time 49851144 ps
CPU time 1.39 seconds
Started Jul 09 05:51:21 PM PDT 24
Finished Jul 09 05:51:23 PM PDT 24
Peak memory 215504 kb
Host smart-8012b9ac-6eb4-4ef1-beed-da68f4ba6ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843480041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1843480041 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3642357860
Short name T429
Test name
Test status
Simulation time 267542648494 ps
CPU time 1173.05 seconds
Started Jul 09 05:51:18 PM PDT 24
Finished Jul 09 06:10:51 PM PDT 24
Peak memory 320172 kb
Host smart-f7e0d1ac-1021-44eb-aa27-70cf06dd49a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642357860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3642357860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.4135002750
Short name T880
Test name
Test status
Simulation time 326195474 ps
CPU time 23.96 seconds
Started Jul 09 05:51:23 PM PDT 24
Finished Jul 09 05:51:47 PM PDT 24
Peak memory 223836 kb
Host smart-3493b867-1073-4344-b74c-2db25561d22a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135002750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.4135002750 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2389996508
Short name T345
Test name
Test status
Simulation time 1432260235 ps
CPU time 21.32 seconds
Started Jul 09 05:51:17 PM PDT 24
Finished Jul 09 05:51:39 PM PDT 24
Peak memory 223844 kb
Host smart-2f8a5f7c-9f9e-4ee0-a2fb-f463a9af6453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389996508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2389996508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1392532713
Short name T557
Test name
Test status
Simulation time 6153463595 ps
CPU time 396.64 seconds
Started Jul 09 05:51:19 PM PDT 24
Finished Jul 09 05:57:57 PM PDT 24
Peak memory 288344 kb
Host smart-801b584a-88dd-455d-870e-59b69ed4f67e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1392532713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1392532713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.1787257311
Short name T973
Test name
Test status
Simulation time 372636409 ps
CPU time 4.63 seconds
Started Jul 09 05:51:18 PM PDT 24
Finished Jul 09 05:51:23 PM PDT 24
Peak memory 215672 kb
Host smart-6fb6cf96-37b8-4751-bc5d-c2062fddce17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787257311 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.1787257311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2015697688
Short name T685
Test name
Test status
Simulation time 69073164 ps
CPU time 3.81 seconds
Started Jul 09 05:51:17 PM PDT 24
Finished Jul 09 05:51:22 PM PDT 24
Peak memory 215912 kb
Host smart-9857a0e5-cb98-4cfa-b9e8-fc43a926a59f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015697688 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2015697688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.1923454594
Short name T903
Test name
Test status
Simulation time 99999655976 ps
CPU time 2039.14 seconds
Started Jul 09 05:51:20 PM PDT 24
Finished Jul 09 06:25:20 PM PDT 24
Peak memory 399308 kb
Host smart-c66c9b21-8886-4e03-8a1d-2aab1a2d4f9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1923454594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.1923454594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.2232842525
Short name T712
Test name
Test status
Simulation time 92097314463 ps
CPU time 1731.74 seconds
Started Jul 09 05:51:21 PM PDT 24
Finished Jul 09 06:20:14 PM PDT 24
Peak memory 362308 kb
Host smart-4e9e8811-f88f-4da5-8bad-04871cdd6fb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2232842525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2232842525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.3938581503
Short name T193
Test name
Test status
Simulation time 53590112289 ps
CPU time 1059.93 seconds
Started Jul 09 05:51:20 PM PDT 24
Finished Jul 09 06:09:01 PM PDT 24
Peak memory 330160 kb
Host smart-178892b4-2568-46b7-8de9-dd71288297ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3938581503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.3938581503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.988198754
Short name T287
Test name
Test status
Simulation time 33609133017 ps
CPU time 869.19 seconds
Started Jul 09 05:51:23 PM PDT 24
Finished Jul 09 06:05:53 PM PDT 24
Peak memory 292000 kb
Host smart-3205334e-ae80-4608-acc7-61aeb24780fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=988198754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.988198754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1218319727
Short name T818
Test name
Test status
Simulation time 340823574417 ps
CPU time 4393.41 seconds
Started Jul 09 05:51:22 PM PDT 24
Finished Jul 09 07:04:37 PM PDT 24
Peak memory 642076 kb
Host smart-b71cb44e-63eb-41d4-8014-614ecbe47a46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1218319727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1218319727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.2126668239
Short name T237
Test name
Test status
Simulation time 43327963590 ps
CPU time 3200.36 seconds
Started Jul 09 05:51:23 PM PDT 24
Finished Jul 09 06:44:44 PM PDT 24
Peak memory 561384 kb
Host smart-e68c69a6-da99-4ae9-b50a-047d7d9055f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2126668239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.2126668239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.2656125382
Short name T677
Test name
Test status
Simulation time 64298888 ps
CPU time 0.78 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 05:51:31 PM PDT 24
Peak memory 205356 kb
Host smart-f5135d7a-f768-4d3c-8323-e9f679f16927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656125382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2656125382 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_burst_write.216510376
Short name T1015
Test name
Test status
Simulation time 15877166235 ps
CPU time 127.32 seconds
Started Jul 09 05:51:20 PM PDT 24
Finished Jul 09 05:53:27 PM PDT 24
Peak memory 222356 kb
Host smart-b9f345cc-95aa-4dcb-b3ac-4baeb05b1677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216510376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.216510376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2220219939
Short name T342
Test name
Test status
Simulation time 73948175320 ps
CPU time 282.31 seconds
Started Jul 09 05:51:25 PM PDT 24
Finished Jul 09 05:56:08 PM PDT 24
Peak memory 243448 kb
Host smart-67a25073-5c2b-41e6-ac25-556bca1d3162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220219939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2220219939 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.356285805
Short name T470
Test name
Test status
Simulation time 4201241929 ps
CPU time 153.98 seconds
Started Jul 09 05:51:24 PM PDT 24
Finished Jul 09 05:53:58 PM PDT 24
Peak memory 246356 kb
Host smart-505aca08-a821-49e5-972a-76cc175d9672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356285805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.356285805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1353486007
Short name T307
Test name
Test status
Simulation time 3186355401 ps
CPU time 4.41 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 05:51:35 PM PDT 24
Peak memory 215652 kb
Host smart-ce2309f2-2915-4371-a95c-bdad1cda3b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353486007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1353486007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.2496190195
Short name T1011
Test name
Test status
Simulation time 123210496 ps
CPU time 1.28 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 05:51:32 PM PDT 24
Peak memory 216596 kb
Host smart-0f4b413f-0529-4ffc-925e-2e6182651a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496190195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2496190195 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.4161629295
Short name T261
Test name
Test status
Simulation time 431901730338 ps
CPU time 1079.08 seconds
Started Jul 09 05:51:19 PM PDT 24
Finished Jul 09 06:09:19 PM PDT 24
Peak memory 320732 kb
Host smart-91b1505c-bab7-4b5c-881f-248eecc7e245
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161629295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.4161629295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.4275505034
Short name T251
Test name
Test status
Simulation time 296222798 ps
CPU time 8.99 seconds
Started Jul 09 05:51:19 PM PDT 24
Finished Jul 09 05:51:29 PM PDT 24
Peak memory 219764 kb
Host smart-518fd5b1-ee86-421a-9f3c-239814c6fa98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275505034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.4275505034 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.648274061
Short name T928
Test name
Test status
Simulation time 12368975222 ps
CPU time 59.23 seconds
Started Jul 09 05:51:19 PM PDT 24
Finished Jul 09 05:52:19 PM PDT 24
Peak memory 215736 kb
Host smart-44c17f22-76fc-4918-b702-174db49d9776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648274061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.648274061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.2057236629
Short name T821
Test name
Test status
Simulation time 2136125939 ps
CPU time 4.88 seconds
Started Jul 09 05:51:25 PM PDT 24
Finished Jul 09 05:51:30 PM PDT 24
Peak memory 215644 kb
Host smart-7ac29e7c-f048-439a-b6ec-94d322a6b463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057236629 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.2057236629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.18166582
Short name T632
Test name
Test status
Simulation time 550128586 ps
CPU time 4.17 seconds
Started Jul 09 05:51:24 PM PDT 24
Finished Jul 09 05:51:28 PM PDT 24
Peak memory 215660 kb
Host smart-ebec233a-e371-4879-81e6-b77504ee3256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18166582 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.kmac_test_vectors_kmac_xof.18166582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.774151168
Short name T859
Test name
Test status
Simulation time 538759528468 ps
CPU time 1865.53 seconds
Started Jul 09 05:51:26 PM PDT 24
Finished Jul 09 06:22:32 PM PDT 24
Peak memory 390620 kb
Host smart-6e04de78-4265-4798-900d-e3d04ff15cd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=774151168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.774151168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.123878103
Short name T955
Test name
Test status
Simulation time 164017992458 ps
CPU time 1890.15 seconds
Started Jul 09 05:51:23 PM PDT 24
Finished Jul 09 06:22:54 PM PDT 24
Peak memory 370860 kb
Host smart-44dadbf7-e169-4c5b-b843-6f247461df8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=123878103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.123878103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.2244475185
Short name T959
Test name
Test status
Simulation time 68065918628 ps
CPU time 1227.04 seconds
Started Jul 09 05:51:22 PM PDT 24
Finished Jul 09 06:11:49 PM PDT 24
Peak memory 334836 kb
Host smart-c1ea9309-67ba-40ff-9168-6918c084db3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2244475185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2244475185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.714889121
Short name T1020
Test name
Test status
Simulation time 32469797734 ps
CPU time 926.8 seconds
Started Jul 09 05:51:25 PM PDT 24
Finished Jul 09 06:06:52 PM PDT 24
Peak memory 293568 kb
Host smart-f92be6f4-f376-4082-97fd-209de08029e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=714889121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.714889121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.811767456
Short name T791
Test name
Test status
Simulation time 1070055798514 ps
CPU time 5613.65 seconds
Started Jul 09 05:51:25 PM PDT 24
Finished Jul 09 07:24:59 PM PDT 24
Peak memory 651020 kb
Host smart-fa4c8ae2-ef94-4746-9989-d218a65e6b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=811767456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.811767456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.3141484977
Short name T813
Test name
Test status
Simulation time 543908585620 ps
CPU time 3283.83 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 06:46:15 PM PDT 24
Peak memory 566008 kb
Host smart-e11fe7b6-00dd-4b17-ae56-f4f52f3f8491
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3141484977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3141484977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.1950872490
Short name T38
Test name
Test status
Simulation time 14212875 ps
CPU time 0.75 seconds
Started Jul 09 05:51:36 PM PDT 24
Finished Jul 09 05:51:38 PM PDT 24
Peak memory 205280 kb
Host smart-d35d7953-0db7-43ac-977b-54ed97647c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950872490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1950872490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.4242749543
Short name T1028
Test name
Test status
Simulation time 2910938806 ps
CPU time 14.49 seconds
Started Jul 09 05:51:37 PM PDT 24
Finished Jul 09 05:51:53 PM PDT 24
Peak memory 217636 kb
Host smart-8df6c83e-23c0-4393-8769-89a2f1cddbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242749543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.4242749543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.4123200223
Short name T826
Test name
Test status
Simulation time 1643584255 ps
CPU time 43.04 seconds
Started Jul 09 05:51:31 PM PDT 24
Finished Jul 09 05:52:14 PM PDT 24
Peak memory 219208 kb
Host smart-d203f9cb-12df-4f3f-8dc3-2407ef6c2b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123200223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.4123200223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.301785688
Short name T338
Test name
Test status
Simulation time 32518527567 ps
CPU time 181.71 seconds
Started Jul 09 05:51:37 PM PDT 24
Finished Jul 09 05:54:40 PM PDT 24
Peak memory 237068 kb
Host smart-891f3479-2121-4085-b406-9427d36ec9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301785688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.301785688 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.541292356
Short name T373
Test name
Test status
Simulation time 13247721830 ps
CPU time 116.98 seconds
Started Jul 09 05:51:36 PM PDT 24
Finished Jul 09 05:53:33 PM PDT 24
Peak memory 248500 kb
Host smart-4731d21b-1bb3-4997-8e65-bcf198e66086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541292356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.541292356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.1115197549
Short name T974
Test name
Test status
Simulation time 538079860 ps
CPU time 2.14 seconds
Started Jul 09 05:51:37 PM PDT 24
Finished Jul 09 05:51:40 PM PDT 24
Peak memory 207236 kb
Host smart-b0cd5cc7-617c-4bfb-93c6-91d19c5022fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115197549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1115197549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3098938765
Short name T56
Test name
Test status
Simulation time 882409324 ps
CPU time 14.75 seconds
Started Jul 09 05:51:34 PM PDT 24
Finished Jul 09 05:51:49 PM PDT 24
Peak memory 232124 kb
Host smart-d61fa186-8d45-4b6b-8c06-c83d0584896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098938765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3098938765 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.3778205912
Short name T288
Test name
Test status
Simulation time 96509811961 ps
CPU time 2088.24 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 06:26:19 PM PDT 24
Peak memory 408340 kb
Host smart-38d49198-9bc8-4614-8498-37768ca88788
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778205912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.3778205912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.2095273288
Short name T374
Test name
Test status
Simulation time 14066873907 ps
CPU time 93.53 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 05:53:04 PM PDT 24
Peak memory 227808 kb
Host smart-8e870e4f-f2d7-4860-bf17-db8a1bfbad61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095273288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2095273288 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3418602554
Short name T394
Test name
Test status
Simulation time 634555446 ps
CPU time 10.75 seconds
Started Jul 09 05:51:29 PM PDT 24
Finished Jul 09 05:51:40 PM PDT 24
Peak memory 219224 kb
Host smart-8bde3621-bd4c-40a3-a88d-698df829572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418602554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3418602554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3926411294
Short name T84
Test name
Test status
Simulation time 166010424878 ps
CPU time 1954.23 seconds
Started Jul 09 05:51:34 PM PDT 24
Finished Jul 09 06:24:09 PM PDT 24
Peak memory 432428 kb
Host smart-ea2983f9-7800-4389-a4e6-e49b6cbb0d48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3926411294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3926411294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.31010786
Short name T617
Test name
Test status
Simulation time 495181439 ps
CPU time 4.53 seconds
Started Jul 09 05:51:33 PM PDT 24
Finished Jul 09 05:51:38 PM PDT 24
Peak memory 215764 kb
Host smart-22414091-723e-4d75-b19a-97fe3795cff3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31010786 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.kmac_test_vectors_kmac.31010786 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.3665924186
Short name T919
Test name
Test status
Simulation time 293321485 ps
CPU time 4.41 seconds
Started Jul 09 05:51:34 PM PDT 24
Finished Jul 09 05:51:39 PM PDT 24
Peak memory 215664 kb
Host smart-ec67731a-9543-4b33-85f3-87a463d9943a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665924186 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.3665924186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.1076857200
Short name T999
Test name
Test status
Simulation time 189077481383 ps
CPU time 1900.76 seconds
Started Jul 09 05:51:30 PM PDT 24
Finished Jul 09 06:23:12 PM PDT 24
Peak memory 389504 kb
Host smart-505295a2-48be-4f04-be86-d936afd262dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1076857200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.1076857200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.1901206719
Short name T738
Test name
Test status
Simulation time 36281951258 ps
CPU time 1585.01 seconds
Started Jul 09 05:51:31 PM PDT 24
Finished Jul 09 06:17:57 PM PDT 24
Peak memory 375012 kb
Host smart-ce31298a-dd94-47d1-98af-6ffa2a57005b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1901206719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.1901206719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2680344352
Short name T422
Test name
Test status
Simulation time 357961655694 ps
CPU time 1293.18 seconds
Started Jul 09 05:51:37 PM PDT 24
Finished Jul 09 06:13:11 PM PDT 24
Peak memory 332644 kb
Host smart-26dfe190-d7bf-4bb4-9136-64041694cfd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2680344352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2680344352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.3707340224
Short name T299
Test name
Test status
Simulation time 360693737937 ps
CPU time 894.3 seconds
Started Jul 09 05:51:31 PM PDT 24
Finished Jul 09 06:06:26 PM PDT 24
Peak memory 293900 kb
Host smart-8ea10164-b9a6-475b-a5ab-fbf91fa89e71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3707340224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3707340224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.335367601
Short name T408
Test name
Test status
Simulation time 187485313429 ps
CPU time 4214.97 seconds
Started Jul 09 05:51:33 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 645120 kb
Host smart-66bfac29-0d3b-4884-95e1-3c58cea8c65e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=335367601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.335367601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.3221272428
Short name T198
Test name
Test status
Simulation time 182792448913 ps
CPU time 3470.57 seconds
Started Jul 09 05:51:31 PM PDT 24
Finished Jul 09 06:49:22 PM PDT 24
Peak memory 573168 kb
Host smart-fcca1778-3bd8-49c7-b4dc-820f926d3f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3221272428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.3221272428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.728849974
Short name T324
Test name
Test status
Simulation time 46281389 ps
CPU time 0.82 seconds
Started Jul 09 05:51:47 PM PDT 24
Finished Jul 09 05:51:48 PM PDT 24
Peak memory 205352 kb
Host smart-87eb52c2-d833-40fd-b002-82b44d5f75ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728849974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.728849974 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.2978299667
Short name T1007
Test name
Test status
Simulation time 48206238849 ps
CPU time 262.31 seconds
Started Jul 09 05:51:48 PM PDT 24
Finished Jul 09 05:56:11 PM PDT 24
Peak memory 245972 kb
Host smart-87f44b15-1948-4945-9e7d-268174a7006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978299667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2978299667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.4127989589
Short name T169
Test name
Test status
Simulation time 5266011312 ps
CPU time 416.22 seconds
Started Jul 09 05:51:39 PM PDT 24
Finished Jul 09 05:58:36 PM PDT 24
Peak memory 231428 kb
Host smart-9635ed41-ec20-4cd6-9518-33f66029999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127989589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.4127989589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1151435226
Short name T201
Test name
Test status
Simulation time 14948918131 ps
CPU time 266.41 seconds
Started Jul 09 05:51:42 PM PDT 24
Finished Jul 09 05:56:09 PM PDT 24
Peak memory 243140 kb
Host smart-8b073fb7-0be5-43cc-8dcb-c35b44c56bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151435226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1151435226 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.4038426580
Short name T544
Test name
Test status
Simulation time 3700036104 ps
CPU time 42.68 seconds
Started Jul 09 05:51:42 PM PDT 24
Finished Jul 09 05:52:25 PM PDT 24
Peak memory 233060 kb
Host smart-1bef5efe-6416-4f80-aa3e-7eed6b44a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038426580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.4038426580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.297914979
Short name T724
Test name
Test status
Simulation time 903306249 ps
CPU time 1.75 seconds
Started Jul 09 05:51:43 PM PDT 24
Finished Jul 09 05:51:45 PM PDT 24
Peak memory 207344 kb
Host smart-b7b076d0-79ae-4791-ad4e-74476f1eacb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297914979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.297914979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1497543915
Short name T572
Test name
Test status
Simulation time 14525545926 ps
CPU time 13.65 seconds
Started Jul 09 05:51:42 PM PDT 24
Finished Jul 09 05:51:56 PM PDT 24
Peak memory 228636 kb
Host smart-1afed195-edfc-460d-942c-c8d14fb7a9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497543915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1497543915 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.4130927570
Short name T691
Test name
Test status
Simulation time 32456927158 ps
CPU time 226.39 seconds
Started Jul 09 05:51:43 PM PDT 24
Finished Jul 09 05:55:30 PM PDT 24
Peak memory 237376 kb
Host smart-41313b0e-52e2-43cd-a7c0-195357b0b135
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130927570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.4130927570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.3387811149
Short name T612
Test name
Test status
Simulation time 3539181633 ps
CPU time 274.33 seconds
Started Jul 09 05:51:40 PM PDT 24
Finished Jul 09 05:56:15 PM PDT 24
Peak memory 245764 kb
Host smart-3369fabe-cf15-4506-b7be-416a4631c836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387811149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3387811149 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.1801757158
Short name T599
Test name
Test status
Simulation time 230373052 ps
CPU time 6.11 seconds
Started Jul 09 05:51:37 PM PDT 24
Finished Jul 09 05:51:44 PM PDT 24
Peak memory 220048 kb
Host smart-a829bc64-b389-4ced-9f35-3ba66fd86e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801757158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1801757158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.4054157878
Short name T923
Test name
Test status
Simulation time 234283502155 ps
CPU time 1057.02 seconds
Started Jul 09 05:51:45 PM PDT 24
Finished Jul 09 06:09:22 PM PDT 24
Peak memory 347040 kb
Host smart-07e8f036-056e-483c-9a09-a58f3902072b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4054157878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.4054157878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.833430895
Short name T694
Test name
Test status
Simulation time 164905011 ps
CPU time 4.56 seconds
Started Jul 09 05:51:39 PM PDT 24
Finished Jul 09 05:51:44 PM PDT 24
Peak memory 215660 kb
Host smart-ae24c2fd-63cc-4b2d-aae0-db83a16ee798
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833430895 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_test_vectors_kmac.833430895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3409897522
Short name T481
Test name
Test status
Simulation time 215721576 ps
CPU time 4.86 seconds
Started Jul 09 05:51:43 PM PDT 24
Finished Jul 09 05:51:48 PM PDT 24
Peak memory 215656 kb
Host smart-f63c065f-8b65-4cfb-90bc-ba642dd2972e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409897522 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3409897522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.3295305119
Short name T353
Test name
Test status
Simulation time 269871130426 ps
CPU time 1838.91 seconds
Started Jul 09 05:51:40 PM PDT 24
Finished Jul 09 06:22:20 PM PDT 24
Peak memory 391748 kb
Host smart-8f476b90-02c9-4c65-b91f-9e63dcc9290e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3295305119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3295305119 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.1580824190
Short name T318
Test name
Test status
Simulation time 35490362612 ps
CPU time 1461.08 seconds
Started Jul 09 05:51:41 PM PDT 24
Finished Jul 09 06:16:03 PM PDT 24
Peak memory 367096 kb
Host smart-37c06141-0e09-49a5-82cf-a003e7a0ee1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1580824190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.1580824190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.551320397
Short name T980
Test name
Test status
Simulation time 68688026646 ps
CPU time 1333.55 seconds
Started Jul 09 05:51:40 PM PDT 24
Finished Jul 09 06:13:55 PM PDT 24
Peak memory 329068 kb
Host smart-ff092f54-7e0c-4d33-9460-eff51e7b8a59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=551320397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.551320397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2079270855
Short name T960
Test name
Test status
Simulation time 186384885560 ps
CPU time 978.23 seconds
Started Jul 09 05:51:39 PM PDT 24
Finished Jul 09 06:07:58 PM PDT 24
Peak memory 293616 kb
Host smart-53cccd66-83e2-4a83-9224-b372dbe0e7a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2079270855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2079270855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3910348610
Short name T271
Test name
Test status
Simulation time 224937043885 ps
CPU time 4532.19 seconds
Started Jul 09 05:51:40 PM PDT 24
Finished Jul 09 07:07:13 PM PDT 24
Peak memory 650468 kb
Host smart-810a508e-b7af-4178-857d-97d585994e41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3910348610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3910348610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.2485330386
Short name T216
Test name
Test status
Simulation time 606790043148 ps
CPU time 3845.46 seconds
Started Jul 09 05:51:40 PM PDT 24
Finished Jul 09 06:55:47 PM PDT 24
Peak memory 564592 kb
Host smart-bd3d5b10-2f4e-4441-824c-d35021ec5dad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2485330386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2485330386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.1774879383
Short name T400
Test name
Test status
Simulation time 16030870 ps
CPU time 0.8 seconds
Started Jul 09 05:51:57 PM PDT 24
Finished Jul 09 05:51:58 PM PDT 24
Peak memory 205316 kb
Host smart-3c9d887a-4227-4aea-a2e1-221e6d65ad31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774879383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1774879383 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.3416307021
Short name T939
Test name
Test status
Simulation time 51468835526 ps
CPU time 248.35 seconds
Started Jul 09 05:51:52 PM PDT 24
Finished Jul 09 05:56:00 PM PDT 24
Peak memory 242984 kb
Host smart-2e8bcc6c-50c6-433d-a2d0-818f9cbdfac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416307021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3416307021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.4232963638
Short name T545
Test name
Test status
Simulation time 194606953404 ps
CPU time 530.38 seconds
Started Jul 09 05:51:45 PM PDT 24
Finished Jul 09 06:00:35 PM PDT 24
Peak memory 230100 kb
Host smart-a3c3be5f-e4d7-4888-9957-ce0dc8823919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232963638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.4232963638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.3060310466
Short name T991
Test name
Test status
Simulation time 10162959404 ps
CPU time 80.44 seconds
Started Jul 09 05:51:54 PM PDT 24
Finished Jul 09 05:53:15 PM PDT 24
Peak memory 228564 kb
Host smart-b7563d65-acac-4069-873c-08c3e0dafb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060310466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3060310466 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.83696282
Short name T1003
Test name
Test status
Simulation time 8853108635 ps
CPU time 170.25 seconds
Started Jul 09 05:51:50 PM PDT 24
Finished Jul 09 05:54:41 PM PDT 24
Peak memory 248840 kb
Host smart-0e73a9e5-f7f3-45cd-8115-afcc548e8223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83696282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.83696282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1362638604
Short name T1059
Test name
Test status
Simulation time 5883528048 ps
CPU time 7.37 seconds
Started Jul 09 05:51:54 PM PDT 24
Finished Jul 09 05:52:02 PM PDT 24
Peak memory 207444 kb
Host smart-ea044c6e-a2b3-44d3-93b1-3fe07a63e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362638604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1362638604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.1593119578
Short name T918
Test name
Test status
Simulation time 119293750 ps
CPU time 1.3 seconds
Started Jul 09 05:51:57 PM PDT 24
Finished Jul 09 05:51:58 PM PDT 24
Peak memory 215612 kb
Host smart-ece260fa-0be5-4790-8ae7-6639e98e822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593119578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1593119578 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.3106491284
Short name T487
Test name
Test status
Simulation time 890117450514 ps
CPU time 1981.32 seconds
Started Jul 09 05:51:45 PM PDT 24
Finished Jul 09 06:24:47 PM PDT 24
Peak memory 414440 kb
Host smart-99775ee4-0cf4-4343-b104-be80794f6bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106491284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.3106491284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3239120078
Short name T925
Test name
Test status
Simulation time 8036007430 ps
CPU time 137.72 seconds
Started Jul 09 05:51:46 PM PDT 24
Finished Jul 09 05:54:04 PM PDT 24
Peak memory 234236 kb
Host smart-d5989419-2448-45c4-bdef-c0a5a97a51d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239120078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3239120078 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.3020385695
Short name T229
Test name
Test status
Simulation time 1829510169 ps
CPU time 41.04 seconds
Started Jul 09 05:51:46 PM PDT 24
Finished Jul 09 05:52:27 PM PDT 24
Peak memory 219140 kb
Host smart-f31ad103-e120-4934-9e5b-6ad5318703ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020385695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3020385695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.1760904495
Short name T52
Test name
Test status
Simulation time 259714310789 ps
CPU time 462.64 seconds
Started Jul 09 05:51:56 PM PDT 24
Finished Jul 09 05:59:39 PM PDT 24
Peak memory 289660 kb
Host smart-44bfa006-51dc-4ea8-8f8a-8bc15db002d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1760904495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1760904495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.720923122
Short name T368
Test name
Test status
Simulation time 438593529 ps
CPU time 4.17 seconds
Started Jul 09 05:51:53 PM PDT 24
Finished Jul 09 05:51:57 PM PDT 24
Peak memory 215604 kb
Host smart-c2f0d879-76fa-4907-8475-9e64ca8b916a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720923122 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.kmac_test_vectors_kmac.720923122 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.3854126753
Short name T613
Test name
Test status
Simulation time 66561836 ps
CPU time 3.74 seconds
Started Jul 09 05:51:51 PM PDT 24
Finished Jul 09 05:51:56 PM PDT 24
Peak memory 215648 kb
Host smart-de20549c-ddf9-47b9-b055-e5b555eab4fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854126753 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.3854126753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.240602404
Short name T189
Test name
Test status
Simulation time 168728350041 ps
CPU time 1890.38 seconds
Started Jul 09 05:51:49 PM PDT 24
Finished Jul 09 06:23:20 PM PDT 24
Peak memory 392536 kb
Host smart-d95c5458-e947-4ffa-85bf-ac11b51019a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=240602404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.240602404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.2207416742
Short name T478
Test name
Test status
Simulation time 63055592796 ps
CPU time 1379.23 seconds
Started Jul 09 05:51:48 PM PDT 24
Finished Jul 09 06:14:47 PM PDT 24
Peak memory 372432 kb
Host smart-a2663f72-ba62-4222-b361-7db836bcb4f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2207416742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.2207416742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.1311251588
Short name T69
Test name
Test status
Simulation time 14110514822 ps
CPU time 1013.02 seconds
Started Jul 09 05:51:49 PM PDT 24
Finished Jul 09 06:08:43 PM PDT 24
Peak memory 330076 kb
Host smart-68bdce57-e1e0-4a5a-b1f2-078124230187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1311251588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1311251588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.4019688515
Short name T895
Test name
Test status
Simulation time 220206711405 ps
CPU time 915.28 seconds
Started Jul 09 05:51:48 PM PDT 24
Finished Jul 09 06:07:04 PM PDT 24
Peak memory 297116 kb
Host smart-6c611256-fab8-40b0-80b3-9ffd5b3ed6e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4019688515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.4019688515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.1633119444
Short name T177
Test name
Test status
Simulation time 110117517700 ps
CPU time 3992.07 seconds
Started Jul 09 05:51:48 PM PDT 24
Finished Jul 09 06:58:21 PM PDT 24
Peak memory 647020 kb
Host smart-c5d488f9-c0ef-41cf-9a62-327229389654
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1633119444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.1633119444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.3992303422
Short name T701
Test name
Test status
Simulation time 189018054611 ps
CPU time 4169.13 seconds
Started Jul 09 05:51:50 PM PDT 24
Finished Jul 09 07:01:20 PM PDT 24
Peak memory 565136 kb
Host smart-e30ab67e-bd40-48f2-803b-93685e057bdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3992303422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3992303422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.149471408
Short name T328
Test name
Test status
Simulation time 26777007 ps
CPU time 0.81 seconds
Started Jul 09 05:52:02 PM PDT 24
Finished Jul 09 05:52:04 PM PDT 24
Peak memory 205332 kb
Host smart-275f4126-a31e-4912-8c03-8489f3824cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149471408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.149471408 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.1218617302
Short name T329
Test name
Test status
Simulation time 12567000102 ps
CPU time 229.42 seconds
Started Jul 09 05:51:59 PM PDT 24
Finished Jul 09 05:55:49 PM PDT 24
Peak memory 239888 kb
Host smart-bd973f0c-940c-427c-8727-16b15eea389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218617302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1218617302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3531709203
Short name T455
Test name
Test status
Simulation time 16681305343 ps
CPU time 340.84 seconds
Started Jul 09 05:51:55 PM PDT 24
Finished Jul 09 05:57:36 PM PDT 24
Peak memory 227084 kb
Host smart-e12bf464-2b6b-425c-a7cc-a0327aca38fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531709203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3531709203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.883935677
Short name T313
Test name
Test status
Simulation time 16903202734 ps
CPU time 76.25 seconds
Started Jul 09 05:52:00 PM PDT 24
Finished Jul 09 05:53:17 PM PDT 24
Peak memory 225584 kb
Host smart-6ef5c3ef-eaa2-464c-9b4d-7f9945c358a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883935677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.883935677 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.579427765
Short name T281
Test name
Test status
Simulation time 33253693280 ps
CPU time 208.21 seconds
Started Jul 09 05:52:02 PM PDT 24
Finished Jul 09 05:55:31 PM PDT 24
Peak memory 254212 kb
Host smart-54b8a478-6068-4022-87cc-e33fb3a28803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579427765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.579427765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.657667308
Short name T66
Test name
Test status
Simulation time 854752636 ps
CPU time 4.83 seconds
Started Jul 09 05:52:02 PM PDT 24
Finished Jul 09 05:52:07 PM PDT 24
Peak memory 215652 kb
Host smart-78591ab7-5e80-427a-99ed-12c073d9f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657667308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.657667308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.3066462574
Short name T489
Test name
Test status
Simulation time 90296515455 ps
CPU time 1742.67 seconds
Started Jul 09 05:51:56 PM PDT 24
Finished Jul 09 06:20:59 PM PDT 24
Peak memory 417448 kb
Host smart-5d322d83-6399-4eed-8c86-1748166d91f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066462574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.3066462574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.1350079122
Short name T1060
Test name
Test status
Simulation time 17543021048 ps
CPU time 338.27 seconds
Started Jul 09 05:51:54 PM PDT 24
Finished Jul 09 05:57:33 PM PDT 24
Peak memory 249404 kb
Host smart-b6d1ae20-a502-4047-b24f-35157e35b476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350079122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1350079122 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3361118169
Short name T1062
Test name
Test status
Simulation time 35136953270 ps
CPU time 73.68 seconds
Started Jul 09 05:51:56 PM PDT 24
Finished Jul 09 05:53:10 PM PDT 24
Peak memory 219428 kb
Host smart-b2103bd6-bf8f-4673-a437-eac3f4f03777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361118169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3361118169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.438630625
Short name T735
Test name
Test status
Simulation time 58604997637 ps
CPU time 913.3 seconds
Started Jul 09 05:52:02 PM PDT 24
Finished Jul 09 06:07:16 PM PDT 24
Peak memory 352472 kb
Host smart-c060079f-aad6-424d-90ac-b51a502fa185
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=438630625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.438630625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.1548189014
Short name T782
Test name
Test status
Simulation time 172686713 ps
CPU time 4.35 seconds
Started Jul 09 05:52:01 PM PDT 24
Finished Jul 09 05:52:06 PM PDT 24
Peak memory 215724 kb
Host smart-a262551f-e31f-4b75-b1de-52eea1aa993a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548189014 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.1548189014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.3987365909
Short name T802
Test name
Test status
Simulation time 1040950548 ps
CPU time 5.73 seconds
Started Jul 09 05:52:00 PM PDT 24
Finished Jul 09 05:52:06 PM PDT 24
Peak memory 215628 kb
Host smart-32f60ebf-9235-4e2e-a466-866b321a0f33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987365909 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.3987365909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2762290204
Short name T547
Test name
Test status
Simulation time 186826665535 ps
CPU time 2030.29 seconds
Started Jul 09 05:51:57 PM PDT 24
Finished Jul 09 06:25:47 PM PDT 24
Peak memory 392132 kb
Host smart-6f597c76-55ca-4624-86a1-d0ac1855bdc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2762290204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2762290204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.2950804639
Short name T886
Test name
Test status
Simulation time 124357756640 ps
CPU time 1607.5 seconds
Started Jul 09 05:52:00 PM PDT 24
Finished Jul 09 06:18:48 PM PDT 24
Peak memory 365756 kb
Host smart-a9bd9823-aa4c-4feb-a649-d8658c816bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2950804639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.2950804639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.108659709
Short name T195
Test name
Test status
Simulation time 61416264214 ps
CPU time 1248.52 seconds
Started Jul 09 05:51:57 PM PDT 24
Finished Jul 09 06:12:46 PM PDT 24
Peak memory 337820 kb
Host smart-5262a691-48cd-459c-b8fa-f835dc058427
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=108659709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.108659709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.1849077561
Short name T539
Test name
Test status
Simulation time 37585211204 ps
CPU time 754.64 seconds
Started Jul 09 05:51:58 PM PDT 24
Finished Jul 09 06:04:33 PM PDT 24
Peak memory 292904 kb
Host smart-ca3ac4e7-5c05-4529-9a61-97f8cc1c2fd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1849077561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1849077561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.761507181
Short name T743
Test name
Test status
Simulation time 106017322644 ps
CPU time 4022.02 seconds
Started Jul 09 05:51:58 PM PDT 24
Finished Jul 09 06:59:01 PM PDT 24
Peak memory 651804 kb
Host smart-93b89f56-ca19-498c-a0fa-8524c534d935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=761507181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.761507181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.1367947522
Short name T680
Test name
Test status
Simulation time 535516831102 ps
CPU time 3975.99 seconds
Started Jul 09 05:52:00 PM PDT 24
Finished Jul 09 06:58:17 PM PDT 24
Peak memory 556472 kb
Host smart-d4f07797-b3cd-4dfd-bb04-8d346bb35695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1367947522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.1367947522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.4035654819
Short name T1046
Test name
Test status
Simulation time 86756709 ps
CPU time 0.8 seconds
Started Jul 09 05:52:14 PM PDT 24
Finished Jul 09 05:52:15 PM PDT 24
Peak memory 205328 kb
Host smart-cf9b310f-5f7b-4d8b-8480-c7dc39059dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035654819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.4035654819 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.1683873020
Short name T1078
Test name
Test status
Simulation time 1656266244 ps
CPU time 25.81 seconds
Started Jul 09 05:52:10 PM PDT 24
Finished Jul 09 05:52:36 PM PDT 24
Peak memory 223820 kb
Host smart-84bffa30-f9bb-46af-9d18-f3c2ddc25fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683873020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1683873020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3036139162
Short name T555
Test name
Test status
Simulation time 7604659641 ps
CPU time 224.98 seconds
Started Jul 09 05:52:06 PM PDT 24
Finished Jul 09 05:55:51 PM PDT 24
Peak memory 224760 kb
Host smart-9db7d62a-e589-42ae-93fc-d54fb46856d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036139162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3036139162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.1503082657
Short name T263
Test name
Test status
Simulation time 11129904356 ps
CPU time 317.43 seconds
Started Jul 09 05:52:10 PM PDT 24
Finished Jul 09 05:57:28 PM PDT 24
Peak memory 244472 kb
Host smart-8f941cea-005c-4452-b230-456cda7de01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503082657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1503082657 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.156363400
Short name T273
Test name
Test status
Simulation time 19494952298 ps
CPU time 98.85 seconds
Started Jul 09 05:52:15 PM PDT 24
Finished Jul 09 05:53:54 PM PDT 24
Peak memory 240384 kb
Host smart-fb51b904-9254-46b6-b48d-a51cc764ca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156363400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.156363400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2080328286
Short name T336
Test name
Test status
Simulation time 815171009 ps
CPU time 4.99 seconds
Started Jul 09 05:52:13 PM PDT 24
Finished Jul 09 05:52:19 PM PDT 24
Peak memory 207356 kb
Host smart-baaf0406-63a2-49bb-91da-9ec745d92edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080328286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2080328286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.120663890
Short name T893
Test name
Test status
Simulation time 32237917 ps
CPU time 1.16 seconds
Started Jul 09 05:52:12 PM PDT 24
Finished Jul 09 05:52:14 PM PDT 24
Peak memory 215544 kb
Host smart-83587fb0-652d-4b4f-bfc9-85442ce31ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120663890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.120663890 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2526509189
Short name T330
Test name
Test status
Simulation time 49303173569 ps
CPU time 1234.54 seconds
Started Jul 09 05:52:05 PM PDT 24
Finished Jul 09 06:12:40 PM PDT 24
Peak memory 345220 kb
Host smart-70aca49b-28e3-42c6-8b21-0bff3edf10e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526509189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2526509189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.3077793917
Short name T730
Test name
Test status
Simulation time 48218942583 ps
CPU time 274.78 seconds
Started Jul 09 05:52:06 PM PDT 24
Finished Jul 09 05:56:41 PM PDT 24
Peak memory 241192 kb
Host smart-e7207094-94e0-4ecb-a43b-6790d8393a4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077793917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3077793917 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.332725857
Short name T839
Test name
Test status
Simulation time 11932770970 ps
CPU time 50.03 seconds
Started Jul 09 05:52:03 PM PDT 24
Finished Jul 09 05:52:54 PM PDT 24
Peak memory 218932 kb
Host smart-c896ab9d-9709-413c-8e4f-a7a2624d83cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332725857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.332725857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.2031250112
Short name T816
Test name
Test status
Simulation time 493096817514 ps
CPU time 1498 seconds
Started Jul 09 05:52:12 PM PDT 24
Finished Jul 09 06:17:11 PM PDT 24
Peak memory 390240 kb
Host smart-bd558cd7-1f22-4679-9b59-e816f197c195
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2031250112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2031250112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.2987187514
Short name T777
Test name
Test status
Simulation time 338636075 ps
CPU time 4.61 seconds
Started Jul 09 05:52:09 PM PDT 24
Finished Jul 09 05:52:14 PM PDT 24
Peak memory 215668 kb
Host smart-f10c3a00-91a1-4a85-b107-34b41fee2497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987187514 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.2987187514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.1436286538
Short name T843
Test name
Test status
Simulation time 252074035 ps
CPU time 5.24 seconds
Started Jul 09 05:52:10 PM PDT 24
Finished Jul 09 05:52:15 PM PDT 24
Peak memory 215684 kb
Host smart-73c7ad71-412c-4380-8622-d429d4900dea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436286538 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.1436286538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.2377222738
Short name T634
Test name
Test status
Simulation time 19072644667 ps
CPU time 1454.31 seconds
Started Jul 09 05:52:06 PM PDT 24
Finished Jul 09 06:16:21 PM PDT 24
Peak memory 374024 kb
Host smart-a5cb1a95-c2da-4937-8be4-9fb125bf6b4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2377222738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2377222738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.2880536834
Short name T750
Test name
Test status
Simulation time 78046561009 ps
CPU time 1736.45 seconds
Started Jul 09 05:52:08 PM PDT 24
Finished Jul 09 06:21:05 PM PDT 24
Peak memory 368344 kb
Host smart-b6df829c-880b-4448-9a5a-786797054ddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2880536834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2880536834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.190083443
Short name T124
Test name
Test status
Simulation time 101557781481 ps
CPU time 1327.48 seconds
Started Jul 09 05:52:09 PM PDT 24
Finished Jul 09 06:14:17 PM PDT 24
Peak memory 333640 kb
Host smart-bca93085-af22-4638-99c5-ff628f07b25c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=190083443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.190083443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.1961894177
Short name T289
Test name
Test status
Simulation time 36596374053 ps
CPU time 820.83 seconds
Started Jul 09 05:52:08 PM PDT 24
Finished Jul 09 06:05:49 PM PDT 24
Peak memory 295548 kb
Host smart-42890e26-c631-440e-aa99-d243db037268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1961894177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1961894177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.4075788271
Short name T152
Test name
Test status
Simulation time 521235034952 ps
CPU time 5159.23 seconds
Started Jul 09 05:52:09 PM PDT 24
Finished Jul 09 07:18:09 PM PDT 24
Peak memory 645368 kb
Host smart-3117d65d-3c34-4e3a-aae0-7dbff941dbd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4075788271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.4075788271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.2388838675
Short name T270
Test name
Test status
Simulation time 218159553398 ps
CPU time 4312.32 seconds
Started Jul 09 05:52:10 PM PDT 24
Finished Jul 09 07:04:03 PM PDT 24
Peak memory 566160 kb
Host smart-ceec6149-f340-4a87-8c6d-0868508ff6f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2388838675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.2388838675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1574102675
Short name T542
Test name
Test status
Simulation time 22811727 ps
CPU time 0.76 seconds
Started Jul 09 05:52:29 PM PDT 24
Finished Jul 09 05:52:30 PM PDT 24
Peak memory 205352 kb
Host smart-7490e51d-2d5f-4c47-b3dd-7299d625eda0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574102675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1574102675 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.2127789980
Short name T872
Test name
Test status
Simulation time 33965066232 ps
CPU time 71.23 seconds
Started Jul 09 05:52:23 PM PDT 24
Finished Jul 09 05:53:34 PM PDT 24
Peak memory 227684 kb
Host smart-ec5c2006-81be-4c7c-815e-9c4103cdc3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127789980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2127789980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.1136888455
Short name T133
Test name
Test status
Simulation time 57925271937 ps
CPU time 412.12 seconds
Started Jul 09 05:52:14 PM PDT 24
Finished Jul 09 05:59:07 PM PDT 24
Peak memory 234628 kb
Host smart-34501212-2d2d-430d-b396-3c7a3bee554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136888455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1136888455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2817266742
Short name T793
Test name
Test status
Simulation time 3046064623 ps
CPU time 14.72 seconds
Started Jul 09 05:52:22 PM PDT 24
Finished Jul 09 05:52:37 PM PDT 24
Peak memory 223912 kb
Host smart-d6bfef03-0989-4d61-8685-d5a6a0894af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817266742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2817266742 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.2865181024
Short name T34
Test name
Test status
Simulation time 37820491228 ps
CPU time 416.72 seconds
Started Jul 09 05:52:22 PM PDT 24
Finished Jul 09 05:59:19 PM PDT 24
Peak memory 254984 kb
Host smart-e8ed34a4-2181-4d56-b070-7e7c53a15f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865181024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2865181024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.3732994675
Short name T403
Test name
Test status
Simulation time 513664090 ps
CPU time 1.89 seconds
Started Jul 09 05:52:25 PM PDT 24
Finished Jul 09 05:52:28 PM PDT 24
Peak memory 207300 kb
Host smart-9b0192ce-a41d-4f51-8f7e-b66f54895b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732994675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3732994675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.902836512
Short name T554
Test name
Test status
Simulation time 203490946 ps
CPU time 1.24 seconds
Started Jul 09 05:52:25 PM PDT 24
Finished Jul 09 05:52:27 PM PDT 24
Peak memory 215636 kb
Host smart-59378bcb-6ee3-415d-a8a1-4f4811c87caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902836512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.902836512 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.2194092448
Short name T883
Test name
Test status
Simulation time 134558561282 ps
CPU time 791.06 seconds
Started Jul 09 05:52:15 PM PDT 24
Finished Jul 09 06:05:27 PM PDT 24
Peak memory 291620 kb
Host smart-5d371fdb-2bd6-4dd6-a416-071260065d04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194092448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.2194092448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.2604474836
Short name T512
Test name
Test status
Simulation time 4442963185 ps
CPU time 68.89 seconds
Started Jul 09 05:52:13 PM PDT 24
Finished Jul 09 05:53:22 PM PDT 24
Peak memory 226920 kb
Host smart-1c2288fe-6380-4922-8e7a-6dbc7d3a9ba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604474836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2604474836 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3564551272
Short name T495
Test name
Test status
Simulation time 11285561692 ps
CPU time 62.65 seconds
Started Jul 09 05:52:13 PM PDT 24
Finished Jul 09 05:53:16 PM PDT 24
Peak memory 217492 kb
Host smart-c40564f2-a8c1-46e5-944e-e57eaf972d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564551272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3564551272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.3142468162
Short name T644
Test name
Test status
Simulation time 144677877617 ps
CPU time 1676.24 seconds
Started Jul 09 05:52:29 PM PDT 24
Finished Jul 09 06:20:26 PM PDT 24
Peak memory 428964 kb
Host smart-7c15d3fa-f5aa-4e9c-b46e-3990e28cd7a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3142468162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3142468162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.469432481
Short name T693
Test name
Test status
Simulation time 245279226 ps
CPU time 4.84 seconds
Started Jul 09 05:52:21 PM PDT 24
Finished Jul 09 05:52:27 PM PDT 24
Peak memory 215672 kb
Host smart-a278a46a-9d5f-4806-be1f-738a83526864
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469432481 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_test_vectors_kmac.469432481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2959380548
Short name T841
Test name
Test status
Simulation time 127274213 ps
CPU time 3.93 seconds
Started Jul 09 05:52:21 PM PDT 24
Finished Jul 09 05:52:26 PM PDT 24
Peak memory 215684 kb
Host smart-382f6ab7-d9bd-4f65-b599-e785dd1739b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959380548 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2959380548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.1101896568
Short name T286
Test name
Test status
Simulation time 62721346935 ps
CPU time 1727.66 seconds
Started Jul 09 05:52:15 PM PDT 24
Finished Jul 09 06:21:03 PM PDT 24
Peak memory 371320 kb
Host smart-9ed1c63b-b3f2-43ec-841c-6f7f6cb4f04a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1101896568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1101896568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.1119449796
Short name T317
Test name
Test status
Simulation time 47969016164 ps
CPU time 1461.78 seconds
Started Jul 09 05:52:15 PM PDT 24
Finished Jul 09 06:16:38 PM PDT 24
Peak memory 373860 kb
Host smart-e6d4c58b-4f51-4686-b59b-91e15a1468f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1119449796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.1119449796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.3295835960
Short name T535
Test name
Test status
Simulation time 45901815065 ps
CPU time 1270.06 seconds
Started Jul 09 05:52:21 PM PDT 24
Finished Jul 09 06:13:31 PM PDT 24
Peak memory 329520 kb
Host smart-b23c6755-6484-4f85-b68b-75114a0ffb78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3295835960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3295835960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.1308791737
Short name T804
Test name
Test status
Simulation time 111055573215 ps
CPU time 935.5 seconds
Started Jul 09 05:52:18 PM PDT 24
Finished Jul 09 06:07:54 PM PDT 24
Peak memory 299328 kb
Host smart-c123177e-f49e-4a0d-969f-ecce5dc22809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1308791737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.1308791737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.4208237882
Short name T969
Test name
Test status
Simulation time 263061478540 ps
CPU time 5060.05 seconds
Started Jul 09 05:52:18 PM PDT 24
Finished Jul 09 07:16:39 PM PDT 24
Peak memory 644860 kb
Host smart-d504d89a-2ebb-4784-96c5-e11e69e2acb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4208237882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.4208237882 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_alert_test.4182784682
Short name T978
Test name
Test status
Simulation time 15916767 ps
CPU time 0.76 seconds
Started Jul 09 05:52:39 PM PDT 24
Finished Jul 09 05:52:41 PM PDT 24
Peak memory 205336 kb
Host smart-7b033de6-6856-419d-8645-8e66250c981a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182784682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.4182784682 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1535450001
Short name T1036
Test name
Test status
Simulation time 1974985607 ps
CPU time 58.6 seconds
Started Jul 09 05:52:38 PM PDT 24
Finished Jul 09 05:53:37 PM PDT 24
Peak memory 226072 kb
Host smart-44fa1ea5-547b-405c-a814-75a3ed9d965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535450001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1535450001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.3748927159
Short name T42
Test name
Test status
Simulation time 5331041312 ps
CPU time 298.29 seconds
Started Jul 09 05:52:33 PM PDT 24
Finished Jul 09 05:57:32 PM PDT 24
Peak memory 227900 kb
Host smart-f6343cf0-5f6c-4d0e-8758-e84ad0547e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748927159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3748927159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.2292329096
Short name T452
Test name
Test status
Simulation time 16236204299 ps
CPU time 164.74 seconds
Started Jul 09 05:52:37 PM PDT 24
Finished Jul 09 05:55:23 PM PDT 24
Peak memory 235712 kb
Host smart-857d93e6-ce7d-466f-b9a4-3bab5591c6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292329096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2292329096 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1325883794
Short name T739
Test name
Test status
Simulation time 9101261850 ps
CPU time 321.51 seconds
Started Jul 09 05:52:41 PM PDT 24
Finished Jul 09 05:58:03 PM PDT 24
Peak memory 256572 kb
Host smart-98d71c92-e18c-4253-9ef4-8910fe654c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325883794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1325883794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.2440869751
Short name T967
Test name
Test status
Simulation time 276737391 ps
CPU time 2.08 seconds
Started Jul 09 05:52:43 PM PDT 24
Finished Jul 09 05:52:46 PM PDT 24
Peak memory 207296 kb
Host smart-d29222f7-d812-45a0-bd4e-ad38d0a7e467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440869751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2440869751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.1537271389
Short name T551
Test name
Test status
Simulation time 56713873 ps
CPU time 1.19 seconds
Started Jul 09 05:52:41 PM PDT 24
Finished Jul 09 05:52:43 PM PDT 24
Peak memory 215568 kb
Host smart-6345961a-4108-45b5-99c3-c7371c046927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537271389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1537271389 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.2955967960
Short name T637
Test name
Test status
Simulation time 77339415701 ps
CPU time 2304.84 seconds
Started Jul 09 05:52:29 PM PDT 24
Finished Jul 09 06:30:55 PM PDT 24
Peak memory 439448 kb
Host smart-c54b4432-cc1d-41e9-b275-b7ed69acc103
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955967960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.2955967960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.1023486322
Short name T641
Test name
Test status
Simulation time 2709405909 ps
CPU time 202.8 seconds
Started Jul 09 05:52:34 PM PDT 24
Finished Jul 09 05:55:57 PM PDT 24
Peak memory 237820 kb
Host smart-8fee2100-876b-4857-8c7a-c5c95fd7f6b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023486322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1023486322 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1631636788
Short name T1054
Test name
Test status
Simulation time 3646150115 ps
CPU time 39.29 seconds
Started Jul 09 05:52:30 PM PDT 24
Finished Jul 09 05:53:09 PM PDT 24
Peak memory 216924 kb
Host smart-a2cd94d6-d7ff-4b1e-8163-b97f2bb566ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631636788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1631636788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1012396583
Short name T309
Test name
Test status
Simulation time 43836124651 ps
CPU time 634.9 seconds
Started Jul 09 05:52:40 PM PDT 24
Finished Jul 09 06:03:15 PM PDT 24
Peak memory 282356 kb
Host smart-f44aac5a-3155-416a-b5f0-7a0760e63715
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1012396583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1012396583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.1827456712
Short name T323
Test name
Test status
Simulation time 422090432 ps
CPU time 4.71 seconds
Started Jul 09 05:52:38 PM PDT 24
Finished Jul 09 05:52:43 PM PDT 24
Peak memory 215492 kb
Host smart-e00ed8a4-d057-48da-9876-65dc30e6920c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827456712 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.1827456712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.3837623696
Short name T745
Test name
Test status
Simulation time 132215757 ps
CPU time 4.04 seconds
Started Jul 09 05:52:36 PM PDT 24
Finished Jul 09 05:52:40 PM PDT 24
Peak memory 215636 kb
Host smart-34fe0529-4814-447b-81f3-b8868f112100
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837623696 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.3837623696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.136910737
Short name T783
Test name
Test status
Simulation time 117088281517 ps
CPU time 1545.22 seconds
Started Jul 09 05:52:34 PM PDT 24
Finished Jul 09 06:18:20 PM PDT 24
Peak memory 390076 kb
Host smart-89f9cb9b-67a1-4541-9f98-1c3ee2fbc11a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=136910737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.136910737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1103990401
Short name T661
Test name
Test status
Simulation time 59757519619 ps
CPU time 1582.11 seconds
Started Jul 09 05:52:33 PM PDT 24
Finished Jul 09 06:18:55 PM PDT 24
Peak memory 365844 kb
Host smart-70450467-f953-477a-ac81-8d33b5174479
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1103990401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1103990401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.988882160
Short name T219
Test name
Test status
Simulation time 14227961401 ps
CPU time 1175.02 seconds
Started Jul 09 05:52:35 PM PDT 24
Finished Jul 09 06:12:10 PM PDT 24
Peak memory 335420 kb
Host smart-74b252f5-1116-41d9-bdd3-72b71739f34f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=988882160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.988882160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.3320595405
Short name T521
Test name
Test status
Simulation time 19259795231 ps
CPU time 768.42 seconds
Started Jul 09 05:52:37 PM PDT 24
Finished Jul 09 06:05:26 PM PDT 24
Peak memory 293996 kb
Host smart-fea238ec-9505-495d-bbcb-c224cc1b94cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3320595405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3320595405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.3283669431
Short name T230
Test name
Test status
Simulation time 240541311575 ps
CPU time 4813.58 seconds
Started Jul 09 05:52:36 PM PDT 24
Finished Jul 09 07:12:50 PM PDT 24
Peak memory 642676 kb
Host smart-f801c18f-b839-45fe-a490-8b47e32d2e9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3283669431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3283669431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.651457555
Short name T1043
Test name
Test status
Simulation time 358266715237 ps
CPU time 3321.95 seconds
Started Jul 09 05:52:35 PM PDT 24
Finished Jul 09 06:47:58 PM PDT 24
Peak memory 557496 kb
Host smart-37b27484-b005-4cfc-96a1-1d6bc36d5ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=651457555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.651457555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.1661323186
Short name T976
Test name
Test status
Simulation time 20841943 ps
CPU time 0.84 seconds
Started Jul 09 05:52:53 PM PDT 24
Finished Jul 09 05:52:55 PM PDT 24
Peak memory 205312 kb
Host smart-987a1b7c-1e37-4465-9ce8-036459cdc9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661323186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1661323186 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.667888117
Short name T546
Test name
Test status
Simulation time 11490596041 ps
CPU time 184.6 seconds
Started Jul 09 05:52:47 PM PDT 24
Finished Jul 09 05:55:52 PM PDT 24
Peak memory 236908 kb
Host smart-02827f18-64bf-48b7-a664-95d9bf3e51d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667888117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.667888117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.1731094465
Short name T215
Test name
Test status
Simulation time 29255452494 ps
CPU time 603.2 seconds
Started Jul 09 05:52:44 PM PDT 24
Finished Jul 09 06:02:47 PM PDT 24
Peak memory 230768 kb
Host smart-92246b2f-645c-4fe3-8b74-679273ed44a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731094465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1731094465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2937566446
Short name T704
Test name
Test status
Simulation time 159874021473 ps
CPU time 183.96 seconds
Started Jul 09 05:52:48 PM PDT 24
Finished Jul 09 05:55:52 PM PDT 24
Peak memory 233684 kb
Host smart-19b6ba40-dec9-44a1-b0cc-30fbafd380bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937566446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2937566446 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.3891005705
Short name T156
Test name
Test status
Simulation time 24972104860 ps
CPU time 202.9 seconds
Started Jul 09 05:52:50 PM PDT 24
Finished Jul 09 05:56:14 PM PDT 24
Peak memory 248472 kb
Host smart-8ce5c626-5e13-4e50-adf9-c8932474ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891005705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3891005705 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.4092071039
Short name T815
Test name
Test status
Simulation time 1887525274 ps
CPU time 9.29 seconds
Started Jul 09 05:52:51 PM PDT 24
Finished Jul 09 05:53:01 PM PDT 24
Peak memory 215560 kb
Host smart-37a9a48a-7220-4a74-be4e-bf4310c14895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092071039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.4092071039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1598603712
Short name T1037
Test name
Test status
Simulation time 88714334 ps
CPU time 1.19 seconds
Started Jul 09 05:52:50 PM PDT 24
Finished Jul 09 05:52:52 PM PDT 24
Peak memory 215588 kb
Host smart-286a5fd5-20e7-4f7c-ba88-1d7aabb6e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598603712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1598603712 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.344344308
Short name T1048
Test name
Test status
Simulation time 177143900219 ps
CPU time 968.67 seconds
Started Jul 09 05:52:45 PM PDT 24
Finished Jul 09 06:08:55 PM PDT 24
Peak memory 304476 kb
Host smart-34cc0a09-a34d-4c3e-9a2e-b8cbf7c61bac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344344308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_an
d_output.344344308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.3965845158
Short name T621
Test name
Test status
Simulation time 43995148497 ps
CPU time 309.65 seconds
Started Jul 09 05:52:44 PM PDT 24
Finished Jul 09 05:57:54 PM PDT 24
Peak memory 245276 kb
Host smart-b76942b0-190d-4bd7-93d9-28247bbc4cbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965845158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3965845158 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1861328975
Short name T258
Test name
Test status
Simulation time 1004597420 ps
CPU time 53.03 seconds
Started Jul 09 05:52:39 PM PDT 24
Finished Jul 09 05:53:33 PM PDT 24
Peak memory 221992 kb
Host smart-2d07f409-be25-464f-b593-e896342ef5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861328975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1861328975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.4050337612
Short name T319
Test name
Test status
Simulation time 503160413440 ps
CPU time 1129.1 seconds
Started Jul 09 05:52:54 PM PDT 24
Finished Jul 09 06:11:44 PM PDT 24
Peak memory 337944 kb
Host smart-7d036162-36fd-4cb4-af1e-57ab5b0f2aaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4050337612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.4050337612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.2037272443
Short name T659
Test name
Test status
Simulation time 371914191 ps
CPU time 4.02 seconds
Started Jul 09 05:52:51 PM PDT 24
Finished Jul 09 05:52:55 PM PDT 24
Peak memory 215672 kb
Host smart-54a840fb-e951-47b0-a82b-ccc632a17eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037272443 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.2037272443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.206111459
Short name T686
Test name
Test status
Simulation time 706757460 ps
CPU time 4.65 seconds
Started Jul 09 05:52:50 PM PDT 24
Finished Jul 09 05:52:55 PM PDT 24
Peak memory 215660 kb
Host smart-589e5d5f-1712-4278-97c7-0bb4b02964ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206111459 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.kmac_test_vectors_kmac_xof.206111459 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.3459006408
Short name T370
Test name
Test status
Simulation time 78543067091 ps
CPU time 1546.92 seconds
Started Jul 09 05:52:50 PM PDT 24
Finished Jul 09 06:18:38 PM PDT 24
Peak memory 392220 kb
Host smart-8285a710-0381-47de-b53f-ba3e5edc46cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3459006408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.3459006408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.3874079101
Short name T898
Test name
Test status
Simulation time 91226940257 ps
CPU time 1818.4 seconds
Started Jul 09 05:52:50 PM PDT 24
Finished Jul 09 06:23:09 PM PDT 24
Peak memory 373380 kb
Host smart-57181bd3-612f-436e-8955-052d2d802079
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3874079101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.3874079101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3543965305
Short name T929
Test name
Test status
Simulation time 16998009341 ps
CPU time 1117.63 seconds
Started Jul 09 05:52:47 PM PDT 24
Finished Jul 09 06:11:25 PM PDT 24
Peak memory 341260 kb
Host smart-7f017455-9dfd-4e95-9881-6b05d2c976d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3543965305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3543965305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.3066525095
Short name T856
Test name
Test status
Simulation time 68833795811 ps
CPU time 928.7 seconds
Started Jul 09 05:52:50 PM PDT 24
Finished Jul 09 06:08:19 PM PDT 24
Peak memory 297376 kb
Host smart-14738db6-df6b-404b-bde0-b729c1ad4e6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3066525095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.3066525095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.1308361939
Short name T891
Test name
Test status
Simulation time 110689812613 ps
CPU time 3994.19 seconds
Started Jul 09 05:52:48 PM PDT 24
Finished Jul 09 06:59:23 PM PDT 24
Peak memory 651776 kb
Host smart-7eff2722-aec1-4d8d-a9c4-b0e46c08ca2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1308361939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1308361939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.786718468
Short name T294
Test name
Test status
Simulation time 809033565617 ps
CPU time 4130.79 seconds
Started Jul 09 05:52:46 PM PDT 24
Finished Jul 09 07:01:38 PM PDT 24
Peak memory 562480 kb
Host smart-1328e1fc-ffe1-4427-8b9b-cd9a1535ed4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=786718468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.786718468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.4046633213
Short name T1081
Test name
Test status
Simulation time 28740724 ps
CPU time 0.78 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:49:53 PM PDT 24
Peak memory 205368 kb
Host smart-75c042ae-7d21-4578-b4c4-ab9f1a6aa74f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046633213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.4046633213 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.2214425160
Short name T40
Test name
Test status
Simulation time 1428728569 ps
CPU time 26.12 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:50:15 PM PDT 24
Peak memory 219096 kb
Host smart-3921c611-1b9d-44eb-bb27-a40266e77e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214425160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2214425160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3840314690
Short name T733
Test name
Test status
Simulation time 36814548282 ps
CPU time 140.19 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 05:52:05 PM PDT 24
Peak memory 232336 kb
Host smart-3b473cb7-4a2b-4e9e-a495-e7b3886b72ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840314690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3840314690 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.2225453295
Short name T335
Test name
Test status
Simulation time 2652628686 ps
CPU time 107.98 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 05:51:23 PM PDT 24
Peak memory 223880 kb
Host smart-a0b61168-a488-42d5-afe7-2dd2978bb8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225453295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2225453295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2525327650
Short name T995
Test name
Test status
Simulation time 841931455 ps
CPU time 14.43 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:06 PM PDT 24
Peak memory 219932 kb
Host smart-46857910-1721-499a-aa72-de9012507724
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525327650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2525327650 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.264385992
Short name T573
Test name
Test status
Simulation time 2705998927 ps
CPU time 6.95 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:49:48 PM PDT 24
Peak memory 220588 kb
Host smart-a6c54960-8f49-4875-9fbb-40935997774f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=264385992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.264385992 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.3068405968
Short name T367
Test name
Test status
Simulation time 4617644703 ps
CPU time 18.34 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:50:08 PM PDT 24
Peak memory 223828 kb
Host smart-396f20d8-e830-4da1-84a6-4968a370b00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068405968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3068405968 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.623532807
Short name T687
Test name
Test status
Simulation time 253724135 ps
CPU time 12.61 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:04 PM PDT 24
Peak memory 220828 kb
Host smart-e15b758c-1c76-4706-bf50-2da6e900f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623532807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.623532807 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.509301494
Short name T589
Test name
Test status
Simulation time 4299591332 ps
CPU time 48.97 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:50:38 PM PDT 24
Peak memory 240208 kb
Host smart-e0499d1e-4053-4d6d-ae02-2acfe4189853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509301494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.509301494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.373218933
Short name T1080
Test name
Test status
Simulation time 2333402227 ps
CPU time 2.69 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:49:53 PM PDT 24
Peak memory 207420 kb
Host smart-43a248de-506d-43ef-9566-beb4683eb35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373218933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.373218933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1380537295
Short name T92
Test name
Test status
Simulation time 87944665 ps
CPU time 1.34 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 05:50:02 PM PDT 24
Peak memory 215620 kb
Host smart-1acc95fc-4424-4f74-b051-9bdbb8c3217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380537295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1380537295 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.2948482204
Short name T559
Test name
Test status
Simulation time 47291949891 ps
CPU time 1252.8 seconds
Started Jul 09 05:49:37 PM PDT 24
Finished Jul 09 06:10:30 PM PDT 24
Peak memory 334588 kb
Host smart-2c8b2e81-bf8d-4f93-8ee0-a4a3bc55156a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948482204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.2948482204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.603829018
Short name T763
Test name
Test status
Simulation time 19136390675 ps
CPU time 256.67 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 05:53:57 PM PDT 24
Peak memory 245348 kb
Host smart-d1798bd6-6dbd-4c10-be95-3b4b87e55b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603829018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.603829018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.1039813417
Short name T75
Test name
Test status
Simulation time 6457842540 ps
CPU time 52.61 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:50:43 PM PDT 24
Peak memory 263272 kb
Host smart-1d9bce3a-a42d-45b4-be79-55bbd4832e3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039813417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1039813417 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.168659546
Short name T722
Test name
Test status
Simulation time 26764104426 ps
CPU time 136.11 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:52:05 PM PDT 24
Peak memory 231572 kb
Host smart-a7edb1be-ffb2-40e2-b2e2-6194052b99a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168659546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.168659546 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.413112988
Short name T582
Test name
Test status
Simulation time 1185415920 ps
CPU time 20.85 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:12 PM PDT 24
Peak memory 218708 kb
Host smart-14db2dc7-bacf-4169-a134-ab618e1a244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413112988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.413112988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1974473966
Short name T1018
Test name
Test status
Simulation time 32146919250 ps
CPU time 1049.6 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 06:07:25 PM PDT 24
Peak memory 332268 kb
Host smart-4a5d9b21-f295-4e79-9d91-1155fc6fb647
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1974473966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1974473966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.1783224238
Short name T857
Test name
Test status
Simulation time 469030164 ps
CPU time 4.68 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:49:54 PM PDT 24
Peak memory 215744 kb
Host smart-91506e59-6594-4f16-a512-15636ef1c703
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783224238 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.1783224238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.468620599
Short name T1026
Test name
Test status
Simulation time 176225917 ps
CPU time 4.28 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:49:50 PM PDT 24
Peak memory 215748 kb
Host smart-cf01ac4e-ce5c-43f6-b3e1-2f4d37b8d0e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468620599 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_test_vectors_kmac_xof.468620599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.3967094369
Short name T800
Test name
Test status
Simulation time 18733387931 ps
CPU time 1552.8 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 06:15:35 PM PDT 24
Peak memory 390416 kb
Host smart-73aa0c6a-c08b-4030-9fa7-a7db0766f63c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3967094369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3967094369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.650105910
Short name T584
Test name
Test status
Simulation time 81195075788 ps
CPU time 1560.47 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 06:15:36 PM PDT 24
Peak memory 364452 kb
Host smart-c6da59e1-1d9f-4789-9c0a-3a408b2dad76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=650105910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.650105910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.1005100089
Short name T425
Test name
Test status
Simulation time 45874636506 ps
CPU time 1200.18 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 06:09:50 PM PDT 24
Peak memory 329040 kb
Host smart-e44d4d56-c47d-4d87-b65b-9e9f03059c7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1005100089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1005100089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.2624272311
Short name T921
Test name
Test status
Simulation time 9413433487 ps
CPU time 751.72 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 06:02:11 PM PDT 24
Peak memory 291256 kb
Host smart-5ebcb674-3403-4d2e-b7be-5aeb8eb0b65c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2624272311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2624272311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.4288976249
Short name T321
Test name
Test status
Simulation time 53439847335 ps
CPU time 3825.13 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 06:53:41 PM PDT 24
Peak memory 657656 kb
Host smart-6d671b60-c1cd-46ed-8124-5cc1b52a8aee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4288976249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.4288976249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.932286740
Short name T471
Test name
Test status
Simulation time 1162302134761 ps
CPU time 3980.87 seconds
Started Jul 09 05:49:36 PM PDT 24
Finished Jul 09 06:55:58 PM PDT 24
Peak memory 551652 kb
Host smart-cd598301-5746-41b3-8c7b-946496f18251
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=932286740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.932286740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.3371104619
Short name T574
Test name
Test status
Simulation time 25958572 ps
CPU time 0.81 seconds
Started Jul 09 05:53:14 PM PDT 24
Finished Jul 09 05:53:15 PM PDT 24
Peak memory 205320 kb
Host smart-f075aeba-7cd5-416c-9a53-6f51ff57bfcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371104619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3371104619 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.4174103671
Short name T1013
Test name
Test status
Simulation time 40017340344 ps
CPU time 236.29 seconds
Started Jul 09 05:53:04 PM PDT 24
Finished Jul 09 05:57:00 PM PDT 24
Peak memory 239776 kb
Host smart-cb4e36cb-ccde-466e-9afc-3205e22744a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174103671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.4174103671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.851738221
Short name T927
Test name
Test status
Simulation time 25699547441 ps
CPU time 768.36 seconds
Started Jul 09 05:53:00 PM PDT 24
Finished Jul 09 06:05:49 PM PDT 24
Peak memory 231564 kb
Host smart-5d1ff962-596b-4097-b2f8-97543ebd214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851738221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.851738221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_error.673447741
Short name T744
Test name
Test status
Simulation time 13963220120 ps
CPU time 347.33 seconds
Started Jul 09 05:53:09 PM PDT 24
Finished Jul 09 05:58:56 PM PDT 24
Peak memory 256684 kb
Host smart-68349a42-470f-4040-8fe1-3d5419a547d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673447741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.673447741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.2730912715
Short name T629
Test name
Test status
Simulation time 535202236 ps
CPU time 3.2 seconds
Started Jul 09 05:53:10 PM PDT 24
Finished Jul 09 05:53:13 PM PDT 24
Peak memory 207400 kb
Host smart-f8b10c7c-f20f-4458-b554-b74caa21d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730912715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2730912715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.2043763182
Short name T810
Test name
Test status
Simulation time 31747411 ps
CPU time 1.22 seconds
Started Jul 09 05:53:08 PM PDT 24
Finished Jul 09 05:53:09 PM PDT 24
Peak memory 215596 kb
Host smart-13a6df44-69c9-4f58-afd3-e67c5c7b4a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043763182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2043763182 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.288575381
Short name T440
Test name
Test status
Simulation time 104408824143 ps
CPU time 2134.94 seconds
Started Jul 09 05:52:59 PM PDT 24
Finished Jul 09 06:28:34 PM PDT 24
Peak memory 438100 kb
Host smart-e016af9c-c6fa-440a-9684-7b8c1c94604f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288575381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.288575381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.1666329527
Short name T310
Test name
Test status
Simulation time 121366387521 ps
CPU time 237.97 seconds
Started Jul 09 05:53:00 PM PDT 24
Finished Jul 09 05:56:58 PM PDT 24
Peak memory 238788 kb
Host smart-761c2227-41ec-4153-a276-55b57b114a8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666329527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1666329527 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.2331678244
Short name T1033
Test name
Test status
Simulation time 1000263401 ps
CPU time 25.64 seconds
Started Jul 09 05:52:54 PM PDT 24
Finished Jul 09 05:53:20 PM PDT 24
Peak memory 219384 kb
Host smart-6c4014c5-3567-408e-a8a5-376ad03d21b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331678244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2331678244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.437718540
Short name T829
Test name
Test status
Simulation time 4249646247 ps
CPU time 329.72 seconds
Started Jul 09 05:53:09 PM PDT 24
Finished Jul 09 05:58:39 PM PDT 24
Peak memory 271296 kb
Host smart-d56d2b08-e262-455f-a7c6-c0050942da2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=437718540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.437718540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.1200981639
Short name T202
Test name
Test status
Simulation time 827604155 ps
CPU time 4.88 seconds
Started Jul 09 05:53:05 PM PDT 24
Finished Jul 09 05:53:10 PM PDT 24
Peak memory 215656 kb
Host smart-714a83c1-5435-4b21-b0a1-70c6def88e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200981639 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.1200981639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.2014651057
Short name T942
Test name
Test status
Simulation time 663957708 ps
CPU time 4.52 seconds
Started Jul 09 05:53:04 PM PDT 24
Finished Jul 09 05:53:09 PM PDT 24
Peak memory 215604 kb
Host smart-fb73a4d0-89ff-4f76-968e-780d00dc47f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014651057 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.2014651057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.2330417180
Short name T757
Test name
Test status
Simulation time 78077144608 ps
CPU time 1645.92 seconds
Started Jul 09 05:53:00 PM PDT 24
Finished Jul 09 06:20:26 PM PDT 24
Peak memory 390340 kb
Host smart-66b02294-cb29-4687-976d-f5329b693439
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2330417180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2330417180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.1448488485
Short name T759
Test name
Test status
Simulation time 474014888937 ps
CPU time 1837.56 seconds
Started Jul 09 05:52:59 PM PDT 24
Finished Jul 09 06:23:37 PM PDT 24
Peak memory 369164 kb
Host smart-c32c42fb-2791-48f0-82c8-268a758f089f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1448488485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.1448488485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.1560539719
Short name T384
Test name
Test status
Simulation time 144288857409 ps
CPU time 1530.89 seconds
Started Jul 09 05:52:57 PM PDT 24
Finished Jul 09 06:18:28 PM PDT 24
Peak memory 331424 kb
Host smart-5984634d-44ca-4f81-a5bf-36fb1dd7f0a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1560539719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.1560539719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.612616930
Short name T80
Test name
Test status
Simulation time 24577995270 ps
CPU time 771.44 seconds
Started Jul 09 05:53:03 PM PDT 24
Finished Jul 09 06:05:55 PM PDT 24
Peak memory 296212 kb
Host smart-ad2442cd-1ad2-4a18-ace6-95c9b73341ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=612616930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.612616930 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.2746829771
Short name T500
Test name
Test status
Simulation time 106782263864 ps
CPU time 3935.59 seconds
Started Jul 09 05:53:02 PM PDT 24
Finished Jul 09 06:58:39 PM PDT 24
Peak memory 658332 kb
Host smart-b0c0a276-9144-4531-9968-ec701beca77a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2746829771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2746829771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.1022962460
Short name T965
Test name
Test status
Simulation time 190002605283 ps
CPU time 3953.42 seconds
Started Jul 09 05:53:02 PM PDT 24
Finished Jul 09 06:58:56 PM PDT 24
Peak memory 570812 kb
Host smart-bf7b7f65-70d1-4104-8cc6-56725c71b6dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1022962460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1022962460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.1166888010
Short name T516
Test name
Test status
Simulation time 13363222 ps
CPU time 0.76 seconds
Started Jul 09 05:53:25 PM PDT 24
Finished Jul 09 05:53:26 PM PDT 24
Peak memory 205308 kb
Host smart-84585444-1059-4151-8b6f-659fe783bd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166888010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1166888010 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.3229686420
Short name T267
Test name
Test status
Simulation time 12305939102 ps
CPU time 232.4 seconds
Started Jul 09 05:53:25 PM PDT 24
Finished Jul 09 05:57:18 PM PDT 24
Peak memory 240060 kb
Host smart-0e4b0883-02b8-4ad7-9222-0ad91f1d4e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229686420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3229686420 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2338836272
Short name T170
Test name
Test status
Simulation time 4818876046 ps
CPU time 375.38 seconds
Started Jul 09 05:53:16 PM PDT 24
Finished Jul 09 05:59:32 PM PDT 24
Peak memory 228924 kb
Host smart-40ffe6df-589a-43c1-9197-030685fa99c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338836272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.2338836272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.3546153252
Short name T625
Test name
Test status
Simulation time 8068086038 ps
CPU time 139.06 seconds
Started Jul 09 05:53:23 PM PDT 24
Finished Jul 09 05:55:42 PM PDT 24
Peak memory 233980 kb
Host smart-8d11b089-1786-47d1-b294-9fd321100828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546153252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3546153252 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.4284996909
Short name T780
Test name
Test status
Simulation time 10234967950 ps
CPU time 232.71 seconds
Started Jul 09 05:54:17 PM PDT 24
Finished Jul 09 05:58:11 PM PDT 24
Peak memory 256664 kb
Host smart-1886ad37-91c4-4f40-b88d-308285dbaa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284996909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.4284996909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.2506369944
Short name T419
Test name
Test status
Simulation time 2386490815 ps
CPU time 6.85 seconds
Started Jul 09 05:53:25 PM PDT 24
Finished Jul 09 05:53:33 PM PDT 24
Peak memory 215632 kb
Host smart-aa0b5600-5616-42e1-b453-1ce700b4156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506369944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2506369944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.1125000530
Short name T396
Test name
Test status
Simulation time 127999519 ps
CPU time 1.3 seconds
Started Jul 09 05:53:25 PM PDT 24
Finished Jul 09 05:53:27 PM PDT 24
Peak memory 216912 kb
Host smart-43215aa3-e3cc-407f-b4b3-eaabc553b2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125000530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1125000530 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.778122795
Short name T196
Test name
Test status
Simulation time 147653798136 ps
CPU time 1116.61 seconds
Started Jul 09 05:53:14 PM PDT 24
Finished Jul 09 06:11:51 PM PDT 24
Peak memory 324144 kb
Host smart-f69feaf6-36f9-4954-94c9-1a1ee367c02d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778122795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_an
d_output.778122795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2348485572
Short name T361
Test name
Test status
Simulation time 2700306420 ps
CPU time 50.66 seconds
Started Jul 09 05:53:13 PM PDT 24
Finished Jul 09 05:54:04 PM PDT 24
Peak memory 223660 kb
Host smart-f377518f-c964-40ea-8495-cb3aab40e638
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348485572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2348485572 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.1422419504
Short name T210
Test name
Test status
Simulation time 4639309116 ps
CPU time 62.38 seconds
Started Jul 09 05:53:12 PM PDT 24
Finished Jul 09 05:54:14 PM PDT 24
Peak memory 219596 kb
Host smart-fd171318-4f08-4d13-8276-a4370496ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422419504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1422419504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.1896728758
Short name T469
Test name
Test status
Simulation time 23571342605 ps
CPU time 471.56 seconds
Started Jul 09 05:53:27 PM PDT 24
Finished Jul 09 06:01:19 PM PDT 24
Peak memory 302548 kb
Host smart-155f87b8-09ba-4d36-ae3f-fd03a9b5e42d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1896728758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1896728758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.458586263
Short name T702
Test name
Test status
Simulation time 1127014494 ps
CPU time 3.85 seconds
Started Jul 09 05:53:22 PM PDT 24
Finished Jul 09 05:53:26 PM PDT 24
Peak memory 216000 kb
Host smart-e15e0849-c1c8-48f3-857a-80f588435bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458586263 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.kmac_test_vectors_kmac.458586263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1532502596
Short name T789
Test name
Test status
Simulation time 315053092 ps
CPU time 4.56 seconds
Started Jul 09 05:53:24 PM PDT 24
Finished Jul 09 05:53:29 PM PDT 24
Peak memory 215616 kb
Host smart-2d60b77d-40e6-42db-b078-20150dbbe873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532502596 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1532502596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.1111268240
Short name T90
Test name
Test status
Simulation time 19599259610 ps
CPU time 1493.27 seconds
Started Jul 09 05:53:16 PM PDT 24
Finished Jul 09 06:18:10 PM PDT 24
Peak memory 387688 kb
Host smart-c7b8c145-2947-44f4-aa41-95e97dd343c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1111268240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.1111268240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.4131918441
Short name T615
Test name
Test status
Simulation time 254480008655 ps
CPU time 1690.32 seconds
Started Jul 09 05:53:16 PM PDT 24
Finished Jul 09 06:21:27 PM PDT 24
Peak memory 374044 kb
Host smart-a3631a35-2c5b-4812-89fb-6b0a39be4c00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4131918441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.4131918441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.1571566661
Short name T257
Test name
Test status
Simulation time 14869855496 ps
CPU time 978.1 seconds
Started Jul 09 05:53:15 PM PDT 24
Finished Jul 09 06:09:33 PM PDT 24
Peak memory 332820 kb
Host smart-fdaa46ed-a4a0-4d78-a717-c6369e29ab93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1571566661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1571566661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.3251194406
Short name T447
Test name
Test status
Simulation time 233873180219 ps
CPU time 910.11 seconds
Started Jul 09 05:53:14 PM PDT 24
Finished Jul 09 06:08:24 PM PDT 24
Peak memory 295428 kb
Host smart-f798b735-02e6-4f43-a630-3430f9b4a01a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3251194406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3251194406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.713783916
Short name T269
Test name
Test status
Simulation time 222282335477 ps
CPU time 4669.78 seconds
Started Jul 09 05:53:18 PM PDT 24
Finished Jul 09 07:11:09 PM PDT 24
Peak memory 648324 kb
Host smart-7cd53c51-beb8-4ec2-9391-40e7d044cda5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=713783916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.713783916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.829620755
Short name T645
Test name
Test status
Simulation time 44499201585 ps
CPU time 3607.58 seconds
Started Jul 09 05:53:19 PM PDT 24
Finished Jul 09 06:53:27 PM PDT 24
Peak memory 567628 kb
Host smart-60988aa8-2820-4761-bea9-e3a5738086f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=829620755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.829620755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.3815074378
Short name T1057
Test name
Test status
Simulation time 15898416 ps
CPU time 0.81 seconds
Started Jul 09 05:53:45 PM PDT 24
Finished Jul 09 05:53:47 PM PDT 24
Peak memory 205300 kb
Host smart-7b1d9156-42c2-44cc-82ca-041b768804bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815074378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3815074378 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2422403529
Short name T577
Test name
Test status
Simulation time 25513231116 ps
CPU time 33.04 seconds
Started Jul 09 05:53:43 PM PDT 24
Finished Jul 09 05:54:16 PM PDT 24
Peak memory 224344 kb
Host smart-14dc3c6e-3982-44a6-b726-7eb7d08aff9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422403529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2422403529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.3620762773
Short name T524
Test name
Test status
Simulation time 84121278694 ps
CPU time 150.08 seconds
Started Jul 09 05:53:30 PM PDT 24
Finished Jul 09 05:56:01 PM PDT 24
Peak memory 221992 kb
Host smart-f221f711-6a81-4590-8353-d0f60c6d7bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620762773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3620762773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.676805614
Short name T513
Test name
Test status
Simulation time 11637927677 ps
CPU time 16.93 seconds
Started Jul 09 05:53:45 PM PDT 24
Finished Jul 09 05:54:02 PM PDT 24
Peak memory 220900 kb
Host smart-35c8d950-f05d-4019-b506-20ac1ba563d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676805614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.676805614 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.485421049
Short name T13
Test name
Test status
Simulation time 109663519613 ps
CPU time 302.11 seconds
Started Jul 09 05:53:43 PM PDT 24
Finished Jul 09 05:58:45 PM PDT 24
Peak memory 254100 kb
Host smart-eb13d084-07a0-4384-9144-ade12bce5152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485421049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.485421049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.876126713
Short name T391
Test name
Test status
Simulation time 2881524435 ps
CPU time 4.5 seconds
Started Jul 09 05:53:45 PM PDT 24
Finished Jul 09 05:53:50 PM PDT 24
Peak memory 207444 kb
Host smart-acd9277a-c7b8-4921-b1b5-b2599e0b9cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876126713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.876126713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2767497870
Short name T59
Test name
Test status
Simulation time 127525089 ps
CPU time 1.29 seconds
Started Jul 09 05:53:46 PM PDT 24
Finished Jul 09 05:53:47 PM PDT 24
Peak memory 215532 kb
Host smart-491fbe89-c7a9-4dfd-ad26-79a11eef6b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767497870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2767497870 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.2491059854
Short name T266
Test name
Test status
Simulation time 1981484892 ps
CPU time 186.77 seconds
Started Jul 09 05:53:28 PM PDT 24
Finished Jul 09 05:56:35 PM PDT 24
Peak memory 233396 kb
Host smart-1bada2e2-8517-4ae4-bdb7-d7c3a007049b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491059854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.2491059854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.2492891212
Short name T601
Test name
Test status
Simulation time 50723325563 ps
CPU time 179.63 seconds
Started Jul 09 05:53:29 PM PDT 24
Finished Jul 09 05:56:29 PM PDT 24
Peak memory 240316 kb
Host smart-f2406b8b-3597-4b46-8a57-be06888feb33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492891212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2492891212 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.3968518964
Short name T525
Test name
Test status
Simulation time 55806667 ps
CPU time 2.87 seconds
Started Jul 09 05:53:24 PM PDT 24
Finished Jul 09 05:53:27 PM PDT 24
Peak memory 220164 kb
Host smart-479835df-3baa-474d-a308-e4ab8138bd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968518964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3968518964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.3910289247
Short name T454
Test name
Test status
Simulation time 450823918 ps
CPU time 4.74 seconds
Started Jul 09 05:53:45 PM PDT 24
Finished Jul 09 05:53:50 PM PDT 24
Peak memory 208752 kb
Host smart-21c8793e-ff63-498e-8135-22bfa8db2e0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910289247 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.3910289247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.3014894511
Short name T865
Test name
Test status
Simulation time 268641877 ps
CPU time 4.7 seconds
Started Jul 09 05:53:46 PM PDT 24
Finished Jul 09 05:53:51 PM PDT 24
Peak memory 215640 kb
Host smart-b28754eb-d00d-4a6f-829b-3e096227f873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014894511 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.3014894511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.2845941532
Short name T618
Test name
Test status
Simulation time 506630413026 ps
CPU time 1939.13 seconds
Started Jul 09 05:53:30 PM PDT 24
Finished Jul 09 06:25:49 PM PDT 24
Peak memory 371216 kb
Host smart-6a93ddb2-b815-4328-984d-676890e342cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2845941532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2845941532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.1979431187
Short name T182
Test name
Test status
Simulation time 63431499871 ps
CPU time 1766.1 seconds
Started Jul 09 05:53:33 PM PDT 24
Finished Jul 09 06:22:59 PM PDT 24
Peak memory 369068 kb
Host smart-cb7feaca-e24e-4537-9c02-a0413fed5f81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1979431187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1979431187 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.2635468284
Short name T360
Test name
Test status
Simulation time 258981302966 ps
CPU time 1434.15 seconds
Started Jul 09 05:53:36 PM PDT 24
Finished Jul 09 06:17:31 PM PDT 24
Peak memory 332512 kb
Host smart-d38da81b-a254-49c1-86ae-955cf3b85fcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2635468284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2635468284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.4170080584
Short name T711
Test name
Test status
Simulation time 38021335478 ps
CPU time 797.23 seconds
Started Jul 09 05:53:36 PM PDT 24
Finished Jul 09 06:06:54 PM PDT 24
Peak memory 295376 kb
Host smart-2e1d7c76-506c-4a87-ab4a-e4fdf241d01f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4170080584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.4170080584 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.495577453
Short name T331
Test name
Test status
Simulation time 52117895734 ps
CPU time 3911.87 seconds
Started Jul 09 05:53:41 PM PDT 24
Finished Jul 09 06:58:53 PM PDT 24
Peak memory 654236 kb
Host smart-3c45ced1-b91b-4688-93d7-a52935a2d8d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=495577453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.495577453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.4069840483
Short name T944
Test name
Test status
Simulation time 87066223461 ps
CPU time 3491.91 seconds
Started Jul 09 05:53:41 PM PDT 24
Finished Jul 09 06:51:54 PM PDT 24
Peak memory 567288 kb
Host smart-cf1a5156-9532-4718-bd51-9a1b8a30124f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4069840483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.4069840483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1117145834
Short name T706
Test name
Test status
Simulation time 22586860 ps
CPU time 0.8 seconds
Started Jul 09 05:54:00 PM PDT 24
Finished Jul 09 05:54:01 PM PDT 24
Peak memory 205364 kb
Host smart-4c8ffa13-f607-47ff-b73a-aa0ffe7de7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117145834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1117145834 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.1948948306
Short name T657
Test name
Test status
Simulation time 16873801455 ps
CPU time 186.68 seconds
Started Jul 09 05:53:57 PM PDT 24
Finished Jul 09 05:57:04 PM PDT 24
Peak memory 240520 kb
Host smart-d0337fe3-e7c3-4fff-901a-5b5449d4515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948948306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1948948306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3066524213
Short name T549
Test name
Test status
Simulation time 57462985482 ps
CPU time 309.27 seconds
Started Jul 09 05:53:47 PM PDT 24
Finished Jul 09 05:58:56 PM PDT 24
Peak memory 227780 kb
Host smart-2b316fa9-498b-454c-81fb-b19ac0401909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066524213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3066524213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.3460772185
Short name T153
Test name
Test status
Simulation time 79656733179 ps
CPU time 345.78 seconds
Started Jul 09 05:53:57 PM PDT 24
Finished Jul 09 05:59:43 PM PDT 24
Peak memory 245640 kb
Host smart-b2e1c7b5-2266-4c23-a002-1e069ece1294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460772185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3460772185 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1760376922
Short name T1082
Test name
Test status
Simulation time 9593934418 ps
CPU time 217.41 seconds
Started Jul 09 05:53:58 PM PDT 24
Finished Jul 09 05:57:35 PM PDT 24
Peak memory 256656 kb
Host smart-2f315f06-648c-4d73-8111-1d395ce5918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760376922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1760376922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.3051366930
Short name T756
Test name
Test status
Simulation time 1525641179 ps
CPU time 3.84 seconds
Started Jul 09 05:54:00 PM PDT 24
Finished Jul 09 05:54:04 PM PDT 24
Peak memory 207324 kb
Host smart-9fc8097e-c7ff-4297-a088-6c92310db176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051366930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3051366930 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.3287381719
Short name T431
Test name
Test status
Simulation time 443977024 ps
CPU time 3.26 seconds
Started Jul 09 05:54:01 PM PDT 24
Finished Jul 09 05:54:05 PM PDT 24
Peak memory 220060 kb
Host smart-9719c4dc-c84e-490c-b176-4274d0c2f478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287381719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3287381719 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.3823189855
Short name T78
Test name
Test status
Simulation time 12292243470 ps
CPU time 373.61 seconds
Started Jul 09 05:53:46 PM PDT 24
Finished Jul 09 06:00:00 PM PDT 24
Peak memory 251976 kb
Host smart-fad7f949-264a-49ad-8228-cb990ed3e5ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823189855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.3823189855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.1803882676
Short name T125
Test name
Test status
Simulation time 6976666986 ps
CPU time 292.65 seconds
Started Jul 09 05:53:48 PM PDT 24
Finished Jul 09 05:58:41 PM PDT 24
Peak memory 243788 kb
Host smart-7beccd7a-3cae-499c-861e-fa111150fa06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803882676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1803882676 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1181687020
Short name T650
Test name
Test status
Simulation time 2388367739 ps
CPU time 32.82 seconds
Started Jul 09 05:53:48 PM PDT 24
Finished Jul 09 05:54:22 PM PDT 24
Peak memory 219120 kb
Host smart-dce05cca-a173-46e6-90e6-848f0dde57fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181687020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1181687020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.20054932
Short name T82
Test name
Test status
Simulation time 3032657705 ps
CPU time 89.71 seconds
Started Jul 09 05:54:01 PM PDT 24
Finished Jul 09 05:55:31 PM PDT 24
Peak memory 221608 kb
Host smart-b08d41ad-410a-4f82-975a-81db749cc542
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=20054932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.20054932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.3981462552
Short name T817
Test name
Test status
Simulation time 350887074 ps
CPU time 4.19 seconds
Started Jul 09 05:53:59 PM PDT 24
Finished Jul 09 05:54:03 PM PDT 24
Peak memory 215644 kb
Host smart-7ef23fc4-e8c2-4811-88af-a07d723279a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981462552 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.3981462552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3385338756
Short name T971
Test name
Test status
Simulation time 83765357 ps
CPU time 4.06 seconds
Started Jul 09 05:53:57 PM PDT 24
Finished Jul 09 05:54:01 PM PDT 24
Peak memory 215652 kb
Host smart-ac223127-6820-4fc4-866f-a7b1ad7ce4a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385338756 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3385338756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.2278705182
Short name T279
Test name
Test status
Simulation time 84069105694 ps
CPU time 1839.96 seconds
Started Jul 09 05:53:50 PM PDT 24
Finished Jul 09 06:24:30 PM PDT 24
Peak memory 379192 kb
Host smart-74f921a3-b8ea-4bb2-b8b8-3752dbf73e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2278705182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.2278705182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.2996572586
Short name T940
Test name
Test status
Simulation time 320002230281 ps
CPU time 1836.76 seconds
Started Jul 09 05:53:52 PM PDT 24
Finished Jul 09 06:24:29 PM PDT 24
Peak memory 378640 kb
Host smart-30047d62-6246-4379-8ccc-7c64a3f95b35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2996572586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2996572586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.4138081422
Short name T369
Test name
Test status
Simulation time 142316794429 ps
CPU time 1409.17 seconds
Started Jul 09 05:53:53 PM PDT 24
Finished Jul 09 06:17:22 PM PDT 24
Peak memory 338232 kb
Host smart-9f2ae484-39ef-4dfc-a922-08583475c8b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4138081422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.4138081422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.43220501
Short name T805
Test name
Test status
Simulation time 33995819274 ps
CPU time 946.39 seconds
Started Jul 09 05:53:54 PM PDT 24
Finished Jul 09 06:09:41 PM PDT 24
Peak memory 295012 kb
Host smart-3a830764-50b2-4dd1-b4ad-f7e6b104ecac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=43220501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.43220501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.1362387924
Short name T776
Test name
Test status
Simulation time 104572529095 ps
CPU time 3741.12 seconds
Started Jul 09 05:53:54 PM PDT 24
Finished Jul 09 06:56:17 PM PDT 24
Peak memory 658908 kb
Host smart-45b7f34f-967b-45d7-9b81-7cbcd5fd70e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1362387924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.1362387924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.2771901825
Short name T758
Test name
Test status
Simulation time 126035865141 ps
CPU time 3264.02 seconds
Started Jul 09 05:53:53 PM PDT 24
Finished Jul 09 06:48:18 PM PDT 24
Peak memory 552952 kb
Host smart-8558e0e3-71bf-448b-9f7d-6b3fdf40c828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2771901825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2771901825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.3649294490
Short name T1053
Test name
Test status
Simulation time 74265080 ps
CPU time 0.83 seconds
Started Jul 09 05:54:17 PM PDT 24
Finished Jul 09 05:54:19 PM PDT 24
Peak memory 205248 kb
Host smart-d9930c1f-6919-494a-ba68-316ac39c365f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649294490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3649294490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.3864509286
Short name T415
Test name
Test status
Simulation time 7832612786 ps
CPU time 184.15 seconds
Started Jul 09 05:54:11 PM PDT 24
Finished Jul 09 05:57:15 PM PDT 24
Peak memory 240084 kb
Host smart-861a46f3-e2ee-4dfa-8dd8-5115b789c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864509286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3864509286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.3714266497
Short name T811
Test name
Test status
Simulation time 89119528589 ps
CPU time 488.99 seconds
Started Jul 09 05:54:07 PM PDT 24
Finished Jul 09 06:02:16 PM PDT 24
Peak memory 228840 kb
Host smart-51dd4f3c-c65a-4857-ab55-fc7508f9eb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714266497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3714266497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.1309096310
Short name T536
Test name
Test status
Simulation time 17056548966 ps
CPU time 219.12 seconds
Started Jul 09 05:54:13 PM PDT 24
Finished Jul 09 05:57:53 PM PDT 24
Peak memory 244456 kb
Host smart-f6708de8-cc3c-4572-a1c4-8040bf7f00a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309096310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1309096310 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2721089276
Short name T696
Test name
Test status
Simulation time 8695618777 ps
CPU time 223.66 seconds
Started Jul 09 05:54:11 PM PDT 24
Finished Jul 09 05:57:55 PM PDT 24
Peak memory 243992 kb
Host smart-a52f1133-4b3d-41d0-972f-2d2e9f2da366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721089276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2721089276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.3012694543
Short name T21
Test name
Test status
Simulation time 4810831118 ps
CPU time 6.09 seconds
Started Jul 09 05:54:16 PM PDT 24
Finished Jul 09 05:54:22 PM PDT 24
Peak memory 215564 kb
Host smart-79ef00bd-11c6-4465-a21a-e80c093d3690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012694543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3012694543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.2690297130
Short name T1056
Test name
Test status
Simulation time 332644277 ps
CPU time 1.26 seconds
Started Jul 09 05:54:13 PM PDT 24
Finished Jul 09 05:54:15 PM PDT 24
Peak memory 215596 kb
Host smart-fb69773a-db2a-441e-8b15-24381c55fff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690297130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2690297130 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.785075958
Short name T570
Test name
Test status
Simulation time 45824915490 ps
CPU time 1369.23 seconds
Started Jul 09 05:54:07 PM PDT 24
Finished Jul 09 06:16:56 PM PDT 24
Peak memory 344044 kb
Host smart-3ed61de9-91b1-41ed-a595-0e8f75f1bb96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785075958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an
d_output.785075958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.4082613677
Short name T1067
Test name
Test status
Simulation time 2527774391 ps
CPU time 29.01 seconds
Started Jul 09 05:54:05 PM PDT 24
Finished Jul 09 05:54:35 PM PDT 24
Peak memory 219392 kb
Host smart-bd94c4b7-ae63-4a39-81fa-253ae9ab2018
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082613677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.4082613677 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.1497975229
Short name T862
Test name
Test status
Simulation time 416160600 ps
CPU time 5.82 seconds
Started Jul 09 05:54:05 PM PDT 24
Finished Jul 09 05:54:11 PM PDT 24
Peak memory 215632 kb
Host smart-fbeeee1f-2893-4037-8308-62bd118885e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497975229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1497975229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.845400780
Short name T465
Test name
Test status
Simulation time 74931862296 ps
CPU time 456.26 seconds
Started Jul 09 05:54:11 PM PDT 24
Finished Jul 09 06:01:48 PM PDT 24
Peak memory 290848 kb
Host smart-d431164c-ea3f-4de3-878b-604232c95414
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=845400780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.845400780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.2034079611
Short name T17
Test name
Test status
Simulation time 269300980 ps
CPU time 4.93 seconds
Started Jul 09 05:54:07 PM PDT 24
Finished Jul 09 05:54:12 PM PDT 24
Peak memory 215572 kb
Host smart-0a62f1e4-9c63-4141-b85a-a544cadb9275
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034079611 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.2034079611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2147698540
Short name T766
Test name
Test status
Simulation time 264543023 ps
CPU time 4.12 seconds
Started Jul 09 05:54:17 PM PDT 24
Finished Jul 09 05:54:22 PM PDT 24
Peak memory 215640 kb
Host smart-cf6a0d4f-34cb-4f84-b8ab-6f17f4e1157c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147698540 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2147698540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.3675411667
Short name T825
Test name
Test status
Simulation time 365993038166 ps
CPU time 1843.83 seconds
Started Jul 09 05:54:05 PM PDT 24
Finished Jul 09 06:24:49 PM PDT 24
Peak memory 392044 kb
Host smart-e63bd995-0523-4189-90d3-631ea5a5e5d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3675411667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.3675411667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.830081865
Short name T876
Test name
Test status
Simulation time 188307563813 ps
CPU time 2010.22 seconds
Started Jul 09 05:54:05 PM PDT 24
Finished Jul 09 06:27:36 PM PDT 24
Peak memory 377412 kb
Host smart-46a17489-9d98-42c2-9b13-aa96d36fc39c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=830081865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.830081865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.3079655094
Short name T790
Test name
Test status
Simulation time 48776136814 ps
CPU time 1295.74 seconds
Started Jul 09 05:54:08 PM PDT 24
Finished Jul 09 06:15:44 PM PDT 24
Peak memory 333716 kb
Host smart-bc38ffc0-dbd1-43dd-872d-8f6545d64bc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3079655094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3079655094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.3575351872
Short name T606
Test name
Test status
Simulation time 117135869333 ps
CPU time 827.18 seconds
Started Jul 09 05:54:08 PM PDT 24
Finished Jul 09 06:07:56 PM PDT 24
Peak memory 292520 kb
Host smart-353ee9f3-d78d-4939-b6dc-f6e9732a448e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3575351872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.3575351872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.3699228769
Short name T249
Test name
Test status
Simulation time 212101709476 ps
CPU time 4070.22 seconds
Started Jul 09 05:54:08 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 651072 kb
Host smart-14f7b681-a349-4d1b-a0a5-82f8af391b8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3699228769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.3699228769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.2242082883
Short name T982
Test name
Test status
Simulation time 151367162323 ps
CPU time 3932.56 seconds
Started Jul 09 05:54:08 PM PDT 24
Finished Jul 09 06:59:42 PM PDT 24
Peak memory 560432 kb
Host smart-7054caa7-2838-4efb-a8b8-5d06e8627e09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2242082883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2242082883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.1189552374
Short name T433
Test name
Test status
Simulation time 16619819 ps
CPU time 0.77 seconds
Started Jul 09 05:54:34 PM PDT 24
Finished Jul 09 05:54:35 PM PDT 24
Peak memory 205268 kb
Host smart-2d463edf-301d-41c3-a563-7fbea391ceaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189552374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1189552374 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.2976405422
Short name T155
Test name
Test status
Simulation time 8939234195 ps
CPU time 251.44 seconds
Started Jul 09 05:54:27 PM PDT 24
Finished Jul 09 05:58:38 PM PDT 24
Peak memory 247736 kb
Host smart-9a3230ef-dfd7-4831-a7a3-187fab2fb878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976405422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2976405422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.1653563880
Short name T527
Test name
Test status
Simulation time 94481258401 ps
CPU time 768.36 seconds
Started Jul 09 05:54:20 PM PDT 24
Finished Jul 09 06:07:09 PM PDT 24
Peak memory 230832 kb
Host smart-0099966a-564d-415e-859a-e8f365d4a6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653563880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1653563880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.939994627
Short name T252
Test name
Test status
Simulation time 9222711466 ps
CPU time 204.27 seconds
Started Jul 09 05:54:25 PM PDT 24
Finished Jul 09 05:57:50 PM PDT 24
Peak memory 239748 kb
Host smart-3bfb5d18-6018-49b1-bf14-b1f10ce925d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939994627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.939994627 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.399093463
Short name T1061
Test name
Test status
Simulation time 4724100905 ps
CPU time 132.15 seconds
Started Jul 09 05:54:29 PM PDT 24
Finished Jul 09 05:56:41 PM PDT 24
Peak memory 240308 kb
Host smart-9a3cec39-88e2-4aa8-8dbe-190db1d8136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399093463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.399093463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2792606341
Short name T684
Test name
Test status
Simulation time 7310287164 ps
CPU time 8.17 seconds
Started Jul 09 05:54:28 PM PDT 24
Finished Jul 09 05:54:36 PM PDT 24
Peak memory 207456 kb
Host smart-b5e700e1-bfff-4166-a9c3-f498e416c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792606341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2792606341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.2669550312
Short name T548
Test name
Test status
Simulation time 38670604 ps
CPU time 1.25 seconds
Started Jul 09 05:54:28 PM PDT 24
Finished Jul 09 05:54:30 PM PDT 24
Peak memory 215560 kb
Host smart-15629dff-1743-4f32-a5d8-8a22dd4b72de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669550312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2669550312 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3765665693
Short name T460
Test name
Test status
Simulation time 530824610 ps
CPU time 15.94 seconds
Started Jul 09 05:54:17 PM PDT 24
Finished Jul 09 05:54:34 PM PDT 24
Peak memory 215560 kb
Host smart-2c761f03-6df4-422f-8abc-9f65ce9b29c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765665693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3765665693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.2363865568
Short name T173
Test name
Test status
Simulation time 40939478075 ps
CPU time 207.97 seconds
Started Jul 09 05:54:18 PM PDT 24
Finished Jul 09 05:57:47 PM PDT 24
Peak memory 235348 kb
Host smart-e0e6ffa2-8588-46e4-8f9d-dd50b47f1db5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363865568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2363865568 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.3095334201
Short name T268
Test name
Test status
Simulation time 113097591 ps
CPU time 3.45 seconds
Started Jul 09 05:54:15 PM PDT 24
Finished Jul 09 05:54:19 PM PDT 24
Peak memory 215644 kb
Host smart-ce9c0339-4da5-49ba-b04a-4d322f43c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095334201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3095334201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.2683547688
Short name T760
Test name
Test status
Simulation time 135768909 ps
CPU time 4.49 seconds
Started Jul 09 05:54:22 PM PDT 24
Finished Jul 09 05:54:27 PM PDT 24
Peak memory 215632 kb
Host smart-e8a5c343-5409-49df-bed2-f7663dd6ece2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683547688 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.2683547688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3226437845
Short name T322
Test name
Test status
Simulation time 163573748 ps
CPU time 4.08 seconds
Started Jul 09 05:54:28 PM PDT 24
Finished Jul 09 05:54:32 PM PDT 24
Peak memory 215700 kb
Host smart-8ed06eb2-2320-4ba0-97d4-118b06c60f6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226437845 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3226437845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.3187410579
Short name T1040
Test name
Test status
Simulation time 198773442896 ps
CPU time 2031.02 seconds
Started Jul 09 05:54:23 PM PDT 24
Finished Jul 09 06:28:15 PM PDT 24
Peak memory 400356 kb
Host smart-8f311043-8237-417e-a331-e919b13fce7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3187410579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3187410579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.2575768439
Short name T420
Test name
Test status
Simulation time 361517319459 ps
CPU time 1989.67 seconds
Started Jul 09 05:54:23 PM PDT 24
Finished Jul 09 06:27:33 PM PDT 24
Peak memory 369848 kb
Host smart-5ac6438b-c94c-4e84-a37f-d239f0c65f6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2575768439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.2575768439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2784301499
Short name T472
Test name
Test status
Simulation time 51660929439 ps
CPU time 1325.28 seconds
Started Jul 09 05:54:22 PM PDT 24
Finished Jul 09 06:16:28 PM PDT 24
Peak memory 332828 kb
Host smart-82264768-02ae-48c9-80d3-c7743dc0e474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2784301499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2784301499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.329998245
Short name T463
Test name
Test status
Simulation time 39730775646 ps
CPU time 795 seconds
Started Jul 09 05:54:23 PM PDT 24
Finished Jul 09 06:07:38 PM PDT 24
Peak memory 295712 kb
Host smart-cf27cf3b-ac49-4e9d-a8a3-e1780b0e2ddb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=329998245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.329998245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.1718685198
Short name T405
Test name
Test status
Simulation time 271460992885 ps
CPU time 5433.44 seconds
Started Jul 09 05:54:22 PM PDT 24
Finished Jul 09 07:24:57 PM PDT 24
Peak memory 655896 kb
Host smart-c1fa5606-0fbb-4fad-8975-cae1b5ccb984
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1718685198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1718685198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.3334700327
Short name T863
Test name
Test status
Simulation time 63037348665 ps
CPU time 3410.19 seconds
Started Jul 09 05:54:23 PM PDT 24
Finished Jul 09 06:51:14 PM PDT 24
Peak memory 564588 kb
Host smart-b98c7d6e-5607-4ed2-9263-85b07dbddf15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3334700327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.3334700327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1820505448
Short name T566
Test name
Test status
Simulation time 107233608 ps
CPU time 0.78 seconds
Started Jul 09 05:54:45 PM PDT 24
Finished Jul 09 05:54:46 PM PDT 24
Peak memory 205304 kb
Host smart-f304a93a-55d2-4506-9029-53a9ce5e4dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820505448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1820505448 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.2393217666
Short name T910
Test name
Test status
Simulation time 179793263968 ps
CPU time 388.66 seconds
Started Jul 09 05:54:39 PM PDT 24
Finished Jul 09 06:01:08 PM PDT 24
Peak memory 247804 kb
Host smart-6ce24ab0-90a8-49a6-8273-a68f5bb4e407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393217666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2393217666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.1992648231
Short name T484
Test name
Test status
Simulation time 9494368394 ps
CPU time 413.26 seconds
Started Jul 09 05:54:43 PM PDT 24
Finished Jul 09 06:01:37 PM PDT 24
Peak memory 230864 kb
Host smart-893caff3-69a4-400d-9ccd-6f52cc0afaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992648231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1992648231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.3277366701
Short name T647
Test name
Test status
Simulation time 1424128211 ps
CPU time 24.96 seconds
Started Jul 09 05:54:40 PM PDT 24
Finished Jul 09 05:55:06 PM PDT 24
Peak memory 223932 kb
Host smart-669db955-9f9c-4b7c-ae69-5f977fd20df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277366701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3277366701 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.4060079802
Short name T30
Test name
Test status
Simulation time 73344077352 ps
CPU time 341.12 seconds
Started Jul 09 05:54:38 PM PDT 24
Finished Jul 09 06:00:20 PM PDT 24
Peak memory 249508 kb
Host smart-d4fc50c6-ae1b-492c-ad49-d610463514de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060079802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4060079802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.3221224252
Short name T510
Test name
Test status
Simulation time 3972599373 ps
CPU time 6.85 seconds
Started Jul 09 05:54:40 PM PDT 24
Finished Jul 09 05:54:47 PM PDT 24
Peak memory 207388 kb
Host smart-209852eb-6469-4ab9-96b6-85b10d2806b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221224252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3221224252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.705271258
Short name T57
Test name
Test status
Simulation time 31370830 ps
CPU time 1.26 seconds
Started Jul 09 05:54:41 PM PDT 24
Finished Jul 09 05:54:42 PM PDT 24
Peak memory 215484 kb
Host smart-65167e18-3f81-495c-8e3e-67cfc7bacacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705271258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.705271258 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.3909758142
Short name T293
Test name
Test status
Simulation time 89883993684 ps
CPU time 2734.89 seconds
Started Jul 09 05:54:34 PM PDT 24
Finished Jul 09 06:40:09 PM PDT 24
Peak memory 472288 kb
Host smart-af695e8b-9527-447b-8990-e66ff7624f5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909758142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.3909758142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.694778647
Short name T534
Test name
Test status
Simulation time 2756413551 ps
CPU time 220.8 seconds
Started Jul 09 05:54:32 PM PDT 24
Finished Jul 09 05:58:13 PM PDT 24
Peak memory 239280 kb
Host smart-8e99473b-f917-4e73-8b67-e1b4eb8d2fc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694778647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.694778647 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.3804062973
Short name T315
Test name
Test status
Simulation time 1821641647 ps
CPU time 45.8 seconds
Started Jul 09 05:54:32 PM PDT 24
Finished Jul 09 05:55:18 PM PDT 24
Peak memory 218884 kb
Host smart-589ab680-a08e-4c67-bedc-6ecadbe4ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804062973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.3804062973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.2211383593
Short name T798
Test name
Test status
Simulation time 30547524701 ps
CPU time 1134.4 seconds
Started Jul 09 05:54:41 PM PDT 24
Finished Jul 09 06:13:36 PM PDT 24
Peak memory 363436 kb
Host smart-97ea75cb-57fb-477b-87b3-42e88d515375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2211383593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2211383593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.1133217518
Short name T300
Test name
Test status
Simulation time 179031916 ps
CPU time 4.89 seconds
Started Jul 09 05:54:43 PM PDT 24
Finished Jul 09 05:54:48 PM PDT 24
Peak memory 215712 kb
Host smart-03351bae-2723-44f3-ac94-41e7e9e52502
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133217518 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.1133217518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2279420296
Short name T351
Test name
Test status
Simulation time 113497985 ps
CPU time 3.64 seconds
Started Jul 09 05:54:38 PM PDT 24
Finished Jul 09 05:54:42 PM PDT 24
Peak memory 215760 kb
Host smart-5f769ef0-30a1-4575-bad7-b240898dc1e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279420296 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2279420296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.3226631742
Short name T732
Test name
Test status
Simulation time 97455326670 ps
CPU time 1915.94 seconds
Started Jul 09 05:54:42 PM PDT 24
Finished Jul 09 06:26:39 PM PDT 24
Peak memory 393240 kb
Host smart-16cbae54-d49e-447d-9484-57ee883eea93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3226631742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.3226631742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.559828824
Short name T639
Test name
Test status
Simulation time 368752122681 ps
CPU time 1880.03 seconds
Started Jul 09 05:54:43 PM PDT 24
Finished Jul 09 06:26:04 PM PDT 24
Peak memory 376304 kb
Host smart-ed104182-49c6-47ce-bd72-7b2200cec9ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=559828824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.559828824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.236601412
Short name T371
Test name
Test status
Simulation time 313383150916 ps
CPU time 1370.81 seconds
Started Jul 09 05:54:42 PM PDT 24
Finished Jul 09 06:17:34 PM PDT 24
Peak memory 330064 kb
Host smart-f2230296-cd81-4144-9678-5aa6ba462cb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=236601412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.236601412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.1815782266
Short name T981
Test name
Test status
Simulation time 97508984922 ps
CPU time 1019.11 seconds
Started Jul 09 05:54:37 PM PDT 24
Finished Jul 09 06:11:36 PM PDT 24
Peak memory 297836 kb
Host smart-af936014-f903-40d0-af22-b1c8a1a568b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1815782266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.1815782266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.1897786421
Short name T529
Test name
Test status
Simulation time 3453368462148 ps
CPU time 4587.98 seconds
Started Jul 09 05:54:43 PM PDT 24
Finished Jul 09 07:11:12 PM PDT 24
Peak memory 654084 kb
Host smart-8b065634-462b-4a90-99c2-ac6f758533de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1897786421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1897786421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.1813989678
Short name T989
Test name
Test status
Simulation time 301678802792 ps
CPU time 3584.3 seconds
Started Jul 09 05:54:40 PM PDT 24
Finished Jul 09 06:54:25 PM PDT 24
Peak memory 558656 kb
Host smart-0d68c01e-221e-48f3-9226-fe819be77680
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1813989678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1813989678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.1969501746
Short name T875
Test name
Test status
Simulation time 108659209 ps
CPU time 0.8 seconds
Started Jul 09 05:54:55 PM PDT 24
Finished Jul 09 05:54:56 PM PDT 24
Peak memory 205244 kb
Host smart-42c01833-0427-40fd-b075-98cd20ac9645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969501746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1969501746 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.2901189681
Short name T954
Test name
Test status
Simulation time 1760994630 ps
CPU time 25.79 seconds
Started Jul 09 05:54:52 PM PDT 24
Finished Jul 09 05:55:18 PM PDT 24
Peak memory 218800 kb
Host smart-285b9452-0868-4146-ac6e-7a3d16bc056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901189681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2901189681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.3806835916
Short name T705
Test name
Test status
Simulation time 5599927467 ps
CPU time 439.67 seconds
Started Jul 09 05:54:49 PM PDT 24
Finished Jul 09 06:02:09 PM PDT 24
Peak memory 231152 kb
Host smart-c8bb2edb-e006-4963-aed5-2a7936c5ea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806835916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3806835916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.1253864179
Short name T768
Test name
Test status
Simulation time 1174353144 ps
CPU time 35.04 seconds
Started Jul 09 05:54:52 PM PDT 24
Finished Jul 09 05:55:27 PM PDT 24
Peak memory 221056 kb
Host smart-94b7146c-df05-4e33-a3ae-265910aed64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253864179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1253864179 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.2371598872
Short name T985
Test name
Test status
Simulation time 8818386929 ps
CPU time 235.64 seconds
Started Jul 09 05:54:51 PM PDT 24
Finished Jul 09 05:58:47 PM PDT 24
Peak memory 256660 kb
Host smart-d5064307-5043-46e8-9fa2-662823eccde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371598872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2371598872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.36921792
Short name T519
Test name
Test status
Simulation time 872109025 ps
CPU time 3.02 seconds
Started Jul 09 05:54:52 PM PDT 24
Finished Jul 09 05:54:56 PM PDT 24
Peak memory 207276 kb
Host smart-279a8b1b-a7ea-4fbd-ab3e-a95268a5f627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36921792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.36921792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.1281776613
Short name T340
Test name
Test status
Simulation time 51401600782 ps
CPU time 755.77 seconds
Started Jul 09 05:54:41 PM PDT 24
Finished Jul 09 06:07:17 PM PDT 24
Peak memory 291932 kb
Host smart-b799b22d-bd94-4676-9624-4a54cb0354bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281776613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.1281776613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.4189650778
Short name T860
Test name
Test status
Simulation time 105052144389 ps
CPU time 254.31 seconds
Started Jul 09 05:54:45 PM PDT 24
Finished Jul 09 05:59:00 PM PDT 24
Peak memory 240112 kb
Host smart-f6db371f-1446-4845-ba87-6a791d567144
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189650778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.4189650778 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.2233160250
Short name T681
Test name
Test status
Simulation time 723926200 ps
CPU time 36.12 seconds
Started Jul 09 05:54:44 PM PDT 24
Finished Jul 09 05:55:20 PM PDT 24
Peak memory 218844 kb
Host smart-e803490b-7427-492c-b595-1b4fba2aff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233160250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2233160250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.829390727
Short name T697
Test name
Test status
Simulation time 841789961 ps
CPU time 4.56 seconds
Started Jul 09 05:54:51 PM PDT 24
Finished Jul 09 05:54:55 PM PDT 24
Peak memory 215612 kb
Host smart-39a96b9e-a0dd-497e-baf0-fe1d24d67212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829390727 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.kmac_test_vectors_kmac.829390727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3126078416
Short name T1009
Test name
Test status
Simulation time 639460863 ps
CPU time 5.02 seconds
Started Jul 09 05:54:49 PM PDT 24
Finished Jul 09 05:54:54 PM PDT 24
Peak memory 215612 kb
Host smart-df19deee-0d3c-42c7-9562-db63fb8851e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126078416 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3126078416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.3848518885
Short name T823
Test name
Test status
Simulation time 19474503564 ps
CPU time 1456.68 seconds
Started Jul 09 05:54:44 PM PDT 24
Finished Jul 09 06:19:02 PM PDT 24
Peak memory 377484 kb
Host smart-ee71ebb5-21dc-4644-bb76-8f46b5a5de9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3848518885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.3848518885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.1929840947
Short name T990
Test name
Test status
Simulation time 17771126915 ps
CPU time 1518.82 seconds
Started Jul 09 05:54:46 PM PDT 24
Finished Jul 09 06:20:05 PM PDT 24
Peak memory 371548 kb
Host smart-dd927bea-87d3-4aa2-999f-68e9c7aa36ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1929840947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.1929840947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1289755303
Short name T658
Test name
Test status
Simulation time 68875852355 ps
CPU time 1434.15 seconds
Started Jul 09 05:54:44 PM PDT 24
Finished Jul 09 06:18:39 PM PDT 24
Peak memory 329744 kb
Host smart-df36d252-a39e-4fae-adaf-d004d1b643bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1289755303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1289755303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.1507291110
Short name T901
Test name
Test status
Simulation time 33327546432 ps
CPU time 879.55 seconds
Started Jul 09 05:54:44 PM PDT 24
Finished Jul 09 06:09:24 PM PDT 24
Peak memory 298980 kb
Host smart-0c815f4d-1d13-44a8-8e0a-df754899e38d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1507291110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1507291110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3213397167
Short name T917
Test name
Test status
Simulation time 1032428922197 ps
CPU time 4537.18 seconds
Started Jul 09 05:54:48 PM PDT 24
Finished Jul 09 07:10:26 PM PDT 24
Peak memory 657412 kb
Host smart-1459fcc0-023f-420c-ae11-60dc4ffe04c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3213397167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3213397167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.3532258753
Short name T866
Test name
Test status
Simulation time 148594051376 ps
CPU time 3868.81 seconds
Started Jul 09 05:54:48 PM PDT 24
Finished Jul 09 06:59:18 PM PDT 24
Peak memory 562908 kb
Host smart-d42084a6-99bd-4668-ad0c-8f9c3aa48536
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3532258753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3532258753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.3282787019
Short name T1008
Test name
Test status
Simulation time 161271944 ps
CPU time 0.74 seconds
Started Jul 09 05:55:13 PM PDT 24
Finished Jul 09 05:55:15 PM PDT 24
Peak memory 205360 kb
Host smart-bab68f9d-bdbd-4333-9ea6-f55e227cf132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282787019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3282787019 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1968033274
Short name T211
Test name
Test status
Simulation time 15373076097 ps
CPU time 178.19 seconds
Started Jul 09 05:55:06 PM PDT 24
Finished Jul 09 05:58:05 PM PDT 24
Peak memory 236124 kb
Host smart-353ea173-869f-4e7b-bde5-3c24d77fdf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968033274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1968033274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.938276494
Short name T43
Test name
Test status
Simulation time 1263545076 ps
CPU time 100.64 seconds
Started Jul 09 05:55:01 PM PDT 24
Finished Jul 09 05:56:42 PM PDT 24
Peak memory 221996 kb
Host smart-9235de31-be85-4119-9211-c25fa9623e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938276494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.938276494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.4067961583
Short name T934
Test name
Test status
Simulation time 22872179824 ps
CPU time 174.99 seconds
Started Jul 09 05:55:11 PM PDT 24
Finished Jul 09 05:58:06 PM PDT 24
Peak memory 238692 kb
Host smart-02408d95-7746-4ffa-8222-1b12078b7148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067961583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.4067961583 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_key_error.1744514586
Short name T1004
Test name
Test status
Simulation time 1450320220 ps
CPU time 2.46 seconds
Started Jul 09 05:55:09 PM PDT 24
Finished Jul 09 05:55:12 PM PDT 24
Peak memory 215524 kb
Host smart-7348b572-fdb5-4617-88af-5071c3b1470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744514586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1744514586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.858780165
Short name T212
Test name
Test status
Simulation time 430579399 ps
CPU time 5.35 seconds
Started Jul 09 05:55:08 PM PDT 24
Finished Jul 09 05:55:14 PM PDT 24
Peak memory 220560 kb
Host smart-2f6c72ed-3bc7-4fcd-b636-b0c3d7307fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858780165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.858780165 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1921695350
Short name T638
Test name
Test status
Simulation time 362888165923 ps
CPU time 2067.25 seconds
Started Jul 09 05:54:54 PM PDT 24
Finished Jul 09 06:29:22 PM PDT 24
Peak memory 401828 kb
Host smart-e9dbc4ed-2717-4e16-8445-9c535823f1f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921695350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1921695350 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.2623332200
Short name T295
Test name
Test status
Simulation time 2828463660 ps
CPU time 102.36 seconds
Started Jul 09 05:54:55 PM PDT 24
Finished Jul 09 05:56:38 PM PDT 24
Peak memory 229940 kb
Host smart-01d9c519-b5f5-4893-9d10-c86a1aacdea3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623332200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2623332200 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.419310283
Short name T1044
Test name
Test status
Simulation time 1464813482 ps
CPU time 18.01 seconds
Started Jul 09 05:54:56 PM PDT 24
Finished Jul 09 05:55:14 PM PDT 24
Peak memory 218864 kb
Host smart-014f3469-2a6b-459c-96a2-1fb6d8783314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419310283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.419310283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.3492180430
Short name T975
Test name
Test status
Simulation time 33386542187 ps
CPU time 567.06 seconds
Started Jul 09 05:55:12 PM PDT 24
Finished Jul 09 06:04:39 PM PDT 24
Peak memory 296464 kb
Host smart-1333c6d7-3877-444f-bc48-d3d6cdc61e4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3492180430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3492180430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.3343883643
Short name T874
Test name
Test status
Simulation time 243963798 ps
CPU time 4.48 seconds
Started Jul 09 05:55:04 PM PDT 24
Finished Jul 09 05:55:09 PM PDT 24
Peak memory 215676 kb
Host smart-6d039457-2666-4759-aacc-69cfa5bf72bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343883643 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.3343883643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1243896876
Short name T241
Test name
Test status
Simulation time 181021522 ps
CPU time 4.86 seconds
Started Jul 09 05:55:04 PM PDT 24
Finished Jul 09 05:55:09 PM PDT 24
Peak memory 215632 kb
Host smart-7cfb0249-0c35-4a4e-b834-4b9891b2bdb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243896876 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1243896876 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.2505448646
Short name T660
Test name
Test status
Simulation time 77985397741 ps
CPU time 1569.96 seconds
Started Jul 09 05:55:00 PM PDT 24
Finished Jul 09 06:21:10 PM PDT 24
Peak memory 389592 kb
Host smart-928c25be-dc87-4e4d-86ef-377c7cb8ce5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2505448646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.2505448646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.3672654429
Short name T343
Test name
Test status
Simulation time 184497174403 ps
CPU time 1783.14 seconds
Started Jul 09 05:55:02 PM PDT 24
Finished Jul 09 06:24:46 PM PDT 24
Peak memory 370092 kb
Host smart-eec502a8-2bef-4d16-aff2-289d20e7c598
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3672654429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3672654429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.4013041074
Short name T779
Test name
Test status
Simulation time 54249684407 ps
CPU time 1156.72 seconds
Started Jul 09 05:55:02 PM PDT 24
Finished Jul 09 06:14:20 PM PDT 24
Peak memory 333736 kb
Host smart-ccc1bc00-b44d-4a04-ab1e-d255cb533401
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4013041074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.4013041074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.3733485148
Short name T356
Test name
Test status
Simulation time 19459047756 ps
CPU time 769.51 seconds
Started Jul 09 05:55:03 PM PDT 24
Finished Jul 09 06:07:53 PM PDT 24
Peak memory 291764 kb
Host smart-7e663a33-f45c-4908-bccd-31265f9ebfef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3733485148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3733485148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.4225005334
Short name T190
Test name
Test status
Simulation time 53435894838 ps
CPU time 4434.07 seconds
Started Jul 09 05:55:04 PM PDT 24
Finished Jul 09 07:08:59 PM PDT 24
Peak memory 661404 kb
Host smart-c5bb1d02-953c-4f78-aa4d-1f39f508b8fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4225005334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.4225005334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.4123016753
Short name T435
Test name
Test status
Simulation time 87668768727 ps
CPU time 3459.97 seconds
Started Jul 09 05:55:06 PM PDT 24
Finished Jul 09 06:52:46 PM PDT 24
Peak memory 573356 kb
Host smart-f37a5121-1d49-4db9-83f7-c41fc398796b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4123016753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.4123016753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.3504626785
Short name T848
Test name
Test status
Simulation time 57289015 ps
CPU time 0.83 seconds
Started Jul 09 05:55:36 PM PDT 24
Finished Jul 09 05:55:37 PM PDT 24
Peak memory 205320 kb
Host smart-12d699e9-dd34-4596-b513-39a004b6e76e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504626785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3504626785 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.3613872838
Short name T29
Test name
Test status
Simulation time 10358372029 ps
CPU time 60.17 seconds
Started Jul 09 05:55:25 PM PDT 24
Finished Jul 09 05:56:26 PM PDT 24
Peak memory 226088 kb
Host smart-4d20ee6b-ebe1-4cae-9702-21990ea88b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613872838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3613872838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.934569891
Short name T459
Test name
Test status
Simulation time 104285605987 ps
CPU time 619.68 seconds
Started Jul 09 05:55:15 PM PDT 24
Finished Jul 09 06:05:35 PM PDT 24
Peak memory 230976 kb
Host smart-cb2988df-18fe-4c78-8930-eb3f4fa67d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934569891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.934569891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.4127074445
Short name T428
Test name
Test status
Simulation time 24298606299 ps
CPU time 292.72 seconds
Started Jul 09 05:55:30 PM PDT 24
Finished Jul 09 06:00:23 PM PDT 24
Peak memory 247512 kb
Host smart-5831e150-3433-4537-96a7-e8db282a7138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127074445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.4127074445 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.1306657610
Short name T797
Test name
Test status
Simulation time 31062354064 ps
CPU time 158.24 seconds
Started Jul 09 05:55:30 PM PDT 24
Finished Jul 09 05:58:08 PM PDT 24
Peak memory 240344 kb
Host smart-d300fddd-1145-4093-aab2-522f0658fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306657610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1306657610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.962036675
Short name T1047
Test name
Test status
Simulation time 128475997 ps
CPU time 1.03 seconds
Started Jul 09 05:55:29 PM PDT 24
Finished Jul 09 05:55:31 PM PDT 24
Peak memory 206108 kb
Host smart-688350cd-f6bd-458a-88b8-9a2df01ab7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962036675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.962036675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.1688050439
Short name T884
Test name
Test status
Simulation time 317491803 ps
CPU time 1.35 seconds
Started Jul 09 05:55:30 PM PDT 24
Finished Jul 09 05:55:32 PM PDT 24
Peak memory 215568 kb
Host smart-06d154fb-7236-45f0-9b47-257f55a44243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688050439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1688050439 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.4186498109
Short name T501
Test name
Test status
Simulation time 23659577760 ps
CPU time 2116.26 seconds
Started Jul 09 05:55:16 PM PDT 24
Finished Jul 09 06:30:33 PM PDT 24
Peak memory 441380 kb
Host smart-6b4177d7-4e23-4688-a875-928607d4b9b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186498109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.4186498109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.308952880
Short name T232
Test name
Test status
Simulation time 43059010702 ps
CPU time 252.79 seconds
Started Jul 09 05:55:16 PM PDT 24
Finished Jul 09 05:59:29 PM PDT 24
Peak memory 241336 kb
Host smart-ea7eb43a-8916-4b13-8c9f-2b8962c686bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308952880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.308952880 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.3067931477
Short name T225
Test name
Test status
Simulation time 912339934 ps
CPU time 20.05 seconds
Started Jul 09 05:55:15 PM PDT 24
Finished Jul 09 05:55:35 PM PDT 24
Peak memory 219416 kb
Host smart-c8548951-2290-4237-a45c-085811dc7ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067931477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.3067931477 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.2218116722
Short name T39
Test name
Test status
Simulation time 5862512560 ps
CPU time 466.01 seconds
Started Jul 09 05:55:29 PM PDT 24
Finished Jul 09 06:03:16 PM PDT 24
Peak memory 291668 kb
Host smart-1a9c5d65-ece4-4008-951a-14b988cdf202
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2218116722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2218116722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.1464832430
Short name T388
Test name
Test status
Simulation time 592563298 ps
CPU time 4.01 seconds
Started Jul 09 05:55:23 PM PDT 24
Finished Jul 09 05:55:27 PM PDT 24
Peak memory 215604 kb
Host smart-795b7ed5-b0d2-4d60-ba58-e2e9c21c17b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464832430 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.1464832430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.1662085180
Short name T626
Test name
Test status
Simulation time 67203266 ps
CPU time 3.83 seconds
Started Jul 09 05:55:25 PM PDT 24
Finished Jul 09 05:55:30 PM PDT 24
Peak memory 215752 kb
Host smart-ad0d24d9-c641-4aeb-9bed-55500b4a8012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662085180 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.1662085180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1479943355
Short name T707
Test name
Test status
Simulation time 42135915873 ps
CPU time 1596.05 seconds
Started Jul 09 05:55:19 PM PDT 24
Finished Jul 09 06:21:56 PM PDT 24
Peak memory 394172 kb
Host smart-91f1ef49-3175-4c9d-a696-644766211582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1479943355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1479943355 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.4231116079
Short name T951
Test name
Test status
Simulation time 110354009168 ps
CPU time 1464.43 seconds
Started Jul 09 05:55:19 PM PDT 24
Finished Jul 09 06:19:44 PM PDT 24
Peak memory 372644 kb
Host smart-6ecf4b4f-4a65-42a5-8aa4-e7f5bf10970d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4231116079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.4231116079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.3480996986
Short name T339
Test name
Test status
Simulation time 135610684925 ps
CPU time 1256.35 seconds
Started Jul 09 05:55:19 PM PDT 24
Finished Jul 09 06:16:16 PM PDT 24
Peak memory 328448 kb
Host smart-04204dc1-bcb3-45f6-81a8-05b58b97259e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3480996986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.3480996986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.3946112026
Short name T673
Test name
Test status
Simulation time 161427319939 ps
CPU time 915.65 seconds
Started Jul 09 05:55:22 PM PDT 24
Finished Jul 09 06:10:38 PM PDT 24
Peak memory 298924 kb
Host smart-01169968-e3f2-4c20-908f-7d03b8eb0def
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3946112026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.3946112026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.2930852911
Short name T1042
Test name
Test status
Simulation time 171538264253 ps
CPU time 4863.31 seconds
Started Jul 09 05:55:22 PM PDT 24
Finished Jul 09 07:16:26 PM PDT 24
Peak memory 647500 kb
Host smart-8003663d-db4f-4e5b-beca-9411a1e0340b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2930852911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.2930852911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3498678824
Short name T311
Test name
Test status
Simulation time 196436327197 ps
CPU time 3384.8 seconds
Started Jul 09 05:55:22 PM PDT 24
Finished Jul 09 06:51:48 PM PDT 24
Peak memory 560768 kb
Host smart-32d32d1d-37e7-4f09-9b1b-2a5d12e3c6c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3498678824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3498678824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1845086983
Short name T624
Test name
Test status
Simulation time 23679457 ps
CPU time 0.76 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:49:43 PM PDT 24
Peak memory 205320 kb
Host smart-2d41527d-15a0-4f49-86d0-f3136d93aaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845086983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1845086983 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.1352780478
Short name T819
Test name
Test status
Simulation time 6599862835 ps
CPU time 204.52 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 05:53:09 PM PDT 24
Peak memory 242504 kb
Host smart-4ab718f2-f116-4fd7-8054-99868fac4eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352780478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1352780478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.2407733986
Short name T354
Test name
Test status
Simulation time 36475653319 ps
CPU time 168.32 seconds
Started Jul 09 05:49:57 PM PDT 24
Finished Jul 09 05:52:46 PM PDT 24
Peak memory 235352 kb
Host smart-d805d501-59ce-479f-9ad8-80132756529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407733986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2407733986 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.274402903
Short name T121
Test name
Test status
Simulation time 14464523487 ps
CPU time 451.12 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 05:57:15 PM PDT 24
Peak memory 229328 kb
Host smart-476f43c5-6fd3-402e-9137-1b811304a2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274402903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.274402903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.3948188530
Short name T424
Test name
Test status
Simulation time 1011054486 ps
CPU time 26.96 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 05:50:02 PM PDT 24
Peak memory 219952 kb
Host smart-8cb8920c-4f6e-49f3-b2b7-cf64c6cb8155
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3948188530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3948188530 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.2453912814
Short name T445
Test name
Test status
Simulation time 1160689471 ps
CPU time 19.68 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 05:50:02 PM PDT 24
Peak memory 217384 kb
Host smart-661b6189-1080-4544-98d9-37d34d2079bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453912814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2453912814 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2982450023
Short name T45
Test name
Test status
Simulation time 1570559135 ps
CPU time 17.27 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:50:00 PM PDT 24
Peak memory 223804 kb
Host smart-ab7b1acb-e66f-4aca-9b49-38ca84e4840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982450023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2982450023 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.1171830558
Short name T749
Test name
Test status
Simulation time 3538959916 ps
CPU time 158.3 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 05:52:10 PM PDT 24
Peak memory 236580 kb
Host smart-2e47e473-5f12-4e3f-b5d5-cc8250a63dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171830558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1171830558 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.2090632603
Short name T383
Test name
Test status
Simulation time 101315883318 ps
CPU time 248.68 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 05:53:49 PM PDT 24
Peak memory 249724 kb
Host smart-55881ecc-92f2-404c-a26a-1ff1ce35b368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090632603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2090632603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.1223057409
Short name T490
Test name
Test status
Simulation time 1112033855 ps
CPU time 3.86 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:49:54 PM PDT 24
Peak memory 207376 kb
Host smart-9262ab68-b99d-417d-8ee5-ee722097c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223057409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1223057409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.2085860547
Short name T8
Test name
Test status
Simulation time 98768728 ps
CPU time 1.32 seconds
Started Jul 09 05:49:31 PM PDT 24
Finished Jul 09 05:49:33 PM PDT 24
Peak memory 220420 kb
Host smart-a9ee0c63-6338-4216-9b54-bd3c51eef84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085860547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2085860547 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.4045748226
Short name T726
Test name
Test status
Simulation time 10822541131 ps
CPU time 868.03 seconds
Started Jul 09 05:49:34 PM PDT 24
Finished Jul 09 06:04:03 PM PDT 24
Peak memory 321216 kb
Host smart-caa764fe-b755-4ba5-8a95-e30bf0ceee98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045748226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.4045748226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.4106946581
Short name T938
Test name
Test status
Simulation time 11643540005 ps
CPU time 118.6 seconds
Started Jul 09 05:49:28 PM PDT 24
Finished Jul 09 05:51:28 PM PDT 24
Peak memory 234732 kb
Host smart-e806d89c-08af-4116-8413-faf4ec4f03ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106946581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.4106946581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.3547022732
Short name T398
Test name
Test status
Simulation time 23233475891 ps
CPU time 232.34 seconds
Started Jul 09 05:49:51 PM PDT 24
Finished Jul 09 05:53:47 PM PDT 24
Peak memory 242092 kb
Host smart-f03eaf28-1fb0-4f15-a1c3-df048d24a278
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547022732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3547022732 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.92705994
Short name T377
Test name
Test status
Simulation time 1706684211 ps
CPU time 36.57 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 05:50:17 PM PDT 24
Peak memory 221736 kb
Host smart-18137d42-b15f-47ec-a953-763d5b57dd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92705994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.92705994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.3658036938
Short name T773
Test name
Test status
Simulation time 135388247003 ps
CPU time 810.92 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 06:03:15 PM PDT 24
Peak memory 298924 kb
Host smart-c6df6426-3dea-4419-a060-12204f4e050f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3658036938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3658036938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.441856715
Short name T755
Test name
Test status
Simulation time 306882122 ps
CPU time 3.84 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 05:49:46 PM PDT 24
Peak memory 215704 kb
Host smart-3fcadda5-a60d-4e7b-9c0f-946d9380268d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441856715 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.kmac_test_vectors_kmac.441856715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.1894363089
Short name T1052
Test name
Test status
Simulation time 311662706 ps
CPU time 4.88 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 05:49:44 PM PDT 24
Peak memory 215648 kb
Host smart-63a79c03-e625-4e20-8afb-68c9cca7621f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894363089 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.1894363089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.3334121269
Short name T206
Test name
Test status
Simulation time 78455882834 ps
CPU time 1534.82 seconds
Started Jul 09 05:49:25 PM PDT 24
Finished Jul 09 06:15:01 PM PDT 24
Peak memory 392016 kb
Host smart-159abe16-de0b-478c-a34e-1b5ffc9ef8c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3334121269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.3334121269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.301971681
Short name T984
Test name
Test status
Simulation time 256449720849 ps
CPU time 1809.49 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 06:19:42 PM PDT 24
Peak memory 376488 kb
Host smart-2dbb7627-0b5c-4892-930b-8a28712e03e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=301971681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.301971681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.196729098
Short name T595
Test name
Test status
Simulation time 771458916737 ps
CPU time 1500.3 seconds
Started Jul 09 05:49:38 PM PDT 24
Finished Jul 09 06:14:39 PM PDT 24
Peak memory 331860 kb
Host smart-691db448-d77a-4f2b-ae7c-ed00af56b170
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=196729098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.196729098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.2701443928
Short name T406
Test name
Test status
Simulation time 182129514060 ps
CPU time 895.24 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 06:04:39 PM PDT 24
Peak memory 293172 kb
Host smart-5af9fd9a-0c1e-48e6-9261-f71aaf4278ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2701443928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2701443928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.612389903
Short name T553
Test name
Test status
Simulation time 255228316917 ps
CPU time 4676.19 seconds
Started Jul 09 05:49:52 PM PDT 24
Finished Jul 09 07:07:52 PM PDT 24
Peak memory 644728 kb
Host smart-c8860abd-db7e-4100-8c85-09aee4a2bfda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=612389903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.612389903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.1794932069
Short name T652
Test name
Test status
Simulation time 45871209401 ps
CPU time 3508.63 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:48:17 PM PDT 24
Peak memory 568396 kb
Host smart-5540cc71-a8b2-4216-8eff-ee747bfc8976
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1794932069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.1794932069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.1758504929
Short name T611
Test name
Test status
Simulation time 21214194 ps
CPU time 0.75 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 05:49:55 PM PDT 24
Peak memory 205356 kb
Host smart-46896fc5-a25e-4153-ac6a-d8afcab63165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758504929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1758504929 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.2989785762
Short name T753
Test name
Test status
Simulation time 7078078143 ps
CPU time 91.8 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:51:18 PM PDT 24
Peak memory 231388 kb
Host smart-d5e27934-964e-4de3-9121-f18c09c35b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989785762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2989785762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.2808090955
Short name T104
Test name
Test status
Simulation time 5018770585 ps
CPU time 57.09 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:49 PM PDT 24
Peak memory 224868 kb
Host smart-0e14540d-715d-4ed8-b280-58598eb2dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808090955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2808090955 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.2135742933
Short name T77
Test name
Test status
Simulation time 45067790683 ps
CPU time 670.03 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 06:01:02 PM PDT 24
Peak memory 231788 kb
Host smart-f3677de0-c508-4815-8403-cd0a55b820f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135742933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2135742933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3662171348
Short name T879
Test name
Test status
Simulation time 3864278094 ps
CPU time 23.62 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:50:12 PM PDT 24
Peak memory 223752 kb
Host smart-11de7ba0-7b3c-457b-afc8-1f884d2d57ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662171348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3662171348 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1200206716
Short name T231
Test name
Test status
Simulation time 6242910537 ps
CPU time 13.12 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:50:04 PM PDT 24
Peak memory 219692 kb
Host smart-cade4135-2938-4b10-8a90-be74244587dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200206716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1200206716 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.3213731201
Short name T556
Test name
Test status
Simulation time 17749070929 ps
CPU time 35.8 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 05:50:17 PM PDT 24
Peak memory 215700 kb
Host smart-d6e98de8-af82-4169-9adc-7ec38adcd10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213731201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3213731201 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.3537060447
Short name T303
Test name
Test status
Simulation time 4772151029 ps
CPU time 242.34 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:53:53 PM PDT 24
Peak memory 244324 kb
Host smart-d9496656-b8dc-43fd-90d3-91755c9345c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537060447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3537060447 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3686200446
Short name T854
Test name
Test status
Simulation time 1465505265 ps
CPU time 7.52 seconds
Started Jul 09 05:49:36 PM PDT 24
Finished Jul 09 05:49:44 PM PDT 24
Peak memory 220324 kb
Host smart-50b5977f-cf72-4acb-993f-96e2f771a265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686200446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3686200446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.4134095235
Short name T476
Test name
Test status
Simulation time 414067882 ps
CPU time 2.72 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:49:48 PM PDT 24
Peak memory 207332 kb
Host smart-4417fd8c-8f7a-43bc-833f-ae8531b6ba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134095235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.4134095235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.3183517765
Short name T993
Test name
Test status
Simulation time 71770598907 ps
CPU time 545.82 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:58:56 PM PDT 24
Peak memory 271492 kb
Host smart-f00bebb0-ce13-4877-a430-7c912224f308
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183517765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.3183517765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.3319704157
Short name T86
Test name
Test status
Simulation time 5112498518 ps
CPU time 97.35 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:51:29 PM PDT 24
Peak memory 229888 kb
Host smart-e63a7388-74e3-469d-892d-fa9021807283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319704157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3319704157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.2744333341
Short name T220
Test name
Test status
Simulation time 60534344557 ps
CPU time 295.83 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:54:46 PM PDT 24
Peak memory 239404 kb
Host smart-176f3ba7-4223-487a-bed9-5c2ee7f1db2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744333341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2744333341 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.3687829
Short name T357
Test name
Test status
Simulation time 3452734140 ps
CPU time 44.77 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 05:50:24 PM PDT 24
Peak memory 216756 kb
Host smart-04b9b812-9a30-4b8e-8e5d-d6a245128a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3687829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.2173839506
Short name T105
Test name
Test status
Simulation time 74651184700 ps
CPU time 1247.71 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 06:10:33 PM PDT 24
Peak memory 342884 kb
Host smart-165beec8-06a6-41ae-9269-b065af6d79a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2173839506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2173839506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3395386021
Short name T1035
Test name
Test status
Simulation time 720471129 ps
CPU time 4.64 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 05:50:00 PM PDT 24
Peak memory 215748 kb
Host smart-54f1246e-036c-4b67-9558-35ad937f3ac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395386021 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3395386021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.1550598369
Short name T68
Test name
Test status
Simulation time 70721082 ps
CPU time 3.97 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 05:49:59 PM PDT 24
Peak memory 215704 kb
Host smart-7a88c976-f0b4-4ad7-9174-b485748383f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550598369 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.1550598369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.2236430138
Short name T387
Test name
Test status
Simulation time 19421462500 ps
CPU time 1514.61 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 06:14:55 PM PDT 24
Peak memory 392948 kb
Host smart-cdfa8c15-1fab-454d-a6b7-8530083620a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2236430138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2236430138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3067945834
Short name T517
Test name
Test status
Simulation time 80839655725 ps
CPU time 1623.33 seconds
Started Jul 09 05:49:38 PM PDT 24
Finished Jul 09 06:16:42 PM PDT 24
Peak memory 366352 kb
Host smart-9654955f-7a24-4a75-a143-4cd37815f04a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3067945834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3067945834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.648852127
Short name T836
Test name
Test status
Simulation time 14616751030 ps
CPU time 1059.61 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 06:07:25 PM PDT 24
Peak memory 327932 kb
Host smart-4590c61d-9d7f-42e2-af92-f54318e950c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=648852127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.648852127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.2329360408
Short name T671
Test name
Test status
Simulation time 53752237700 ps
CPU time 800.72 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:03:09 PM PDT 24
Peak memory 298752 kb
Host smart-51867405-0112-4559-bf35-d2e6faa766d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2329360408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2329360408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.674049254
Short name T748
Test name
Test status
Simulation time 101072678431 ps
CPU time 4082.67 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 06:57:54 PM PDT 24
Peak memory 643812 kb
Host smart-35e76be9-22f9-400d-a851-4549badab4d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=674049254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.674049254 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.3699168769
Short name T314
Test name
Test status
Simulation time 579210557582 ps
CPU time 3787.9 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 06:53:00 PM PDT 24
Peak memory 557040 kb
Host smart-3008a3fa-c3a9-45d5-ae8a-f7f23851808d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3699168769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3699168769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3259674479
Short name T378
Test name
Test status
Simulation time 56827803 ps
CPU time 0.77 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:49:47 PM PDT 24
Peak memory 205340 kb
Host smart-7fb96807-783c-4907-8d08-af03c201cbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259674479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3259674479 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.2337279256
Short name T983
Test name
Test status
Simulation time 12555115439 ps
CPU time 174.86 seconds
Started Jul 09 05:49:54 PM PDT 24
Finished Jul 09 05:52:50 PM PDT 24
Peak memory 240808 kb
Host smart-9e8a754c-180f-4b03-bb38-adde03fb76d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337279256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2337279256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.562444010
Short name T434
Test name
Test status
Simulation time 12085387992 ps
CPU time 252.27 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:54:03 PM PDT 24
Peak memory 243864 kb
Host smart-c1836a44-f1d1-4866-b49f-fb7095818f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562444010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.562444010 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.3353674638
Short name T849
Test name
Test status
Simulation time 11282258558 ps
CPU time 224.84 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:53:30 PM PDT 24
Peak memory 226576 kb
Host smart-721699b5-e7fd-4d44-97f7-2f5047fa795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353674638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3353674638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1519222410
Short name T619
Test name
Test status
Simulation time 3418574315 ps
CPU time 20.22 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:50:07 PM PDT 24
Peak memory 223888 kb
Host smart-b824fb82-8ca9-4db0-9cf1-cada4fef92de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1519222410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1519222410 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.1936097725
Short name T914
Test name
Test status
Simulation time 302400867 ps
CPU time 21.72 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 05:50:18 PM PDT 24
Peak memory 224276 kb
Host smart-08bbebed-b06e-4daa-abb3-4353a7b6a776
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1936097725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1936097725 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.1807402696
Short name T1002
Test name
Test status
Simulation time 1533704846 ps
CPU time 14.01 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 05:50:15 PM PDT 24
Peak memory 215668 kb
Host smart-e406a454-8eac-4ebd-9d5f-4a860736bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807402696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1807402696 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.3337695676
Short name T607
Test name
Test status
Simulation time 1312804088 ps
CPU time 20.45 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 05:50:14 PM PDT 24
Peak memory 223648 kb
Host smart-c3b56018-ee03-452a-bde7-86e66f6b2199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337695676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3337695676 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.3220593782
Short name T28
Test name
Test status
Simulation time 4159597498 ps
CPU time 317.71 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 05:54:58 PM PDT 24
Peak memory 256020 kb
Host smart-f839d59d-f78c-46fb-8a93-eed7fd15cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220593782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3220593782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.3067593381
Short name T845
Test name
Test status
Simulation time 2244214360 ps
CPU time 3.68 seconds
Started Jul 09 05:49:32 PM PDT 24
Finished Jul 09 05:49:36 PM PDT 24
Peak memory 207240 kb
Host smart-8a36d503-1ee6-4b26-a746-8f0346c552ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067593381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3067593381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.462215040
Short name T936
Test name
Test status
Simulation time 78889887 ps
CPU time 1.2 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:49:53 PM PDT 24
Peak memory 215512 kb
Host smart-d374482b-43ab-4a6a-80a7-09f5e15ba0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462215040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.462215040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.1237489804
Short name T466
Test name
Test status
Simulation time 228067282347 ps
CPU time 2281.34 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 06:27:53 PM PDT 24
Peak memory 488116 kb
Host smart-d809e68d-3394-4c08-ae04-802a62d3be63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237489804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.1237489804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.3386318887
Short name T85
Test name
Test status
Simulation time 7578029376 ps
CPU time 116.65 seconds
Started Jul 09 05:49:43 PM PDT 24
Finished Jul 09 05:51:41 PM PDT 24
Peak memory 235024 kb
Host smart-8f207410-5fbc-44dd-bdd4-ddc8c1b35c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386318887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3386318887 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2002940487
Short name T366
Test name
Test status
Simulation time 5797656462 ps
CPU time 291.08 seconds
Started Jul 09 05:49:59 PM PDT 24
Finished Jul 09 05:54:51 PM PDT 24
Peak memory 247952 kb
Host smart-22e2ec83-9d5e-4cc3-a320-884bade6f9b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002940487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2002940487 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.257183839
Short name T15
Test name
Test status
Simulation time 4074505454 ps
CPU time 17.26 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 05:50:00 PM PDT 24
Peak memory 220768 kb
Host smart-22a63e5b-50c7-4be3-b328-bd2a2f05dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257183839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.257183839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3758675057
Short name T1016
Test name
Test status
Simulation time 30658155301 ps
CPU time 675.79 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 06:01:16 PM PDT 24
Peak memory 309072 kb
Host smart-1584d59e-2c5b-4d40-abfb-455b02e5abc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3758675057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3758675057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.1764094437
Short name T50
Test name
Test status
Simulation time 11249688555 ps
CPU time 272.19 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 05:54:08 PM PDT 24
Peak memory 252956 kb
Host smart-b6bb05fd-e298-4eab-b4a4-2adf10939182
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764094437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.1764094437 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.458688129
Short name T915
Test name
Test status
Simulation time 2091258325 ps
CPU time 5.37 seconds
Started Jul 09 05:50:04 PM PDT 24
Finished Jul 09 05:50:10 PM PDT 24
Peak memory 215612 kb
Host smart-db8cbb84-3129-4cfe-8e4b-dd6fcfd05c1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458688129 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.kmac_test_vectors_kmac.458688129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.1511484637
Short name T426
Test name
Test status
Simulation time 574370715 ps
CPU time 4.27 seconds
Started Jul 09 05:49:59 PM PDT 24
Finished Jul 09 05:50:04 PM PDT 24
Peak memory 215684 kb
Host smart-2f1f3555-acef-48d9-9703-82da214690a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511484637 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.1511484637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2821410905
Short name T236
Test name
Test status
Simulation time 78767590235 ps
CPU time 1482.11 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 06:14:35 PM PDT 24
Peak memory 392848 kb
Host smart-ce7e50ff-3946-435f-935b-06b021eb47c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2821410905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2821410905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3207145222
Short name T349
Test name
Test status
Simulation time 92858101037 ps
CPU time 1827.76 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:20:15 PM PDT 24
Peak memory 364812 kb
Host smart-9dd0a8b2-6896-4a07-8d94-f6a9dc6c3c97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3207145222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3207145222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3886781744
Short name T355
Test name
Test status
Simulation time 196869218086 ps
CPU time 1228.79 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 06:10:12 PM PDT 24
Peak memory 337492 kb
Host smart-f5ac0670-7c6b-4b7e-bf98-afb81e95f5d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3886781744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3886781744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.2232657613
Short name T346
Test name
Test status
Simulation time 139360912198 ps
CPU time 853.44 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:04:01 PM PDT 24
Peak memory 291764 kb
Host smart-30d7d58b-ba39-4c88-91e2-ab8e3414692c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2232657613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2232657613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.1692837899
Short name T474
Test name
Test status
Simulation time 346303537016 ps
CPU time 4575.65 seconds
Started Jul 09 05:50:11 PM PDT 24
Finished Jul 09 07:06:28 PM PDT 24
Peak memory 637676 kb
Host smart-e8a078f7-72a0-42d1-b785-4812b5b48deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1692837899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.1692837899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.1655737757
Short name T16
Test name
Test status
Simulation time 153651208527 ps
CPU time 3815.7 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 06:53:16 PM PDT 24
Peak memory 565360 kb
Host smart-c1b5b4f6-87b1-42ff-8685-5ceebee1771e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1655737757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1655737757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.142959292
Short name T457
Test name
Test status
Simulation time 22467095 ps
CPU time 0.79 seconds
Started Jul 09 05:49:58 PM PDT 24
Finished Jul 09 05:49:59 PM PDT 24
Peak memory 205352 kb
Host smart-a3df9193-66e3-4158-b141-905bb0e73298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142959292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.142959292 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.2324134102
Short name T558
Test name
Test status
Simulation time 4192341825 ps
CPU time 10.2 seconds
Started Jul 09 05:49:54 PM PDT 24
Finished Jul 09 05:50:06 PM PDT 24
Peak memory 221952 kb
Host smart-24b38016-ae50-4b28-938c-a7e94a1abdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324134102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2324134102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.3609973302
Short name T937
Test name
Test status
Simulation time 31508285083 ps
CPU time 138.61 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:52:04 PM PDT 24
Peak memory 232264 kb
Host smart-d7e21f11-0d7c-4d65-a33d-f99e8ceeaf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609973302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3609973302 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.4199985331
Short name T205
Test name
Test status
Simulation time 14298097640 ps
CPU time 306.96 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:54:54 PM PDT 24
Peak memory 226324 kb
Host smart-a5c44439-c197-4b86-b89f-3e1702425dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199985331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.4199985331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2748527992
Short name T389
Test name
Test status
Simulation time 7605881311 ps
CPU time 33.22 seconds
Started Jul 09 05:49:51 PM PDT 24
Finished Jul 09 05:50:28 PM PDT 24
Peak memory 219796 kb
Host smart-a6141b2f-2da2-4ef4-994a-14f46fa0409f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2748527992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2748527992 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2710689584
Short name T509
Test name
Test status
Simulation time 2601651541 ps
CPU time 22.21 seconds
Started Jul 09 05:49:39 PM PDT 24
Finished Jul 09 05:50:01 PM PDT 24
Peak memory 223788 kb
Host smart-84916f01-b563-4c44-8cd5-733c005a7e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710689584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2710689584 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.2562235031
Short name T46
Test name
Test status
Simulation time 26659964344 ps
CPU time 25.36 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:17 PM PDT 24
Peak memory 223764 kb
Host smart-b3d5c20e-938e-44a9-b066-85e2952e76bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562235031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2562235031 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.1559692624
Short name T871
Test name
Test status
Simulation time 982010909 ps
CPU time 12.13 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 05:50:13 PM PDT 24
Peak memory 215724 kb
Host smart-fb1cf53a-6b07-4255-93cd-04895a5ce899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559692624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1559692624 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.1344217602
Short name T729
Test name
Test status
Simulation time 13587236449 ps
CPU time 259.4 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:54:13 PM PDT 24
Peak memory 254392 kb
Host smart-64ff6d09-7774-4ec4-a93b-545f87fcb505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344217602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1344217602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.4059349266
Short name T23
Test name
Test status
Simulation time 438059521 ps
CPU time 3.03 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 05:49:59 PM PDT 24
Peak memory 207224 kb
Host smart-ecffb851-f549-4581-8c2d-351130e1fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059349266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.4059349266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.2793033862
Short name T58
Test name
Test status
Simulation time 61411774 ps
CPU time 1.15 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:49:53 PM PDT 24
Peak memory 215552 kb
Host smart-e0b2e597-78eb-4d0b-a6fe-221f1aae829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793033862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2793033862 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1410460296
Short name T740
Test name
Test status
Simulation time 92230287062 ps
CPU time 1898.89 seconds
Started Jul 09 05:49:41 PM PDT 24
Finished Jul 09 06:21:21 PM PDT 24
Peak memory 429564 kb
Host smart-854f6071-c8be-449b-af7b-570014fce6ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410460296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1410460296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.4111290342
Short name T820
Test name
Test status
Simulation time 3139454631 ps
CPU time 169.32 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:52:40 PM PDT 24
Peak memory 238744 kb
Host smart-58ed164d-3914-40fd-8acb-e9fe2552b861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111290342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.4111290342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3418449670
Short name T662
Test name
Test status
Simulation time 8986140879 ps
CPU time 121.7 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:51:55 PM PDT 24
Peak memory 229404 kb
Host smart-22314e8c-b734-4ce3-8d50-e5e5c1b00c26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418449670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3418449670 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.1001741015
Short name T305
Test name
Test status
Simulation time 622403821 ps
CPU time 3.61 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 05:49:59 PM PDT 24
Peak memory 223716 kb
Host smart-1e60840f-0b25-4ae0-a2ec-e6d964ade279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001741015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1001741015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.3373765539
Short name T742
Test name
Test status
Simulation time 112587763454 ps
CPU time 2484.51 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:31:14 PM PDT 24
Peak memory 458032 kb
Host smart-ad7ba056-a9bd-4703-80c8-a0e3ddc63ad3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3373765539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3373765539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.1067285949
Short name T943
Test name
Test status
Simulation time 1284174697 ps
CPU time 4.34 seconds
Started Jul 09 05:49:42 PM PDT 24
Finished Jul 09 05:49:48 PM PDT 24
Peak memory 215540 kb
Host smart-144f95c0-8c32-4091-8a9d-c836f9d48cdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067285949 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.1067285949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2336899778
Short name T833
Test name
Test status
Simulation time 241457648 ps
CPU time 4.65 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 05:49:52 PM PDT 24
Peak memory 215572 kb
Host smart-d55c9866-57fb-43f3-ad4f-2b3e25a25cba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336899778 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2336899778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2203615381
Short name T676
Test name
Test status
Simulation time 254244747716 ps
CPU time 1554.27 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 06:15:46 PM PDT 24
Peak memory 377456 kb
Host smart-768c42b8-104b-4316-a9fd-a4b52d6683d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2203615381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2203615381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.238371736
Short name T844
Test name
Test status
Simulation time 81750463561 ps
CPU time 1681.16 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 06:17:50 PM PDT 24
Peak memory 370300 kb
Host smart-ba3c61a0-0668-46ba-8310-a5dbe2b8b137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=238371736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.238371736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.1716160169
Short name T679
Test name
Test status
Simulation time 190948903475 ps
CPU time 1205.48 seconds
Started Jul 09 05:49:55 PM PDT 24
Finished Jul 09 06:10:02 PM PDT 24
Peak memory 327452 kb
Host smart-93e24d49-b6b8-407a-9df0-31e145e1f62e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1716160169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1716160169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.2704462298
Short name T630
Test name
Test status
Simulation time 49980331867 ps
CPU time 812.95 seconds
Started Jul 09 05:49:35 PM PDT 24
Finished Jul 09 06:03:09 PM PDT 24
Peak memory 294172 kb
Host smart-e5304326-fae5-4906-b945-5a23bef4ad71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2704462298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2704462298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.3855997467
Short name T382
Test name
Test status
Simulation time 254362632256 ps
CPU time 5377.58 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 07:19:39 PM PDT 24
Peak memory 641044 kb
Host smart-b5e18261-e45d-4aef-9204-20cc161cf73f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3855997467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.3855997467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.4197707304
Short name T250
Test name
Test status
Simulation time 149742321168 ps
CPU time 4057.37 seconds
Started Jul 09 05:49:40 PM PDT 24
Finished Jul 09 06:57:19 PM PDT 24
Peak memory 569532 kb
Host smart-aa560008-11f4-4600-9087-29f98c790bdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4197707304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.4197707304 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.3953889483
Short name T700
Test name
Test status
Simulation time 16487842 ps
CPU time 0.81 seconds
Started Jul 09 05:49:52 PM PDT 24
Finished Jul 09 05:49:56 PM PDT 24
Peak memory 205356 kb
Host smart-d574432f-90fd-4a2e-a364-3e801305bbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953889483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3953889483 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.2184119428
Short name T280
Test name
Test status
Simulation time 58369136772 ps
CPU time 277.59 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 05:54:38 PM PDT 24
Peak memory 244436 kb
Host smart-b280f733-aa85-4549-92d1-a74ba85715d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184119428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2184119428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.1328884108
Short name T456
Test name
Test status
Simulation time 1291845463 ps
CPU time 19.68 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:50:13 PM PDT 24
Peak memory 223904 kb
Host smart-47f5df2e-b3c6-4df0-b49f-69234a9a97b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328884108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1328884108 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.2675294700
Short name T540
Test name
Test status
Simulation time 29081746269 ps
CPU time 538.05 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:58:52 PM PDT 24
Peak memory 230280 kb
Host smart-fd695993-582c-4a4e-8d99-28230d40be8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675294700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2675294700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2651633505
Short name T723
Test name
Test status
Simulation time 5545689174 ps
CPU time 29.96 seconds
Started Jul 09 05:50:00 PM PDT 24
Finished Jul 09 05:50:30 PM PDT 24
Peak memory 223708 kb
Host smart-d501c98f-d151-41b5-85a1-a04c73491b3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2651633505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2651633505 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.192815597
Short name T283
Test name
Test status
Simulation time 608040409 ps
CPU time 19.23 seconds
Started Jul 09 05:49:51 PM PDT 24
Finished Jul 09 05:50:14 PM PDT 24
Peak memory 218144 kb
Host smart-55ac6bce-ddd2-45a9-b17d-1a1653ad9885
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=192815597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.192815597 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1432089137
Short name T656
Test name
Test status
Simulation time 2784697473 ps
CPU time 17.86 seconds
Started Jul 09 05:49:50 PM PDT 24
Finished Jul 09 05:50:12 PM PDT 24
Peak memory 215704 kb
Host smart-549258fd-156a-4d7e-8320-e2221bf634bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432089137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1432089137 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.887930486
Short name T399
Test name
Test status
Simulation time 190246875423 ps
CPU time 276.78 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:54:24 PM PDT 24
Peak memory 238300 kb
Host smart-eb0cf3b4-ff61-4867-865f-58f89bfd7962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887930486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.887930486 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.3443986724
Short name T770
Test name
Test status
Simulation time 24654023352 ps
CPU time 249.52 seconds
Started Jul 09 05:49:58 PM PDT 24
Finished Jul 09 05:54:07 PM PDT 24
Peak memory 250104 kb
Host smart-9fc79f46-5b48-48c0-9ab6-121dcf8f1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443986724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3443986724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.3796673911
Short name T410
Test name
Test status
Simulation time 1303218752 ps
CPU time 6.81 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:50:00 PM PDT 24
Peak memory 207344 kb
Host smart-074ba24a-909d-4b82-a88a-543b1c74e424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796673911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3796673911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.346193809
Short name T91
Test name
Test status
Simulation time 99020601 ps
CPU time 1.2 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:49:52 PM PDT 24
Peak memory 215548 kb
Host smart-9cb248e0-fae9-4583-b1e6-51ec48b9a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346193809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.346193809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.3549506380
Short name T1072
Test name
Test status
Simulation time 36396219220 ps
CPU time 817.09 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 06:03:32 PM PDT 24
Peak memory 310336 kb
Host smart-5524d198-38db-4ab0-9cf3-cb8cfc8b3c23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549506380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.3549506380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.395040012
Short name T952
Test name
Test status
Simulation time 5844368115 ps
CPU time 64.51 seconds
Started Jul 09 05:49:49 PM PDT 24
Finished Jul 09 05:50:58 PM PDT 24
Peak memory 225780 kb
Host smart-79654722-2a9a-4d00-b0c0-32e5f07aa5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395040012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.395040012 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.1942958690
Short name T1075
Test name
Test status
Simulation time 137107131359 ps
CPU time 381.36 seconds
Started Jul 09 05:49:45 PM PDT 24
Finished Jul 09 05:56:10 PM PDT 24
Peak memory 249664 kb
Host smart-0054ffa5-03b1-4bf5-81eb-2abbb22b7252
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942958690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1942958690 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1004678542
Short name T233
Test name
Test status
Simulation time 6281013451 ps
CPU time 45.83 seconds
Started Jul 09 05:49:46 PM PDT 24
Finished Jul 09 05:50:36 PM PDT 24
Peak memory 215936 kb
Host smart-eb877c47-cd81-4d12-82bd-abba6a385491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004678542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1004678542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3452973825
Short name T870
Test name
Test status
Simulation time 13199035799 ps
CPU time 48.06 seconds
Started Jul 09 05:49:47 PM PDT 24
Finished Jul 09 05:50:40 PM PDT 24
Peak memory 233888 kb
Host smart-ebce353b-eeca-4cfa-9327-6d4572ff68c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3452973825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3452973825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.2048286086
Short name T209
Test name
Test status
Simulation time 254501351 ps
CPU time 5.31 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:49:58 PM PDT 24
Peak memory 215592 kb
Host smart-d9beea3c-eb95-4f63-9c2b-7c6bf1d35b72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048286086 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.2048286086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3450257618
Short name T223
Test name
Test status
Simulation time 990002656 ps
CPU time 4.9 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 05:49:57 PM PDT 24
Peak memory 215652 kb
Host smart-2008e23b-4f38-4c9d-a763-a81fa3410a8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450257618 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3450257618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.2819478221
Short name T1076
Test name
Test status
Simulation time 37962137667 ps
CPU time 1604.45 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 06:16:31 PM PDT 24
Peak memory 394896 kb
Host smart-2a96af67-17db-439a-9c36-9b4795adc8b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2819478221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.2819478221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.470353071
Short name T392
Test name
Test status
Simulation time 370607779815 ps
CPU time 1758.83 seconds
Started Jul 09 05:49:44 PM PDT 24
Finished Jul 09 06:19:05 PM PDT 24
Peak memory 378900 kb
Host smart-bbae1d05-6132-488f-99ff-b2432c39c76d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=470353071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.470353071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.4172054157
Short name T1049
Test name
Test status
Simulation time 190076673541 ps
CPU time 1331.44 seconds
Started Jul 09 05:50:02 PM PDT 24
Finished Jul 09 06:12:14 PM PDT 24
Peak memory 338496 kb
Host smart-ad38654d-f3bf-4bc2-beba-389ee00df4e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4172054157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.4172054157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.985057163
Short name T764
Test name
Test status
Simulation time 132289155084 ps
CPU time 875.48 seconds
Started Jul 09 05:49:53 PM PDT 24
Finished Jul 09 06:04:31 PM PDT 24
Peak memory 296876 kb
Host smart-b040f9a4-a608-4fb4-bf1f-278d3063b796
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=985057163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.985057163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.2123951763
Short name T418
Test name
Test status
Simulation time 169260871389 ps
CPU time 4616.4 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 07:06:50 PM PDT 24
Peak memory 634472 kb
Host smart-0da11fc0-62e1-4486-a873-06e3063c038b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2123951763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.2123951763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.4073306128
Short name T334
Test name
Test status
Simulation time 223072751667 ps
CPU time 4271.28 seconds
Started Jul 09 05:49:48 PM PDT 24
Finished Jul 09 07:01:04 PM PDT 24
Peak memory 568700 kb
Host smart-24c330d3-b000-44df-b526-b6e93f5bdaeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4073306128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.4073306128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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