Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100601913	1			T1	160757		T3	160155		T13	15194
all_values[1]	100601913	1			T1	160757		T3	160155		T13	15194
all_values[2]	100601913	1			T1	160757		T3	160155		T13	15194

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

516207

1

T1

10

T3

20

T13

1

auto[1]

301289532

1

T1

482261

T3

480445

T13

45581

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300281100

1

T1

480897

T3

479124

T13

45171

auto[1]

1524639

1

T1

1374

T3

1341

T13

411

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	185207	1			T3	1		T14	17		T15	3
all_values[0]	auto[0]	auto[1]	2065	1			T3	2		T14	2		T15	4
all_values[0]	auto[1]	auto[0]	99908493	1			T1	160299		T3	159707		T13	15057
all_values[0]	auto[1]	auto[1]	506148	1			T1	458		T3	445		T13	137
all_values[1]	auto[0]	auto[0]	169028	1			T1	5		T14	4		T15	1
all_values[1]	auto[0]	auto[1]	1542	1			T1	2		T15	2		T59	3
all_values[1]	auto[1]	auto[0]	99924672	1			T1	160294		T3	159708		T13	15057
all_values[1]	auto[1]	auto[1]	506671	1			T1	456		T3	447		T13	137
all_values[2]	auto[0]	auto[0]	156964	1			T1	2		T3	11		T13	1
all_values[2]	auto[0]	auto[1]	1401	1			T1	1		T3	6		T14	7
all_values[2]	auto[1]	auto[0]	99936736	1			T1	160297		T3	159697		T13	15056
all_values[2]	auto[1]	auto[1]	506812	1			T1	457		T3	441		T13	137