Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336138 |
1 |
|
|
T1 |
620 |
|
T3 |
2 |
|
T13 |
2 |
auto[1] |
355242 |
1 |
|
|
T3 |
618 |
|
T13 |
238 |
|
T14 |
264 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172766 |
1 |
|
|
T1 |
138 |
|
T3 |
158 |
|
T13 |
53 |
lower_val |
170794 |
1 |
|
|
T1 |
150 |
|
T3 |
136 |
|
T13 |
62 |
zero_val |
1759 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345018 |
1 |
|
|
T1 |
296 |
|
T3 |
314 |
|
T13 |
120 |
lower_val |
346354 |
1 |
|
|
T1 |
324 |
|
T3 |
306 |
|
T13 |
120 |
zero_val |
8 |
1 |
|
|
T154 |
2 |
|
T155 |
2 |
|
T156 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42033 |
1 |
|
|
T1 |
64 |
|
T14 |
9 |
|
T15 |
625 |
higher_val |
higher_val |
auto[1] |
44237 |
1 |
|
|
T3 |
87 |
|
T13 |
25 |
|
T14 |
19 |
higher_val |
lower_val |
auto[0] |
41982 |
1 |
|
|
T1 |
74 |
|
T3 |
1 |
|
T14 |
17 |
higher_val |
lower_val |
auto[1] |
44514 |
1 |
|
|
T3 |
70 |
|
T13 |
28 |
|
T14 |
40 |
lower_val |
higher_val |
auto[0] |
41155 |
1 |
|
|
T1 |
64 |
|
T14 |
24 |
|
T15 |
561 |
lower_val |
higher_val |
auto[1] |
43804 |
1 |
|
|
T3 |
67 |
|
T13 |
30 |
|
T14 |
36 |
lower_val |
lower_val |
auto[0] |
41657 |
1 |
|
|
T1 |
86 |
|
T14 |
22 |
|
T15 |
603 |
lower_val |
lower_val |
auto[1] |
44174 |
1 |
|
|
T3 |
69 |
|
T13 |
32 |
|
T14 |
45 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T155 |
2 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T154 |
1 |
|
T157 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
665 |
1 |
|
|
T15 |
5 |
|
T16 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
231 |
1 |
|
|
T3 |
2 |
|
T14 |
1 |
|
T37 |
2 |
zero_val |
lower_val |
auto[0] |
641 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
222 |
1 |
|
|
T37 |
2 |
|
T158 |
2 |
|
T23 |
2 |